PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 24258 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT                                                                     0x1
PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 16868 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT                                                                     0x1
PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 18199 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT                                                                     0x1
PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 18074 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT                                                                     0x1
PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 5585 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x00000001
PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 5568 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 6356 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 6890 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1