PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 24257 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT                                                                     0x0
PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 16867 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT                                                                     0x0
PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 18198 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT                                                                     0x0
PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 18073 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT                                                                     0x0
PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 5583 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x00000000
PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 5566 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 6354 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 6888 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0