OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK 21215 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L
OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK 30196 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L
OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK 26854 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L