ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK 35838 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK                                                           0x0000000CL
ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK 32520 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK                                                           0x0000000CL