MPLL_SEQ_UCODE_1__INSTR5__SHIFT 11481 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x00000014
MPLL_SEQ_UCODE_1__INSTR5__SHIFT 9414 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x14
MPLL_SEQ_UCODE_1__INSTR5__SHIFT 10326 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x14