MPLL_SEQ_UCODE_1__INSTR4__SHIFT 11479 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x00000010
MPLL_SEQ_UCODE_1__INSTR4__SHIFT 9412 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x10
MPLL_SEQ_UCODE_1__INSTR4__SHIFT 10324 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x10