MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 11410 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x00000007L
MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 9641 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x7
MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 10555 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x7