MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 11347 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x0000001e
MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 9590 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x1e
MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 10504 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x1e