MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 11341 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x0000001a
MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 9582 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x1a
MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 10496 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x1a