MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 11339 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x00000019
MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 9580 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x19
MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 10494 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x19