MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 11335 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x00000016
MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 9574 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x16
MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 10488 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x16