MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 11333 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x00000015
MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 9572 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x15
MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 10486 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x15