MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 11325 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x00000010
MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 9562 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x10
MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 10476 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x10