MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 23950 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 20882 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L