MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 18907 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 23342 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 20274 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0