MP1_SMN_IH_SW_INT__VALID__SHIFT  482 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h #define MP1_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x0
MP1_SMN_IH_SW_INT__VALID__SHIFT  923 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h #define MP1_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
MP1_SMN_IH_SW_INT__VALID__SHIFT  478 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h #define MP1_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
MP1_SMN_IH_SW_INT__VALID__SHIFT  507 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h #define MP1_SMN_IH_SW_INT__VALID__SHIFT	0x0