MP1_P2CMSG_INTSTS__INTSTS3__SHIFT  640 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT                                                                     0x3
MP1_P2CMSG_INTSTS__INTSTS3__SHIFT  397 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT                                                                     0x3
MP1_P2CMSG_INTSTS__INTSTS3__SHIFT  625 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT                                                                     0x3
MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 1151 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT	0x3