MP1_P2CMSG_INTSTS__INTSTS2__SHIFT  639 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT                                                                     0x2
MP1_P2CMSG_INTSTS__INTSTS2__SHIFT  396 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT                                                                     0x2
MP1_P2CMSG_INTSTS__INTSTS2__SHIFT  624 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT                                                                     0x2
MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 1150 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT	0x2