MP1_P2CMSG_INTSTS__INTSTS1__SHIFT  638 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT                                                                     0x1
MP1_P2CMSG_INTSTS__INTSTS1__SHIFT  395 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT                                                                     0x1
MP1_P2CMSG_INTSTS__INTSTS1__SHIFT  623 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT                                                                     0x1
MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 1149 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT	0x1