MP1_P2CMSG_INTSTS__INTSTS0__SHIFT  637 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT                                                                     0x0
MP1_P2CMSG_INTSTS__INTSTS0__SHIFT  394 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT                                                                     0x0
MP1_P2CMSG_INTSTS__INTSTS0__SHIFT  622 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT                                                                     0x0
MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 1148 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h #define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT	0x0