MP0_SMN_IH_SW_INT__VALID__SHIFT  248 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h #define MP0_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x0
MP0_SMN_IH_SW_INT__VALID__SHIFT  255 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h #define MP0_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
MP0_SMN_IH_SW_INT__VALID__SHIFT  249 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h #define MP0_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
MP0_SMN_IH_SW_INT__VALID__SHIFT  253 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h #define MP0_SMN_IH_SW_INT__VALID__SHIFT	0x0