MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK  255 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h #define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK                                                             0x00000001L
MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK  260 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h #define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK	0x00000001L