MP0_SMN_C2PMSG_40__CONTENT__SHIFT   51 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
MP0_SMN_C2PMSG_40__CONTENT__SHIFT   52 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
MP0_SMN_C2PMSG_40__CONTENT__SHIFT   51 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
MP0_SMN_C2PMSG_40__CONTENT__SHIFT   51 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT	0x0