MP0_IH_SW_INT__ID_MASK  510 drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h #define MP0_IH_SW_INT__ID_MASK                                                                                0x000000FFL
MP0_IH_SW_INT__ID_MASK  495 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h #define MP0_IH_SW_INT__ID_MASK                                                                                0x000000FFL
MP0_IH_SW_INT__ID_MASK  974 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h #define MP0_IH_SW_INT__ID_MASK	0x000000FFL