MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK  392 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK                                                                0x0000FF00L
MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK  392 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK                                                                0x0000FF00L