MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 6832 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 6284 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 6880 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 13985 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18