MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 4824 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 3777 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_sh_mask.h #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 4276 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 4843 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT   26 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 10863 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5