MMCR1_TD_CP_DBG0SEL_SH 48 arch/powerpc/perf/power5+-pmu.c #define MMCR1_TD_CP_DBG0SEL_SH 54 MMCR1_TD_CP_DBG0SEL_SH 48 arch/powerpc/perf/power5-pmu.c #define MMCR1_TD_CP_DBG0SEL_SH 54 MMCR1_TD_CP_DBG0SEL_SH 52 arch/powerpc/perf/ppc970-pmu.c #define MMCR1_TD_CP_DBG0SEL_SH 50