MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT  274 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT  270 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT  270 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT  272 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT  270 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT  298 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10