MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 1604 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 1552 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 1714 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 2730 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8
MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 7758 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x00000008
MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 1568 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 2092 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8
MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT  655 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8
MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT  537 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8