1/* 2 * 3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 4 * 5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 6 * Copyright (c) 2006 ATI Technologies Inc. 7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 10 * 11 * Authors: 12 * Wu Fengguang <wfg@linux.intel.com> 13 * 14 * Maintained by: 15 * Wu Fengguang <wfg@linux.intel.com> 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License as published by the Free 19 * Software Foundation; either version 2 of the License, or (at your option) 20 * any later version. 21 * 22 * This program is distributed in the hope that it will be useful, but 23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 * for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software Foundation, 29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 30 */ 31 32#include <linux/init.h> 33#include <linux/delay.h> 34#include <linux/slab.h> 35#include <linux/module.h> 36#include <sound/core.h> 37#include <sound/jack.h> 38#include <sound/asoundef.h> 39#include <sound/tlv.h> 40#include <sound/hdaudio.h> 41#include <sound/hda_i915.h> 42#include "hda_codec.h" 43#include "hda_local.h" 44#include "hda_jack.h" 45 46static bool static_hdmi_pcm; 47module_param(static_hdmi_pcm, bool, 0644); 48MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 49 50#define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807) 51#define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808) 52#define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809) 53#define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a) 54#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \ 55 || is_skylake(codec) || is_broxton(codec)) 56 57#define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882) 58#define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883) 59#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec)) 60 61struct hdmi_spec_per_cvt { 62 hda_nid_t cvt_nid; 63 int assigned; 64 unsigned int channels_min; 65 unsigned int channels_max; 66 u32 rates; 67 u64 formats; 68 unsigned int maxbps; 69}; 70 71/* max. connections to a widget */ 72#define HDA_MAX_CONNECTIONS 32 73 74struct hdmi_spec_per_pin { 75 hda_nid_t pin_nid; 76 int num_mux_nids; 77 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 78 int mux_idx; 79 hda_nid_t cvt_nid; 80 81 struct hda_codec *codec; 82 struct hdmi_eld sink_eld; 83 struct mutex lock; 84 struct delayed_work work; 85 struct snd_kcontrol *eld_ctl; 86 int repoll_count; 87 bool setup; /* the stream has been set up by prepare callback */ 88 int channels; /* current number of channels */ 89 bool non_pcm; 90 bool chmap_set; /* channel-map override by ALSA API? */ 91 unsigned char chmap[8]; /* ALSA API channel-map */ 92#ifdef CONFIG_SND_PROC_FS 93 struct snd_info_entry *proc_entry; 94#endif 95}; 96 97struct cea_channel_speaker_allocation; 98 99/* operations used by generic code that can be overridden by patches */ 100struct hdmi_ops { 101 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 102 unsigned char *buf, int *eld_size); 103 104 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */ 105 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid, 106 int asp_slot); 107 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid, 108 int asp_slot, int channel); 109 110 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 111 int ca, int active_channels, int conn_type); 112 113 /* enable/disable HBR (HD passthrough) */ 114 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr); 115 116 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 117 hda_nid_t pin_nid, u32 stream_tag, int format); 118 119 /* Helpers for producing the channel map TLVs. These can be overridden 120 * for devices that have non-standard mapping requirements. */ 121 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap, 122 int channels); 123 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap, 124 unsigned int *chmap, int channels); 125 126 /* check that the user-given chmap is supported */ 127 int (*chmap_validate)(int ca, int channels, unsigned char *chmap); 128}; 129 130struct hdmi_spec { 131 int num_cvts; 132 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 133 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 134 135 int num_pins; 136 struct snd_array pins; /* struct hdmi_spec_per_pin */ 137 struct hda_pcm *pcm_rec[16]; 138 unsigned int channels_max; /* max over all cvts */ 139 140 struct hdmi_eld temp_eld; 141 struct hdmi_ops ops; 142 143 bool dyn_pin_out; 144 145 /* 146 * Non-generic VIA/NVIDIA specific 147 */ 148 struct hda_multi_out multiout; 149 struct hda_pcm_stream pcm_playback; 150 151 /* i915/powerwell (Haswell+/Valleyview+) specific */ 152 struct i915_audio_component_audio_ops i915_audio_ops; 153}; 154 155 156struct hdmi_audio_infoframe { 157 u8 type; /* 0x84 */ 158 u8 ver; /* 0x01 */ 159 u8 len; /* 0x0a */ 160 161 u8 checksum; 162 163 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 164 u8 SS01_SF24; 165 u8 CXT04; 166 u8 CA; 167 u8 LFEPBL01_LSV36_DM_INH7; 168}; 169 170struct dp_audio_infoframe { 171 u8 type; /* 0x84 */ 172 u8 len; /* 0x1b */ 173 u8 ver; /* 0x11 << 2 */ 174 175 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 176 u8 SS01_SF24; 177 u8 CXT04; 178 u8 CA; 179 u8 LFEPBL01_LSV36_DM_INH7; 180}; 181 182union audio_infoframe { 183 struct hdmi_audio_infoframe hdmi; 184 struct dp_audio_infoframe dp; 185 u8 bytes[0]; 186}; 187 188/* 189 * CEA speaker placement: 190 * 191 * FLH FCH FRH 192 * FLW FL FLC FC FRC FR FRW 193 * 194 * LFE 195 * TC 196 * 197 * RL RLC RC RRC RR 198 * 199 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to 200 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC. 201 */ 202enum cea_speaker_placement { 203 FL = (1 << 0), /* Front Left */ 204 FC = (1 << 1), /* Front Center */ 205 FR = (1 << 2), /* Front Right */ 206 FLC = (1 << 3), /* Front Left Center */ 207 FRC = (1 << 4), /* Front Right Center */ 208 RL = (1 << 5), /* Rear Left */ 209 RC = (1 << 6), /* Rear Center */ 210 RR = (1 << 7), /* Rear Right */ 211 RLC = (1 << 8), /* Rear Left Center */ 212 RRC = (1 << 9), /* Rear Right Center */ 213 LFE = (1 << 10), /* Low Frequency Effect */ 214 FLW = (1 << 11), /* Front Left Wide */ 215 FRW = (1 << 12), /* Front Right Wide */ 216 FLH = (1 << 13), /* Front Left High */ 217 FCH = (1 << 14), /* Front Center High */ 218 FRH = (1 << 15), /* Front Right High */ 219 TC = (1 << 16), /* Top Center */ 220}; 221 222/* 223 * ELD SA bits in the CEA Speaker Allocation data block 224 */ 225static int eld_speaker_allocation_bits[] = { 226 [0] = FL | FR, 227 [1] = LFE, 228 [2] = FC, 229 [3] = RL | RR, 230 [4] = RC, 231 [5] = FLC | FRC, 232 [6] = RLC | RRC, 233 /* the following are not defined in ELD yet */ 234 [7] = FLW | FRW, 235 [8] = FLH | FRH, 236 [9] = TC, 237 [10] = FCH, 238}; 239 240struct cea_channel_speaker_allocation { 241 int ca_index; 242 int speakers[8]; 243 244 /* derived values, just for convenience */ 245 int channels; 246 int spk_mask; 247}; 248 249/* 250 * ALSA sequence is: 251 * 252 * surround40 surround41 surround50 surround51 surround71 253 * ch0 front left = = = = 254 * ch1 front right = = = = 255 * ch2 rear left = = = = 256 * ch3 rear right = = = = 257 * ch4 LFE center center center 258 * ch5 LFE LFE 259 * ch6 side left 260 * ch7 side right 261 * 262 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR} 263 */ 264static int hdmi_channel_mapping[0x32][8] = { 265 /* stereo */ 266 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }, 267 /* 2.1 */ 268 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }, 269 /* Dolby Surround */ 270 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 }, 271 /* surround40 */ 272 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 }, 273 /* 4ch */ 274 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 }, 275 /* surround41 */ 276 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 }, 277 /* surround50 */ 278 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 }, 279 /* surround51 */ 280 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 }, 281 /* 7.1 */ 282 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 }, 283}; 284 285/* 286 * This is an ordered list! 287 * 288 * The preceding ones have better chances to be selected by 289 * hdmi_channel_allocation(). 290 */ 291static struct cea_channel_speaker_allocation channel_allocations[] = { 292/* channel: 7 6 5 4 3 2 1 0 */ 293{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, 294 /* 2.1 */ 295{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, 296 /* Dolby Surround */ 297{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, 298 /* surround40 */ 299{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, 300 /* surround41 */ 301{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, 302 /* surround50 */ 303{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, 304 /* surround51 */ 305{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, 306 /* 6.1 */ 307{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, 308 /* surround71 */ 309{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, 310 311{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, 312{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, 313{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, 314{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, 315{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, 316{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, 317{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, 318{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, 319{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, 320{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, 321{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, 322{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, 323{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, 324{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, 325{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, 326{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, 327{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, 328{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, 329{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, 330{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, 331{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, 332{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, 333{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, 334{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } }, 335{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } }, 336{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } }, 337{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } }, 338{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } }, 339{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } }, 340{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } }, 341{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } }, 342{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } }, 343{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } }, 344{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } }, 345{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } }, 346{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } }, 347{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } }, 348{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } }, 349{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } }, 350{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } }, 351{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } }, 352}; 353 354 355/* 356 * HDMI routines 357 */ 358 359#define get_pin(spec, idx) \ 360 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 361#define get_cvt(spec, idx) \ 362 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 363#define get_pcm_rec(spec, idx) ((spec)->pcm_rec[idx]) 364 365static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid) 366{ 367 struct hdmi_spec *spec = codec->spec; 368 int pin_idx; 369 370 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) 371 if (get_pin(spec, pin_idx)->pin_nid == pin_nid) 372 return pin_idx; 373 374 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 375 return -EINVAL; 376} 377 378static int hinfo_to_pin_index(struct hda_codec *codec, 379 struct hda_pcm_stream *hinfo) 380{ 381 struct hdmi_spec *spec = codec->spec; 382 int pin_idx; 383 384 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) 385 if (get_pcm_rec(spec, pin_idx)->stream == hinfo) 386 return pin_idx; 387 388 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); 389 return -EINVAL; 390} 391 392static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 393{ 394 struct hdmi_spec *spec = codec->spec; 395 int cvt_idx; 396 397 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 398 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 399 return cvt_idx; 400 401 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 402 return -EINVAL; 403} 404 405static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 406 struct snd_ctl_elem_info *uinfo) 407{ 408 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 409 struct hdmi_spec *spec = codec->spec; 410 struct hdmi_spec_per_pin *per_pin; 411 struct hdmi_eld *eld; 412 int pin_idx; 413 414 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 415 416 pin_idx = kcontrol->private_value; 417 per_pin = get_pin(spec, pin_idx); 418 eld = &per_pin->sink_eld; 419 420 mutex_lock(&per_pin->lock); 421 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 422 mutex_unlock(&per_pin->lock); 423 424 return 0; 425} 426 427static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 428 struct snd_ctl_elem_value *ucontrol) 429{ 430 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 431 struct hdmi_spec *spec = codec->spec; 432 struct hdmi_spec_per_pin *per_pin; 433 struct hdmi_eld *eld; 434 int pin_idx; 435 436 pin_idx = kcontrol->private_value; 437 per_pin = get_pin(spec, pin_idx); 438 eld = &per_pin->sink_eld; 439 440 mutex_lock(&per_pin->lock); 441 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 442 eld->eld_size > ELD_MAX_SIZE) { 443 mutex_unlock(&per_pin->lock); 444 snd_BUG(); 445 return -EINVAL; 446 } 447 448 memset(ucontrol->value.bytes.data, 0, 449 ARRAY_SIZE(ucontrol->value.bytes.data)); 450 if (eld->eld_valid) 451 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 452 eld->eld_size); 453 mutex_unlock(&per_pin->lock); 454 455 return 0; 456} 457 458static struct snd_kcontrol_new eld_bytes_ctl = { 459 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, 460 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 461 .name = "ELD", 462 .info = hdmi_eld_ctl_info, 463 .get = hdmi_eld_ctl_get, 464}; 465 466static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx, 467 int device) 468{ 469 struct snd_kcontrol *kctl; 470 struct hdmi_spec *spec = codec->spec; 471 int err; 472 473 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 474 if (!kctl) 475 return -ENOMEM; 476 kctl->private_value = pin_idx; 477 kctl->id.device = device; 478 479 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl); 480 if (err < 0) 481 return err; 482 483 get_pin(spec, pin_idx)->eld_ctl = kctl; 484 return 0; 485} 486 487#ifdef BE_PARANOID 488static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 489 int *packet_index, int *byte_index) 490{ 491 int val; 492 493 val = snd_hda_codec_read(codec, pin_nid, 0, 494 AC_VERB_GET_HDMI_DIP_INDEX, 0); 495 496 *packet_index = val >> 5; 497 *byte_index = val & 0x1f; 498} 499#endif 500 501static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 502 int packet_index, int byte_index) 503{ 504 int val; 505 506 val = (packet_index << 5) | (byte_index & 0x1f); 507 508 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 509} 510 511static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 512 unsigned char val) 513{ 514 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 515} 516 517static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 518{ 519 struct hdmi_spec *spec = codec->spec; 520 int pin_out; 521 522 /* Unmute */ 523 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 524 snd_hda_codec_write(codec, pin_nid, 0, 525 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 526 527 if (spec->dyn_pin_out) 528 /* Disable pin out until stream is active */ 529 pin_out = 0; 530 else 531 /* Enable pin out: some machines with GM965 gets broken output 532 * when the pin is disabled or changed while using with HDMI 533 */ 534 pin_out = PIN_OUT; 535 536 snd_hda_codec_write(codec, pin_nid, 0, 537 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 538} 539 540static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid) 541{ 542 return 1 + snd_hda_codec_read(codec, cvt_nid, 0, 543 AC_VERB_GET_CVT_CHAN_COUNT, 0); 544} 545 546static void hdmi_set_channel_count(struct hda_codec *codec, 547 hda_nid_t cvt_nid, int chs) 548{ 549 if (chs != hdmi_get_channel_count(codec, cvt_nid)) 550 snd_hda_codec_write(codec, cvt_nid, 0, 551 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1); 552} 553 554/* 555 * ELD proc files 556 */ 557 558#ifdef CONFIG_SND_PROC_FS 559static void print_eld_info(struct snd_info_entry *entry, 560 struct snd_info_buffer *buffer) 561{ 562 struct hdmi_spec_per_pin *per_pin = entry->private_data; 563 564 mutex_lock(&per_pin->lock); 565 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 566 mutex_unlock(&per_pin->lock); 567} 568 569static void write_eld_info(struct snd_info_entry *entry, 570 struct snd_info_buffer *buffer) 571{ 572 struct hdmi_spec_per_pin *per_pin = entry->private_data; 573 574 mutex_lock(&per_pin->lock); 575 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 576 mutex_unlock(&per_pin->lock); 577} 578 579static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 580{ 581 char name[32]; 582 struct hda_codec *codec = per_pin->codec; 583 struct snd_info_entry *entry; 584 int err; 585 586 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 587 err = snd_card_proc_new(codec->card, name, &entry); 588 if (err < 0) 589 return err; 590 591 snd_info_set_text_ops(entry, per_pin, print_eld_info); 592 entry->c.text.write = write_eld_info; 593 entry->mode |= S_IWUSR; 594 per_pin->proc_entry = entry; 595 596 return 0; 597} 598 599static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 600{ 601 if (!per_pin->codec->bus->shutdown) { 602 snd_info_free_entry(per_pin->proc_entry); 603 per_pin->proc_entry = NULL; 604 } 605} 606#else 607static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 608 int index) 609{ 610 return 0; 611} 612static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 613{ 614} 615#endif 616 617/* 618 * Channel mapping routines 619 */ 620 621/* 622 * Compute derived values in channel_allocations[]. 623 */ 624static void init_channel_allocations(void) 625{ 626 int i, j; 627 struct cea_channel_speaker_allocation *p; 628 629 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 630 p = channel_allocations + i; 631 p->channels = 0; 632 p->spk_mask = 0; 633 for (j = 0; j < ARRAY_SIZE(p->speakers); j++) 634 if (p->speakers[j]) { 635 p->channels++; 636 p->spk_mask |= p->speakers[j]; 637 } 638 } 639} 640 641static int get_channel_allocation_order(int ca) 642{ 643 int i; 644 645 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 646 if (channel_allocations[i].ca_index == ca) 647 break; 648 } 649 return i; 650} 651 652/* 653 * The transformation takes two steps: 654 * 655 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask 656 * spk_mask => (channel_allocations[]) => ai->CA 657 * 658 * TODO: it could select the wrong CA from multiple candidates. 659*/ 660static int hdmi_channel_allocation(struct hda_codec *codec, 661 struct hdmi_eld *eld, int channels) 662{ 663 int i; 664 int ca = 0; 665 int spk_mask = 0; 666 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE]; 667 668 /* 669 * CA defaults to 0 for basic stereo audio 670 */ 671 if (channels <= 2) 672 return 0; 673 674 /* 675 * expand ELD's speaker allocation mask 676 * 677 * ELD tells the speaker mask in a compact(paired) form, 678 * expand ELD's notions to match the ones used by Audio InfoFrame. 679 */ 680 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 681 if (eld->info.spk_alloc & (1 << i)) 682 spk_mask |= eld_speaker_allocation_bits[i]; 683 } 684 685 /* search for the first working match in the CA table */ 686 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 687 if (channels == channel_allocations[i].channels && 688 (spk_mask & channel_allocations[i].spk_mask) == 689 channel_allocations[i].spk_mask) { 690 ca = channel_allocations[i].ca_index; 691 break; 692 } 693 } 694 695 if (!ca) { 696 /* if there was no match, select the regular ALSA channel 697 * allocation with the matching number of channels */ 698 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 699 if (channels == channel_allocations[i].channels) { 700 ca = channel_allocations[i].ca_index; 701 break; 702 } 703 } 704 } 705 706 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf)); 707 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n", 708 ca, channels, buf); 709 710 return ca; 711} 712 713static void hdmi_debug_channel_mapping(struct hda_codec *codec, 714 hda_nid_t pin_nid) 715{ 716#ifdef CONFIG_SND_DEBUG_VERBOSE 717 struct hdmi_spec *spec = codec->spec; 718 int i; 719 int channel; 720 721 for (i = 0; i < 8; i++) { 722 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i); 723 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n", 724 channel, i); 725 } 726#endif 727} 728 729static void hdmi_std_setup_channel_mapping(struct hda_codec *codec, 730 hda_nid_t pin_nid, 731 bool non_pcm, 732 int ca) 733{ 734 struct hdmi_spec *spec = codec->spec; 735 struct cea_channel_speaker_allocation *ch_alloc; 736 int i; 737 int err; 738 int order; 739 int non_pcm_mapping[8]; 740 741 order = get_channel_allocation_order(ca); 742 ch_alloc = &channel_allocations[order]; 743 744 if (hdmi_channel_mapping[ca][1] == 0) { 745 int hdmi_slot = 0; 746 /* fill actual channel mappings in ALSA channel (i) order */ 747 for (i = 0; i < ch_alloc->channels; i++) { 748 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8)) 749 hdmi_slot++; /* skip zero slots */ 750 751 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++; 752 } 753 /* fill the rest of the slots with ALSA channel 0xf */ 754 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) 755 if (!ch_alloc->speakers[7 - hdmi_slot]) 756 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot; 757 } 758 759 if (non_pcm) { 760 for (i = 0; i < ch_alloc->channels; i++) 761 non_pcm_mapping[i] = (i << 4) | i; 762 for (; i < 8; i++) 763 non_pcm_mapping[i] = (0xf << 4) | i; 764 } 765 766 for (i = 0; i < 8; i++) { 767 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]; 768 int hdmi_slot = slotsetup & 0x0f; 769 int channel = (slotsetup & 0xf0) >> 4; 770 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel); 771 if (err) { 772 codec_dbg(codec, "HDMI: channel mapping failed\n"); 773 break; 774 } 775 } 776} 777 778struct channel_map_table { 779 unsigned char map; /* ALSA API channel map position */ 780 int spk_mask; /* speaker position bit mask */ 781}; 782 783static struct channel_map_table map_tables[] = { 784 { SNDRV_CHMAP_FL, FL }, 785 { SNDRV_CHMAP_FR, FR }, 786 { SNDRV_CHMAP_RL, RL }, 787 { SNDRV_CHMAP_RR, RR }, 788 { SNDRV_CHMAP_LFE, LFE }, 789 { SNDRV_CHMAP_FC, FC }, 790 { SNDRV_CHMAP_RLC, RLC }, 791 { SNDRV_CHMAP_RRC, RRC }, 792 { SNDRV_CHMAP_RC, RC }, 793 { SNDRV_CHMAP_FLC, FLC }, 794 { SNDRV_CHMAP_FRC, FRC }, 795 { SNDRV_CHMAP_TFL, FLH }, 796 { SNDRV_CHMAP_TFR, FRH }, 797 { SNDRV_CHMAP_FLW, FLW }, 798 { SNDRV_CHMAP_FRW, FRW }, 799 { SNDRV_CHMAP_TC, TC }, 800 { SNDRV_CHMAP_TFC, FCH }, 801 {} /* terminator */ 802}; 803 804/* from ALSA API channel position to speaker bit mask */ 805static int to_spk_mask(unsigned char c) 806{ 807 struct channel_map_table *t = map_tables; 808 for (; t->map; t++) { 809 if (t->map == c) 810 return t->spk_mask; 811 } 812 return 0; 813} 814 815/* from ALSA API channel position to CEA slot */ 816static int to_cea_slot(int ordered_ca, unsigned char pos) 817{ 818 int mask = to_spk_mask(pos); 819 int i; 820 821 if (mask) { 822 for (i = 0; i < 8; i++) { 823 if (channel_allocations[ordered_ca].speakers[7 - i] == mask) 824 return i; 825 } 826 } 827 828 return -1; 829} 830 831/* from speaker bit mask to ALSA API channel position */ 832static int spk_to_chmap(int spk) 833{ 834 struct channel_map_table *t = map_tables; 835 for (; t->map; t++) { 836 if (t->spk_mask == spk) 837 return t->map; 838 } 839 return 0; 840} 841 842/* from CEA slot to ALSA API channel position */ 843static int from_cea_slot(int ordered_ca, unsigned char slot) 844{ 845 int mask = channel_allocations[ordered_ca].speakers[7 - slot]; 846 847 return spk_to_chmap(mask); 848} 849 850/* get the CA index corresponding to the given ALSA API channel map */ 851static int hdmi_manual_channel_allocation(int chs, unsigned char *map) 852{ 853 int i, spks = 0, spk_mask = 0; 854 855 for (i = 0; i < chs; i++) { 856 int mask = to_spk_mask(map[i]); 857 if (mask) { 858 spk_mask |= mask; 859 spks++; 860 } 861 } 862 863 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 864 if ((chs == channel_allocations[i].channels || 865 spks == channel_allocations[i].channels) && 866 (spk_mask & channel_allocations[i].spk_mask) == 867 channel_allocations[i].spk_mask) 868 return channel_allocations[i].ca_index; 869 } 870 return -1; 871} 872 873/* set up the channel slots for the given ALSA API channel map */ 874static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec, 875 hda_nid_t pin_nid, 876 int chs, unsigned char *map, 877 int ca) 878{ 879 struct hdmi_spec *spec = codec->spec; 880 int ordered_ca = get_channel_allocation_order(ca); 881 int alsa_pos, hdmi_slot; 882 int assignments[8] = {[0 ... 7] = 0xf}; 883 884 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) { 885 886 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]); 887 888 if (hdmi_slot < 0) 889 continue; /* unassigned channel */ 890 891 assignments[hdmi_slot] = alsa_pos; 892 } 893 894 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) { 895 int err; 896 897 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, 898 assignments[hdmi_slot]); 899 if (err) 900 return -EINVAL; 901 } 902 return 0; 903} 904 905/* store ALSA API channel map from the current default map */ 906static void hdmi_setup_fake_chmap(unsigned char *map, int ca) 907{ 908 int i; 909 int ordered_ca = get_channel_allocation_order(ca); 910 for (i = 0; i < 8; i++) { 911 if (i < channel_allocations[ordered_ca].channels) 912 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f); 913 else 914 map[i] = 0; 915 } 916} 917 918static void hdmi_setup_channel_mapping(struct hda_codec *codec, 919 hda_nid_t pin_nid, bool non_pcm, int ca, 920 int channels, unsigned char *map, 921 bool chmap_set) 922{ 923 if (!non_pcm && chmap_set) { 924 hdmi_manual_setup_channel_mapping(codec, pin_nid, 925 channels, map, ca); 926 } else { 927 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca); 928 hdmi_setup_fake_chmap(map, ca); 929 } 930 931 hdmi_debug_channel_mapping(codec, pin_nid); 932} 933 934static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid, 935 int asp_slot, int channel) 936{ 937 return snd_hda_codec_write(codec, pin_nid, 0, 938 AC_VERB_SET_HDMI_CHAN_SLOT, 939 (channel << 4) | asp_slot); 940} 941 942static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid, 943 int asp_slot) 944{ 945 return (snd_hda_codec_read(codec, pin_nid, 0, 946 AC_VERB_GET_HDMI_CHAN_SLOT, 947 asp_slot) & 0xf0) >> 4; 948} 949 950/* 951 * Audio InfoFrame routines 952 */ 953 954/* 955 * Enable Audio InfoFrame Transmission 956 */ 957static void hdmi_start_infoframe_trans(struct hda_codec *codec, 958 hda_nid_t pin_nid) 959{ 960 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 961 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 962 AC_DIPXMIT_BEST); 963} 964 965/* 966 * Disable Audio InfoFrame Transmission 967 */ 968static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 969 hda_nid_t pin_nid) 970{ 971 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 972 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 973 AC_DIPXMIT_DISABLE); 974} 975 976static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 977{ 978#ifdef CONFIG_SND_DEBUG_VERBOSE 979 int i; 980 int size; 981 982 size = snd_hdmi_get_eld_size(codec, pin_nid); 983 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 984 985 for (i = 0; i < 8; i++) { 986 size = snd_hda_codec_read(codec, pin_nid, 0, 987 AC_VERB_GET_HDMI_DIP_SIZE, i); 988 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 989 } 990#endif 991} 992 993static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 994{ 995#ifdef BE_PARANOID 996 int i, j; 997 int size; 998 int pi, bi; 999 for (i = 0; i < 8; i++) { 1000 size = snd_hda_codec_read(codec, pin_nid, 0, 1001 AC_VERB_GET_HDMI_DIP_SIZE, i); 1002 if (size == 0) 1003 continue; 1004 1005 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 1006 for (j = 1; j < 1000; j++) { 1007 hdmi_write_dip_byte(codec, pin_nid, 0x0); 1008 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 1009 if (pi != i) 1010 codec_dbg(codec, "dip index %d: %d != %d\n", 1011 bi, pi, i); 1012 if (bi == 0) /* byte index wrapped around */ 1013 break; 1014 } 1015 codec_dbg(codec, 1016 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 1017 i, size, j); 1018 } 1019#endif 1020} 1021 1022static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 1023{ 1024 u8 *bytes = (u8 *)hdmi_ai; 1025 u8 sum = 0; 1026 int i; 1027 1028 hdmi_ai->checksum = 0; 1029 1030 for (i = 0; i < sizeof(*hdmi_ai); i++) 1031 sum += bytes[i]; 1032 1033 hdmi_ai->checksum = -sum; 1034} 1035 1036static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 1037 hda_nid_t pin_nid, 1038 u8 *dip, int size) 1039{ 1040 int i; 1041 1042 hdmi_debug_dip_size(codec, pin_nid); 1043 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 1044 1045 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 1046 for (i = 0; i < size; i++) 1047 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 1048} 1049 1050static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 1051 u8 *dip, int size) 1052{ 1053 u8 val; 1054 int i; 1055 1056 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 1057 != AC_DIPXMIT_BEST) 1058 return false; 1059 1060 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 1061 for (i = 0; i < size; i++) { 1062 val = snd_hda_codec_read(codec, pin_nid, 0, 1063 AC_VERB_GET_HDMI_DIP_DATA, 0); 1064 if (val != dip[i]) 1065 return false; 1066 } 1067 1068 return true; 1069} 1070 1071static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 1072 hda_nid_t pin_nid, 1073 int ca, int active_channels, 1074 int conn_type) 1075{ 1076 union audio_infoframe ai; 1077 1078 memset(&ai, 0, sizeof(ai)); 1079 if (conn_type == 0) { /* HDMI */ 1080 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 1081 1082 hdmi_ai->type = 0x84; 1083 hdmi_ai->ver = 0x01; 1084 hdmi_ai->len = 0x0a; 1085 hdmi_ai->CC02_CT47 = active_channels - 1; 1086 hdmi_ai->CA = ca; 1087 hdmi_checksum_audio_infoframe(hdmi_ai); 1088 } else if (conn_type == 1) { /* DisplayPort */ 1089 struct dp_audio_infoframe *dp_ai = &ai.dp; 1090 1091 dp_ai->type = 0x84; 1092 dp_ai->len = 0x1b; 1093 dp_ai->ver = 0x11 << 2; 1094 dp_ai->CC02_CT47 = active_channels - 1; 1095 dp_ai->CA = ca; 1096 } else { 1097 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 1098 pin_nid); 1099 return; 1100 } 1101 1102 /* 1103 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 1104 * sizeof(*dp_ai) to avoid partial match/update problems when 1105 * the user switches between HDMI/DP monitors. 1106 */ 1107 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 1108 sizeof(ai))) { 1109 codec_dbg(codec, 1110 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 1111 pin_nid, 1112 active_channels, ca); 1113 hdmi_stop_infoframe_trans(codec, pin_nid); 1114 hdmi_fill_audio_infoframe(codec, pin_nid, 1115 ai.bytes, sizeof(ai)); 1116 hdmi_start_infoframe_trans(codec, pin_nid); 1117 } 1118} 1119 1120static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 1121 struct hdmi_spec_per_pin *per_pin, 1122 bool non_pcm) 1123{ 1124 struct hdmi_spec *spec = codec->spec; 1125 hda_nid_t pin_nid = per_pin->pin_nid; 1126 int channels = per_pin->channels; 1127 int active_channels; 1128 struct hdmi_eld *eld; 1129 int ca, ordered_ca; 1130 1131 if (!channels) 1132 return; 1133 1134 if (is_haswell_plus(codec)) 1135 snd_hda_codec_write(codec, pin_nid, 0, 1136 AC_VERB_SET_AMP_GAIN_MUTE, 1137 AMP_OUT_UNMUTE); 1138 1139 eld = &per_pin->sink_eld; 1140 1141 if (!non_pcm && per_pin->chmap_set) 1142 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap); 1143 else 1144 ca = hdmi_channel_allocation(codec, eld, channels); 1145 if (ca < 0) 1146 ca = 0; 1147 1148 ordered_ca = get_channel_allocation_order(ca); 1149 active_channels = channel_allocations[ordered_ca].channels; 1150 1151 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels); 1152 1153 /* 1154 * always configure channel mapping, it may have been changed by the 1155 * user in the meantime 1156 */ 1157 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca, 1158 channels, per_pin->chmap, 1159 per_pin->chmap_set); 1160 1161 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels, 1162 eld->info.conn_type); 1163 1164 per_pin->non_pcm = non_pcm; 1165} 1166 1167/* 1168 * Unsolicited events 1169 */ 1170 1171static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 1172 1173static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid) 1174{ 1175 struct hdmi_spec *spec = codec->spec; 1176 int pin_idx = pin_nid_to_pin_index(codec, nid); 1177 1178 if (pin_idx < 0) 1179 return; 1180 if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) 1181 snd_hda_jack_report_sync(codec); 1182} 1183 1184static void jack_callback(struct hda_codec *codec, 1185 struct hda_jack_callback *jack) 1186{ 1187 check_presence_and_report(codec, jack->nid); 1188} 1189 1190static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) 1191{ 1192 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 1193 struct hda_jack_tbl *jack; 1194 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 1195 1196 jack = snd_hda_jack_tbl_get_from_tag(codec, tag); 1197 if (!jack) 1198 return; 1199 jack->jack_dirty = 1; 1200 1201 codec_dbg(codec, 1202 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 1203 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA), 1204 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 1205 1206 check_presence_and_report(codec, jack->nid); 1207} 1208 1209static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 1210{ 1211 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 1212 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 1213 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 1214 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 1215 1216 codec_info(codec, 1217 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 1218 codec->addr, 1219 tag, 1220 subtag, 1221 cp_state, 1222 cp_ready); 1223 1224 /* TODO */ 1225 if (cp_state) 1226 ; 1227 if (cp_ready) 1228 ; 1229} 1230 1231 1232static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 1233{ 1234 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 1235 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 1236 1237 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) { 1238 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 1239 return; 1240 } 1241 1242 if (subtag == 0) 1243 hdmi_intrinsic_event(codec, res); 1244 else 1245 hdmi_non_intrinsic_event(codec, res); 1246} 1247 1248static void haswell_verify_D0(struct hda_codec *codec, 1249 hda_nid_t cvt_nid, hda_nid_t nid) 1250{ 1251 int pwr; 1252 1253 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 1254 * thus pins could only choose converter 0 for use. Make sure the 1255 * converters are in correct power state */ 1256 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 1257 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 1258 1259 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 1260 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 1261 AC_PWRST_D0); 1262 msleep(40); 1263 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 1264 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 1265 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 1266 } 1267} 1268 1269/* 1270 * Callbacks 1271 */ 1272 1273/* HBR should be Non-PCM, 8 channels */ 1274#define is_hbr_format(format) \ 1275 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 1276 1277static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 1278 bool hbr) 1279{ 1280 int pinctl, new_pinctl; 1281 1282 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 1283 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 1284 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1285 1286 if (pinctl < 0) 1287 return hbr ? -EINVAL : 0; 1288 1289 new_pinctl = pinctl & ~AC_PINCTL_EPT; 1290 if (hbr) 1291 new_pinctl |= AC_PINCTL_EPT_HBR; 1292 else 1293 new_pinctl |= AC_PINCTL_EPT_NATIVE; 1294 1295 codec_dbg(codec, 1296 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 1297 pin_nid, 1298 pinctl == new_pinctl ? "" : "new-", 1299 new_pinctl); 1300 1301 if (pinctl != new_pinctl) 1302 snd_hda_codec_write(codec, pin_nid, 0, 1303 AC_VERB_SET_PIN_WIDGET_CONTROL, 1304 new_pinctl); 1305 } else if (hbr) 1306 return -EINVAL; 1307 1308 return 0; 1309} 1310 1311static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 1312 hda_nid_t pin_nid, u32 stream_tag, int format) 1313{ 1314 struct hdmi_spec *spec = codec->spec; 1315 int err; 1316 1317 if (is_haswell_plus(codec)) 1318 haswell_verify_D0(codec, cvt_nid, pin_nid); 1319 1320 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format)); 1321 1322 if (err) { 1323 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 1324 return err; 1325 } 1326 1327 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 1328 return 0; 1329} 1330 1331static int hdmi_choose_cvt(struct hda_codec *codec, 1332 int pin_idx, int *cvt_id, int *mux_id) 1333{ 1334 struct hdmi_spec *spec = codec->spec; 1335 struct hdmi_spec_per_pin *per_pin; 1336 struct hdmi_spec_per_cvt *per_cvt = NULL; 1337 int cvt_idx, mux_idx = 0; 1338 1339 per_pin = get_pin(spec, pin_idx); 1340 1341 /* Dynamically assign converter to stream */ 1342 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1343 per_cvt = get_cvt(spec, cvt_idx); 1344 1345 /* Must not already be assigned */ 1346 if (per_cvt->assigned) 1347 continue; 1348 /* Must be in pin's mux's list of converters */ 1349 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1350 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 1351 break; 1352 /* Not in mux list */ 1353 if (mux_idx == per_pin->num_mux_nids) 1354 continue; 1355 break; 1356 } 1357 1358 /* No free converters */ 1359 if (cvt_idx == spec->num_cvts) 1360 return -ENODEV; 1361 1362 per_pin->mux_idx = mux_idx; 1363 1364 if (cvt_id) 1365 *cvt_id = cvt_idx; 1366 if (mux_id) 1367 *mux_id = mux_idx; 1368 1369 return 0; 1370} 1371 1372/* Assure the pin select the right convetor */ 1373static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1374 struct hdmi_spec_per_pin *per_pin) 1375{ 1376 hda_nid_t pin_nid = per_pin->pin_nid; 1377 int mux_idx, curr; 1378 1379 mux_idx = per_pin->mux_idx; 1380 curr = snd_hda_codec_read(codec, pin_nid, 0, 1381 AC_VERB_GET_CONNECT_SEL, 0); 1382 if (curr != mux_idx) 1383 snd_hda_codec_write_cache(codec, pin_nid, 0, 1384 AC_VERB_SET_CONNECT_SEL, 1385 mux_idx); 1386} 1387 1388/* Intel HDMI workaround to fix audio routing issue: 1389 * For some Intel display codecs, pins share the same connection list. 1390 * So a conveter can be selected by multiple pins and playback on any of these 1391 * pins will generate sound on the external display, because audio flows from 1392 * the same converter to the display pipeline. Also muting one pin may make 1393 * other pins have no sound output. 1394 * So this function assures that an assigned converter for a pin is not selected 1395 * by any other pins. 1396 */ 1397static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1398 hda_nid_t pin_nid, int mux_idx) 1399{ 1400 struct hdmi_spec *spec = codec->spec; 1401 hda_nid_t nid; 1402 int cvt_idx, curr; 1403 struct hdmi_spec_per_cvt *per_cvt; 1404 1405 /* configure all pins, including "no physical connection" ones */ 1406 for_each_hda_codec_node(nid, codec) { 1407 unsigned int wid_caps = get_wcaps(codec, nid); 1408 unsigned int wid_type = get_wcaps_type(wid_caps); 1409 1410 if (wid_type != AC_WID_PIN) 1411 continue; 1412 1413 if (nid == pin_nid) 1414 continue; 1415 1416 curr = snd_hda_codec_read(codec, nid, 0, 1417 AC_VERB_GET_CONNECT_SEL, 0); 1418 if (curr != mux_idx) 1419 continue; 1420 1421 /* choose an unassigned converter. The conveters in the 1422 * connection list are in the same order as in the codec. 1423 */ 1424 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1425 per_cvt = get_cvt(spec, cvt_idx); 1426 if (!per_cvt->assigned) { 1427 codec_dbg(codec, 1428 "choose cvt %d for pin nid %d\n", 1429 cvt_idx, nid); 1430 snd_hda_codec_write_cache(codec, nid, 0, 1431 AC_VERB_SET_CONNECT_SEL, 1432 cvt_idx); 1433 break; 1434 } 1435 } 1436 } 1437} 1438 1439/* 1440 * HDA PCM callbacks 1441 */ 1442static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1443 struct hda_codec *codec, 1444 struct snd_pcm_substream *substream) 1445{ 1446 struct hdmi_spec *spec = codec->spec; 1447 struct snd_pcm_runtime *runtime = substream->runtime; 1448 int pin_idx, cvt_idx, mux_idx = 0; 1449 struct hdmi_spec_per_pin *per_pin; 1450 struct hdmi_eld *eld; 1451 struct hdmi_spec_per_cvt *per_cvt = NULL; 1452 int err; 1453 1454 /* Validate hinfo */ 1455 pin_idx = hinfo_to_pin_index(codec, hinfo); 1456 if (snd_BUG_ON(pin_idx < 0)) 1457 return -EINVAL; 1458 per_pin = get_pin(spec, pin_idx); 1459 eld = &per_pin->sink_eld; 1460 1461 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx); 1462 if (err < 0) 1463 return err; 1464 1465 per_cvt = get_cvt(spec, cvt_idx); 1466 /* Claim converter */ 1467 per_cvt->assigned = 1; 1468 per_pin->cvt_nid = per_cvt->cvt_nid; 1469 hinfo->nid = per_cvt->cvt_nid; 1470 1471 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1472 AC_VERB_SET_CONNECT_SEL, 1473 mux_idx); 1474 1475 /* configure unused pins to choose other converters */ 1476 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) 1477 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx); 1478 1479 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid); 1480 1481 /* Initially set the converter's capabilities */ 1482 hinfo->channels_min = per_cvt->channels_min; 1483 hinfo->channels_max = per_cvt->channels_max; 1484 hinfo->rates = per_cvt->rates; 1485 hinfo->formats = per_cvt->formats; 1486 hinfo->maxbps = per_cvt->maxbps; 1487 1488 /* Restrict capabilities by ELD if this isn't disabled */ 1489 if (!static_hdmi_pcm && eld->eld_valid) { 1490 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1491 if (hinfo->channels_min > hinfo->channels_max || 1492 !hinfo->rates || !hinfo->formats) { 1493 per_cvt->assigned = 0; 1494 hinfo->nid = 0; 1495 snd_hda_spdif_ctls_unassign(codec, pin_idx); 1496 return -ENODEV; 1497 } 1498 } 1499 1500 /* Store the updated parameters */ 1501 runtime->hw.channels_min = hinfo->channels_min; 1502 runtime->hw.channels_max = hinfo->channels_max; 1503 runtime->hw.formats = hinfo->formats; 1504 runtime->hw.rates = hinfo->rates; 1505 1506 snd_pcm_hw_constraint_step(substream->runtime, 0, 1507 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1508 return 0; 1509} 1510 1511/* 1512 * HDA/HDMI auto parsing 1513 */ 1514static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1515{ 1516 struct hdmi_spec *spec = codec->spec; 1517 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1518 hda_nid_t pin_nid = per_pin->pin_nid; 1519 1520 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1521 codec_warn(codec, 1522 "HDMI: pin %d wcaps %#x does not support connection list\n", 1523 pin_nid, get_wcaps(codec, pin_nid)); 1524 return -EINVAL; 1525 } 1526 1527 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid, 1528 per_pin->mux_nids, 1529 HDA_MAX_CONNECTIONS); 1530 1531 return 0; 1532} 1533 1534static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1535{ 1536 struct hda_jack_tbl *jack; 1537 struct hda_codec *codec = per_pin->codec; 1538 struct hdmi_spec *spec = codec->spec; 1539 struct hdmi_eld *eld = &spec->temp_eld; 1540 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1541 hda_nid_t pin_nid = per_pin->pin_nid; 1542 /* 1543 * Always execute a GetPinSense verb here, even when called from 1544 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1545 * response's PD bit is not the real PD value, but indicates that 1546 * the real PD value changed. An older version of the HD-audio 1547 * specification worked this way. Hence, we just ignore the data in 1548 * the unsolicited response to avoid custom WARs. 1549 */ 1550 int present; 1551 bool update_eld = false; 1552 bool eld_changed = false; 1553 bool ret; 1554 1555 snd_hda_power_up_pm(codec); 1556 present = snd_hda_pin_sense(codec, pin_nid); 1557 1558 mutex_lock(&per_pin->lock); 1559 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1560 if (pin_eld->monitor_present) 1561 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1562 else 1563 eld->eld_valid = false; 1564 1565 codec_dbg(codec, 1566 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1567 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid); 1568 1569 if (eld->eld_valid) { 1570 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer, 1571 &eld->eld_size) < 0) 1572 eld->eld_valid = false; 1573 else { 1574 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld)); 1575 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1576 eld->eld_size) < 0) 1577 eld->eld_valid = false; 1578 } 1579 1580 if (eld->eld_valid) { 1581 snd_hdmi_show_eld(codec, &eld->info); 1582 update_eld = true; 1583 } 1584 else if (repoll) { 1585 schedule_delayed_work(&per_pin->work, 1586 msecs_to_jiffies(300)); 1587 goto unlock; 1588 } 1589 } 1590 1591 if (pin_eld->eld_valid != eld->eld_valid) 1592 eld_changed = true; 1593 1594 if (pin_eld->eld_valid && !eld->eld_valid) 1595 update_eld = true; 1596 1597 if (update_eld) { 1598 bool old_eld_valid = pin_eld->eld_valid; 1599 pin_eld->eld_valid = eld->eld_valid; 1600 if (pin_eld->eld_size != eld->eld_size || 1601 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1602 eld->eld_size) != 0) { 1603 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1604 eld->eld_size); 1605 eld_changed = true; 1606 } 1607 pin_eld->eld_size = eld->eld_size; 1608 pin_eld->info = eld->info; 1609 1610 /* 1611 * Re-setup pin and infoframe. This is needed e.g. when 1612 * - sink is first plugged-in (infoframe is not set up if !monitor_present) 1613 * - transcoder can change during stream playback on Haswell 1614 * and this can make HW reset converter selection on a pin. 1615 */ 1616 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1617 if (is_haswell_plus(codec) || 1618 is_valleyview_plus(codec)) { 1619 intel_verify_pin_cvt_connect(codec, per_pin); 1620 intel_not_share_assigned_cvt(codec, pin_nid, 1621 per_pin->mux_idx); 1622 } 1623 1624 hdmi_setup_audio_infoframe(codec, per_pin, 1625 per_pin->non_pcm); 1626 } 1627 } 1628 1629 if (eld_changed) 1630 snd_ctl_notify(codec->card, 1631 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, 1632 &per_pin->eld_ctl->id); 1633 unlock: 1634 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid; 1635 1636 jack = snd_hda_jack_tbl_get(codec, pin_nid); 1637 if (jack) 1638 jack->block_report = !ret; 1639 1640 mutex_unlock(&per_pin->lock); 1641 snd_hda_power_down_pm(codec); 1642 return ret; 1643} 1644 1645static void hdmi_repoll_eld(struct work_struct *work) 1646{ 1647 struct hdmi_spec_per_pin *per_pin = 1648 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1649 1650 if (per_pin->repoll_count++ > 6) 1651 per_pin->repoll_count = 0; 1652 1653 if (hdmi_present_sense(per_pin, per_pin->repoll_count)) 1654 snd_hda_jack_report_sync(per_pin->codec); 1655} 1656 1657static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 1658 hda_nid_t nid); 1659 1660static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1661{ 1662 struct hdmi_spec *spec = codec->spec; 1663 unsigned int caps, config; 1664 int pin_idx; 1665 struct hdmi_spec_per_pin *per_pin; 1666 int err; 1667 1668 caps = snd_hda_query_pin_caps(codec, pin_nid); 1669 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1670 return 0; 1671 1672 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1673 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1674 return 0; 1675 1676 if (is_haswell_plus(codec)) 1677 intel_haswell_fixup_connect_list(codec, pin_nid); 1678 1679 pin_idx = spec->num_pins; 1680 per_pin = snd_array_new(&spec->pins); 1681 if (!per_pin) 1682 return -ENOMEM; 1683 1684 per_pin->pin_nid = pin_nid; 1685 per_pin->non_pcm = false; 1686 1687 err = hdmi_read_pin_conn(codec, pin_idx); 1688 if (err < 0) 1689 return err; 1690 1691 spec->num_pins++; 1692 1693 return 0; 1694} 1695 1696static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1697{ 1698 struct hdmi_spec *spec = codec->spec; 1699 struct hdmi_spec_per_cvt *per_cvt; 1700 unsigned int chans; 1701 int err; 1702 1703 chans = get_wcaps(codec, cvt_nid); 1704 chans = get_wcaps_channels(chans); 1705 1706 per_cvt = snd_array_new(&spec->cvts); 1707 if (!per_cvt) 1708 return -ENOMEM; 1709 1710 per_cvt->cvt_nid = cvt_nid; 1711 per_cvt->channels_min = 2; 1712 if (chans <= 16) { 1713 per_cvt->channels_max = chans; 1714 if (chans > spec->channels_max) 1715 spec->channels_max = chans; 1716 } 1717 1718 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1719 &per_cvt->rates, 1720 &per_cvt->formats, 1721 &per_cvt->maxbps); 1722 if (err < 0) 1723 return err; 1724 1725 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1726 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1727 spec->num_cvts++; 1728 1729 return 0; 1730} 1731 1732static int hdmi_parse_codec(struct hda_codec *codec) 1733{ 1734 hda_nid_t nid; 1735 int i, nodes; 1736 1737 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); 1738 if (!nid || nodes < 0) { 1739 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1740 return -EINVAL; 1741 } 1742 1743 for (i = 0; i < nodes; i++, nid++) { 1744 unsigned int caps; 1745 unsigned int type; 1746 1747 caps = get_wcaps(codec, nid); 1748 type = get_wcaps_type(caps); 1749 1750 if (!(caps & AC_WCAP_DIGITAL)) 1751 continue; 1752 1753 switch (type) { 1754 case AC_WID_AUD_OUT: 1755 hdmi_add_cvt(codec, nid); 1756 break; 1757 case AC_WID_PIN: 1758 hdmi_add_pin(codec, nid); 1759 break; 1760 } 1761 } 1762 1763 return 0; 1764} 1765 1766/* 1767 */ 1768static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1769{ 1770 struct hda_spdif_out *spdif; 1771 bool non_pcm; 1772 1773 mutex_lock(&codec->spdif_mutex); 1774 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1775 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1776 mutex_unlock(&codec->spdif_mutex); 1777 return non_pcm; 1778} 1779 1780/* There is a fixed mapping between audio pin node and display port 1781 * on current Intel platforms: 1782 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 1783 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 1784 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 1785 */ 1786static int intel_pin2port(hda_nid_t pin_nid) 1787{ 1788 return pin_nid - 4; 1789} 1790 1791/* 1792 * HDMI callbacks 1793 */ 1794 1795static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1796 struct hda_codec *codec, 1797 unsigned int stream_tag, 1798 unsigned int format, 1799 struct snd_pcm_substream *substream) 1800{ 1801 hda_nid_t cvt_nid = hinfo->nid; 1802 struct hdmi_spec *spec = codec->spec; 1803 int pin_idx = hinfo_to_pin_index(codec, hinfo); 1804 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1805 hda_nid_t pin_nid = per_pin->pin_nid; 1806 struct snd_pcm_runtime *runtime = substream->runtime; 1807 struct i915_audio_component *acomp = codec->bus->core.audio_component; 1808 bool non_pcm; 1809 int pinctl; 1810 1811 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) { 1812 /* Verify pin:cvt selections to avoid silent audio after S3. 1813 * After S3, the audio driver restores pin:cvt selections 1814 * but this can happen before gfx is ready and such selection 1815 * is overlooked by HW. Thus multiple pins can share a same 1816 * default convertor and mute control will affect each other, 1817 * which can cause a resumed audio playback become silent 1818 * after S3. 1819 */ 1820 intel_verify_pin_cvt_connect(codec, per_pin); 1821 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx); 1822 } 1823 1824 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 1825 /* Todo: add DP1.2 MST audio support later */ 1826 if (acomp && acomp->ops && acomp->ops->sync_audio_rate) 1827 acomp->ops->sync_audio_rate(acomp->dev, 1828 intel_pin2port(pin_nid), 1829 runtime->rate); 1830 1831 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1832 mutex_lock(&per_pin->lock); 1833 per_pin->channels = substream->runtime->channels; 1834 per_pin->setup = true; 1835 1836 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1837 mutex_unlock(&per_pin->lock); 1838 1839 if (spec->dyn_pin_out) { 1840 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 1841 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1842 snd_hda_codec_write(codec, pin_nid, 0, 1843 AC_VERB_SET_PIN_WIDGET_CONTROL, 1844 pinctl | PIN_OUT); 1845 } 1846 1847 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 1848} 1849 1850static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 1851 struct hda_codec *codec, 1852 struct snd_pcm_substream *substream) 1853{ 1854 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 1855 return 0; 1856} 1857 1858static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 1859 struct hda_codec *codec, 1860 struct snd_pcm_substream *substream) 1861{ 1862 struct hdmi_spec *spec = codec->spec; 1863 int cvt_idx, pin_idx; 1864 struct hdmi_spec_per_cvt *per_cvt; 1865 struct hdmi_spec_per_pin *per_pin; 1866 int pinctl; 1867 1868 if (hinfo->nid) { 1869 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 1870 if (snd_BUG_ON(cvt_idx < 0)) 1871 return -EINVAL; 1872 per_cvt = get_cvt(spec, cvt_idx); 1873 1874 snd_BUG_ON(!per_cvt->assigned); 1875 per_cvt->assigned = 0; 1876 hinfo->nid = 0; 1877 1878 pin_idx = hinfo_to_pin_index(codec, hinfo); 1879 if (snd_BUG_ON(pin_idx < 0)) 1880 return -EINVAL; 1881 per_pin = get_pin(spec, pin_idx); 1882 1883 if (spec->dyn_pin_out) { 1884 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1885 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1886 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1887 AC_VERB_SET_PIN_WIDGET_CONTROL, 1888 pinctl & ~PIN_OUT); 1889 } 1890 1891 snd_hda_spdif_ctls_unassign(codec, pin_idx); 1892 1893 mutex_lock(&per_pin->lock); 1894 per_pin->chmap_set = false; 1895 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1896 1897 per_pin->setup = false; 1898 per_pin->channels = 0; 1899 mutex_unlock(&per_pin->lock); 1900 } 1901 1902 return 0; 1903} 1904 1905static const struct hda_pcm_ops generic_ops = { 1906 .open = hdmi_pcm_open, 1907 .close = hdmi_pcm_close, 1908 .prepare = generic_hdmi_playback_pcm_prepare, 1909 .cleanup = generic_hdmi_playback_pcm_cleanup, 1910}; 1911 1912/* 1913 * ALSA API channel-map control callbacks 1914 */ 1915static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol, 1916 struct snd_ctl_elem_info *uinfo) 1917{ 1918 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); 1919 struct hda_codec *codec = info->private_data; 1920 struct hdmi_spec *spec = codec->spec; 1921 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1922 uinfo->count = spec->channels_max; 1923 uinfo->value.integer.min = 0; 1924 uinfo->value.integer.max = SNDRV_CHMAP_LAST; 1925 return 0; 1926} 1927 1928static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap, 1929 int channels) 1930{ 1931 /* If the speaker allocation matches the channel count, it is OK.*/ 1932 if (cap->channels != channels) 1933 return -1; 1934 1935 /* all channels are remappable freely */ 1936 return SNDRV_CTL_TLVT_CHMAP_VAR; 1937} 1938 1939static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap, 1940 unsigned int *chmap, int channels) 1941{ 1942 int count = 0; 1943 int c; 1944 1945 for (c = 7; c >= 0; c--) { 1946 int spk = cap->speakers[c]; 1947 if (!spk) 1948 continue; 1949 1950 chmap[count++] = spk_to_chmap(spk); 1951 } 1952 1953 WARN_ON(count != channels); 1954} 1955 1956static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag, 1957 unsigned int size, unsigned int __user *tlv) 1958{ 1959 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); 1960 struct hda_codec *codec = info->private_data; 1961 struct hdmi_spec *spec = codec->spec; 1962 unsigned int __user *dst; 1963 int chs, count = 0; 1964 1965 if (size < 8) 1966 return -ENOMEM; 1967 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv)) 1968 return -EFAULT; 1969 size -= 8; 1970 dst = tlv + 2; 1971 for (chs = 2; chs <= spec->channels_max; chs++) { 1972 int i; 1973 struct cea_channel_speaker_allocation *cap; 1974 cap = channel_allocations; 1975 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) { 1976 int chs_bytes = chs * 4; 1977 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs); 1978 unsigned int tlv_chmap[8]; 1979 1980 if (type < 0) 1981 continue; 1982 if (size < 8) 1983 return -ENOMEM; 1984 if (put_user(type, dst) || 1985 put_user(chs_bytes, dst + 1)) 1986 return -EFAULT; 1987 dst += 2; 1988 size -= 8; 1989 count += 8; 1990 if (size < chs_bytes) 1991 return -ENOMEM; 1992 size -= chs_bytes; 1993 count += chs_bytes; 1994 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs); 1995 if (copy_to_user(dst, tlv_chmap, chs_bytes)) 1996 return -EFAULT; 1997 dst += chs; 1998 } 1999 } 2000 if (put_user(count, tlv + 1)) 2001 return -EFAULT; 2002 return 0; 2003} 2004 2005static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol, 2006 struct snd_ctl_elem_value *ucontrol) 2007{ 2008 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); 2009 struct hda_codec *codec = info->private_data; 2010 struct hdmi_spec *spec = codec->spec; 2011 int pin_idx = kcontrol->private_value; 2012 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2013 int i; 2014 2015 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++) 2016 ucontrol->value.integer.value[i] = per_pin->chmap[i]; 2017 return 0; 2018} 2019 2020static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol, 2021 struct snd_ctl_elem_value *ucontrol) 2022{ 2023 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); 2024 struct hda_codec *codec = info->private_data; 2025 struct hdmi_spec *spec = codec->spec; 2026 int pin_idx = kcontrol->private_value; 2027 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2028 unsigned int ctl_idx; 2029 struct snd_pcm_substream *substream; 2030 unsigned char chmap[8]; 2031 int i, err, ca, prepared = 0; 2032 2033 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 2034 substream = snd_pcm_chmap_substream(info, ctl_idx); 2035 if (!substream || !substream->runtime) 2036 return 0; /* just for avoiding error from alsactl restore */ 2037 switch (substream->runtime->status->state) { 2038 case SNDRV_PCM_STATE_OPEN: 2039 case SNDRV_PCM_STATE_SETUP: 2040 break; 2041 case SNDRV_PCM_STATE_PREPARED: 2042 prepared = 1; 2043 break; 2044 default: 2045 return -EBUSY; 2046 } 2047 memset(chmap, 0, sizeof(chmap)); 2048 for (i = 0; i < ARRAY_SIZE(chmap); i++) 2049 chmap[i] = ucontrol->value.integer.value[i]; 2050 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap))) 2051 return 0; 2052 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap); 2053 if (ca < 0) 2054 return -EINVAL; 2055 if (spec->ops.chmap_validate) { 2056 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap); 2057 if (err) 2058 return err; 2059 } 2060 mutex_lock(&per_pin->lock); 2061 per_pin->chmap_set = true; 2062 memcpy(per_pin->chmap, chmap, sizeof(chmap)); 2063 if (prepared) 2064 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2065 mutex_unlock(&per_pin->lock); 2066 2067 return 0; 2068} 2069 2070static int generic_hdmi_build_pcms(struct hda_codec *codec) 2071{ 2072 struct hdmi_spec *spec = codec->spec; 2073 int pin_idx; 2074 2075 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2076 struct hda_pcm *info; 2077 struct hda_pcm_stream *pstr; 2078 2079 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx); 2080 if (!info) 2081 return -ENOMEM; 2082 spec->pcm_rec[pin_idx] = info; 2083 info->pcm_type = HDA_PCM_TYPE_HDMI; 2084 info->own_chmap = true; 2085 2086 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2087 pstr->substreams = 1; 2088 pstr->ops = generic_ops; 2089 /* other pstr fields are set in open */ 2090 } 2091 2092 return 0; 2093} 2094 2095static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx) 2096{ 2097 char hdmi_str[32] = "HDMI/DP"; 2098 struct hdmi_spec *spec = codec->spec; 2099 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2100 int pcmdev = get_pcm_rec(spec, pin_idx)->device; 2101 bool phantom_jack; 2102 2103 if (pcmdev > 0) 2104 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2105 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); 2106 if (phantom_jack) 2107 strncat(hdmi_str, " Phantom", 2108 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2109 2110 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 2111 phantom_jack); 2112} 2113 2114static int generic_hdmi_build_controls(struct hda_codec *codec) 2115{ 2116 struct hdmi_spec *spec = codec->spec; 2117 int err; 2118 int pin_idx; 2119 2120 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2121 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2122 2123 err = generic_hdmi_build_jack(codec, pin_idx); 2124 if (err < 0) 2125 return err; 2126 2127 err = snd_hda_create_dig_out_ctls(codec, 2128 per_pin->pin_nid, 2129 per_pin->mux_nids[0], 2130 HDA_PCM_TYPE_HDMI); 2131 if (err < 0) 2132 return err; 2133 snd_hda_spdif_ctls_unassign(codec, pin_idx); 2134 2135 /* add control for ELD Bytes */ 2136 err = hdmi_create_eld_ctl(codec, pin_idx, 2137 get_pcm_rec(spec, pin_idx)->device); 2138 2139 if (err < 0) 2140 return err; 2141 2142 hdmi_present_sense(per_pin, 0); 2143 } 2144 2145 /* add channel maps */ 2146 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2147 struct hda_pcm *pcm; 2148 struct snd_pcm_chmap *chmap; 2149 struct snd_kcontrol *kctl; 2150 int i; 2151 2152 pcm = spec->pcm_rec[pin_idx]; 2153 if (!pcm || !pcm->pcm) 2154 break; 2155 err = snd_pcm_add_chmap_ctls(pcm->pcm, 2156 SNDRV_PCM_STREAM_PLAYBACK, 2157 NULL, 0, pin_idx, &chmap); 2158 if (err < 0) 2159 return err; 2160 /* override handlers */ 2161 chmap->private_data = codec; 2162 kctl = chmap->kctl; 2163 for (i = 0; i < kctl->count; i++) 2164 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE; 2165 kctl->info = hdmi_chmap_ctl_info; 2166 kctl->get = hdmi_chmap_ctl_get; 2167 kctl->put = hdmi_chmap_ctl_put; 2168 kctl->tlv.c = hdmi_chmap_ctl_tlv; 2169 } 2170 2171 return 0; 2172} 2173 2174static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2175{ 2176 struct hdmi_spec *spec = codec->spec; 2177 int pin_idx; 2178 2179 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2180 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2181 2182 per_pin->codec = codec; 2183 mutex_init(&per_pin->lock); 2184 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2185 eld_proc_new(per_pin, pin_idx); 2186 } 2187 return 0; 2188} 2189 2190static int generic_hdmi_init(struct hda_codec *codec) 2191{ 2192 struct hdmi_spec *spec = codec->spec; 2193 int pin_idx; 2194 2195 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2196 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2197 hda_nid_t pin_nid = per_pin->pin_nid; 2198 2199 hdmi_init_pin(codec, pin_nid); 2200 snd_hda_jack_detect_enable_callback(codec, pin_nid, 2201 codec->jackpoll_interval > 0 ? jack_callback : NULL); 2202 } 2203 return 0; 2204} 2205 2206static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2207{ 2208 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2209 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2210} 2211 2212static void hdmi_array_free(struct hdmi_spec *spec) 2213{ 2214 snd_array_free(&spec->pins); 2215 snd_array_free(&spec->cvts); 2216} 2217 2218static void generic_hdmi_free(struct hda_codec *codec) 2219{ 2220 struct hdmi_spec *spec = codec->spec; 2221 int pin_idx; 2222 2223 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) 2224 snd_hdac_i915_register_notifier(NULL); 2225 2226 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2227 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2228 2229 cancel_delayed_work_sync(&per_pin->work); 2230 eld_proc_free(per_pin); 2231 } 2232 2233 hdmi_array_free(spec); 2234 kfree(spec); 2235} 2236 2237#ifdef CONFIG_PM 2238static int generic_hdmi_resume(struct hda_codec *codec) 2239{ 2240 struct hdmi_spec *spec = codec->spec; 2241 int pin_idx; 2242 2243 codec->patch_ops.init(codec); 2244 regcache_sync(codec->core.regmap); 2245 2246 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2247 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2248 hdmi_present_sense(per_pin, 1); 2249 } 2250 return 0; 2251} 2252#endif 2253 2254static const struct hda_codec_ops generic_hdmi_patch_ops = { 2255 .init = generic_hdmi_init, 2256 .free = generic_hdmi_free, 2257 .build_pcms = generic_hdmi_build_pcms, 2258 .build_controls = generic_hdmi_build_controls, 2259 .unsol_event = hdmi_unsol_event, 2260#ifdef CONFIG_PM 2261 .resume = generic_hdmi_resume, 2262#endif 2263}; 2264 2265static const struct hdmi_ops generic_standard_hdmi_ops = { 2266 .pin_get_eld = snd_hdmi_get_eld, 2267 .pin_get_slot_channel = hdmi_pin_get_slot_channel, 2268 .pin_set_slot_channel = hdmi_pin_set_slot_channel, 2269 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2270 .pin_hbr_setup = hdmi_pin_hbr_setup, 2271 .setup_stream = hdmi_setup_stream, 2272 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type, 2273 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap, 2274}; 2275 2276 2277static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 2278 hda_nid_t nid) 2279{ 2280 struct hdmi_spec *spec = codec->spec; 2281 hda_nid_t conns[4]; 2282 int nconns; 2283 2284 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns)); 2285 if (nconns == spec->num_cvts && 2286 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t))) 2287 return; 2288 2289 /* override pins connection list */ 2290 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid); 2291 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids); 2292} 2293 2294#define INTEL_VENDOR_NID 0x08 2295#define INTEL_GET_VENDOR_VERB 0xf81 2296#define INTEL_SET_VENDOR_VERB 0x781 2297#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2298#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2299 2300static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2301 bool update_tree) 2302{ 2303 unsigned int vendor_param; 2304 2305 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0, 2306 INTEL_GET_VENDOR_VERB, 0); 2307 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2308 return; 2309 2310 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2311 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0, 2312 INTEL_SET_VENDOR_VERB, vendor_param); 2313 if (vendor_param == -1) 2314 return; 2315 2316 if (update_tree) 2317 snd_hda_codec_update_widgets(codec); 2318} 2319 2320static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2321{ 2322 unsigned int vendor_param; 2323 2324 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0, 2325 INTEL_GET_VENDOR_VERB, 0); 2326 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2327 return; 2328 2329 /* enable DP1.2 mode */ 2330 vendor_param |= INTEL_EN_DP12; 2331 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2332 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0, 2333 INTEL_SET_VENDOR_VERB, vendor_param); 2334} 2335 2336/* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2337 * Otherwise you may get severe h/w communication errors. 2338 */ 2339static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2340 unsigned int power_state) 2341{ 2342 if (power_state == AC_PWRST_D0) { 2343 intel_haswell_enable_all_pins(codec, false); 2344 intel_haswell_fixup_enable_dp12(codec); 2345 } 2346 2347 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2348 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2349} 2350 2351static void intel_pin_eld_notify(void *audio_ptr, int port) 2352{ 2353 struct hda_codec *codec = audio_ptr; 2354 int pin_nid = port + 0x04; 2355 2356 /* we assume only from port-B to port-D */ 2357 if (port < 1 || port > 3) 2358 return; 2359 2360 /* skip notification during system suspend (but not in runtime PM); 2361 * the state will be updated at resume 2362 */ 2363 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2364 return; 2365 2366 check_presence_and_report(codec, pin_nid); 2367} 2368 2369static int patch_generic_hdmi(struct hda_codec *codec) 2370{ 2371 struct hdmi_spec *spec; 2372 2373 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2374 if (spec == NULL) 2375 return -ENOMEM; 2376 2377 spec->ops = generic_standard_hdmi_ops; 2378 codec->spec = spec; 2379 hdmi_array_init(spec, 4); 2380 2381 if (is_haswell_plus(codec)) { 2382 intel_haswell_enable_all_pins(codec, true); 2383 intel_haswell_fixup_enable_dp12(codec); 2384 } 2385 2386 /* For Valleyview/Cherryview, only the display codec is in the display 2387 * power well and can use link_power ops to request/release the power. 2388 * For Haswell/Broadwell, the controller is also in the power well and 2389 * can cover the codec power request, and so need not set this flag. 2390 * For previous platforms, there is no such power well feature. 2391 */ 2392 if (is_valleyview_plus(codec) || is_skylake(codec) || 2393 is_broxton(codec)) 2394 codec->core.link_power_control = 1; 2395 2396 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) { 2397 codec->depop_delay = 0; 2398 spec->i915_audio_ops.audio_ptr = codec; 2399 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify; 2400 snd_hdac_i915_register_notifier(&spec->i915_audio_ops); 2401 } 2402 2403 if (hdmi_parse_codec(codec) < 0) { 2404 codec->spec = NULL; 2405 kfree(spec); 2406 return -EINVAL; 2407 } 2408 codec->patch_ops = generic_hdmi_patch_ops; 2409 if (is_haswell_plus(codec)) { 2410 codec->patch_ops.set_power_state = haswell_set_power_state; 2411 codec->dp_mst = true; 2412 } 2413 2414 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */ 2415 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) 2416 codec->auto_runtime_pm = 1; 2417 2418 generic_hdmi_init_per_pins(codec); 2419 2420 init_channel_allocations(); 2421 2422 return 0; 2423} 2424 2425/* 2426 * Shared non-generic implementations 2427 */ 2428 2429static int simple_playback_build_pcms(struct hda_codec *codec) 2430{ 2431 struct hdmi_spec *spec = codec->spec; 2432 struct hda_pcm *info; 2433 unsigned int chans; 2434 struct hda_pcm_stream *pstr; 2435 struct hdmi_spec_per_cvt *per_cvt; 2436 2437 per_cvt = get_cvt(spec, 0); 2438 chans = get_wcaps(codec, per_cvt->cvt_nid); 2439 chans = get_wcaps_channels(chans); 2440 2441 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 2442 if (!info) 2443 return -ENOMEM; 2444 spec->pcm_rec[0] = info; 2445 info->pcm_type = HDA_PCM_TYPE_HDMI; 2446 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2447 *pstr = spec->pcm_playback; 2448 pstr->nid = per_cvt->cvt_nid; 2449 if (pstr->channels_max <= 2 && chans && chans <= 16) 2450 pstr->channels_max = chans; 2451 2452 return 0; 2453} 2454 2455/* unsolicited event for jack sensing */ 2456static void simple_hdmi_unsol_event(struct hda_codec *codec, 2457 unsigned int res) 2458{ 2459 snd_hda_jack_set_dirty_all(codec); 2460 snd_hda_jack_report_sync(codec); 2461} 2462 2463/* generic_hdmi_build_jack can be used for simple_hdmi, too, 2464 * as long as spec->pins[] is set correctly 2465 */ 2466#define simple_hdmi_build_jack generic_hdmi_build_jack 2467 2468static int simple_playback_build_controls(struct hda_codec *codec) 2469{ 2470 struct hdmi_spec *spec = codec->spec; 2471 struct hdmi_spec_per_cvt *per_cvt; 2472 int err; 2473 2474 per_cvt = get_cvt(spec, 0); 2475 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 2476 per_cvt->cvt_nid, 2477 HDA_PCM_TYPE_HDMI); 2478 if (err < 0) 2479 return err; 2480 return simple_hdmi_build_jack(codec, 0); 2481} 2482 2483static int simple_playback_init(struct hda_codec *codec) 2484{ 2485 struct hdmi_spec *spec = codec->spec; 2486 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 2487 hda_nid_t pin = per_pin->pin_nid; 2488 2489 snd_hda_codec_write(codec, pin, 0, 2490 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 2491 /* some codecs require to unmute the pin */ 2492 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 2493 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 2494 AMP_OUT_UNMUTE); 2495 snd_hda_jack_detect_enable(codec, pin); 2496 return 0; 2497} 2498 2499static void simple_playback_free(struct hda_codec *codec) 2500{ 2501 struct hdmi_spec *spec = codec->spec; 2502 2503 hdmi_array_free(spec); 2504 kfree(spec); 2505} 2506 2507/* 2508 * Nvidia specific implementations 2509 */ 2510 2511#define Nv_VERB_SET_Channel_Allocation 0xF79 2512#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 2513#define Nv_VERB_SET_Audio_Protection_On 0xF98 2514#define Nv_VERB_SET_Audio_Protection_Off 0xF99 2515 2516#define nvhdmi_master_con_nid_7x 0x04 2517#define nvhdmi_master_pin_nid_7x 0x05 2518 2519static const hda_nid_t nvhdmi_con_nids_7x[4] = { 2520 /*front, rear, clfe, rear_surr */ 2521 0x6, 0x8, 0xa, 0xc, 2522}; 2523 2524static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 2525 /* set audio protect on */ 2526 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2527 /* enable digital output on pin widget */ 2528 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2529 {} /* terminator */ 2530}; 2531 2532static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 2533 /* set audio protect on */ 2534 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2535 /* enable digital output on pin widget */ 2536 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2537 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2538 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2539 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2540 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2541 {} /* terminator */ 2542}; 2543 2544#ifdef LIMITED_RATE_FMT_SUPPORT 2545/* support only the safe format and rate */ 2546#define SUPPORTED_RATES SNDRV_PCM_RATE_48000 2547#define SUPPORTED_MAXBPS 16 2548#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 2549#else 2550/* support all rates and formats */ 2551#define SUPPORTED_RATES \ 2552 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 2553 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 2554 SNDRV_PCM_RATE_192000) 2555#define SUPPORTED_MAXBPS 24 2556#define SUPPORTED_FORMATS \ 2557 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 2558#endif 2559 2560static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 2561{ 2562 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 2563 return 0; 2564} 2565 2566static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 2567{ 2568 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 2569 return 0; 2570} 2571 2572static unsigned int channels_2_6_8[] = { 2573 2, 6, 8 2574}; 2575 2576static unsigned int channels_2_8[] = { 2577 2, 8 2578}; 2579 2580static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 2581 .count = ARRAY_SIZE(channels_2_6_8), 2582 .list = channels_2_6_8, 2583 .mask = 0, 2584}; 2585 2586static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 2587 .count = ARRAY_SIZE(channels_2_8), 2588 .list = channels_2_8, 2589 .mask = 0, 2590}; 2591 2592static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 2593 struct hda_codec *codec, 2594 struct snd_pcm_substream *substream) 2595{ 2596 struct hdmi_spec *spec = codec->spec; 2597 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 2598 2599 switch (codec->preset->vendor_id) { 2600 case 0x10de0002: 2601 case 0x10de0003: 2602 case 0x10de0005: 2603 case 0x10de0006: 2604 hw_constraints_channels = &hw_constraints_2_8_channels; 2605 break; 2606 case 0x10de0007: 2607 hw_constraints_channels = &hw_constraints_2_6_8_channels; 2608 break; 2609 default: 2610 break; 2611 } 2612 2613 if (hw_constraints_channels != NULL) { 2614 snd_pcm_hw_constraint_list(substream->runtime, 0, 2615 SNDRV_PCM_HW_PARAM_CHANNELS, 2616 hw_constraints_channels); 2617 } else { 2618 snd_pcm_hw_constraint_step(substream->runtime, 0, 2619 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 2620 } 2621 2622 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 2623} 2624 2625static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 2626 struct hda_codec *codec, 2627 struct snd_pcm_substream *substream) 2628{ 2629 struct hdmi_spec *spec = codec->spec; 2630 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 2631} 2632 2633static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2634 struct hda_codec *codec, 2635 unsigned int stream_tag, 2636 unsigned int format, 2637 struct snd_pcm_substream *substream) 2638{ 2639 struct hdmi_spec *spec = codec->spec; 2640 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 2641 stream_tag, format, substream); 2642} 2643 2644static const struct hda_pcm_stream simple_pcm_playback = { 2645 .substreams = 1, 2646 .channels_min = 2, 2647 .channels_max = 2, 2648 .ops = { 2649 .open = simple_playback_pcm_open, 2650 .close = simple_playback_pcm_close, 2651 .prepare = simple_playback_pcm_prepare 2652 }, 2653}; 2654 2655static const struct hda_codec_ops simple_hdmi_patch_ops = { 2656 .build_controls = simple_playback_build_controls, 2657 .build_pcms = simple_playback_build_pcms, 2658 .init = simple_playback_init, 2659 .free = simple_playback_free, 2660 .unsol_event = simple_hdmi_unsol_event, 2661}; 2662 2663static int patch_simple_hdmi(struct hda_codec *codec, 2664 hda_nid_t cvt_nid, hda_nid_t pin_nid) 2665{ 2666 struct hdmi_spec *spec; 2667 struct hdmi_spec_per_cvt *per_cvt; 2668 struct hdmi_spec_per_pin *per_pin; 2669 2670 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2671 if (!spec) 2672 return -ENOMEM; 2673 2674 codec->spec = spec; 2675 hdmi_array_init(spec, 1); 2676 2677 spec->multiout.num_dacs = 0; /* no analog */ 2678 spec->multiout.max_channels = 2; 2679 spec->multiout.dig_out_nid = cvt_nid; 2680 spec->num_cvts = 1; 2681 spec->num_pins = 1; 2682 per_pin = snd_array_new(&spec->pins); 2683 per_cvt = snd_array_new(&spec->cvts); 2684 if (!per_pin || !per_cvt) { 2685 simple_playback_free(codec); 2686 return -ENOMEM; 2687 } 2688 per_cvt->cvt_nid = cvt_nid; 2689 per_pin->pin_nid = pin_nid; 2690 spec->pcm_playback = simple_pcm_playback; 2691 2692 codec->patch_ops = simple_hdmi_patch_ops; 2693 2694 return 0; 2695} 2696 2697static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 2698 int channels) 2699{ 2700 unsigned int chanmask; 2701 int chan = channels ? (channels - 1) : 1; 2702 2703 switch (channels) { 2704 default: 2705 case 0: 2706 case 2: 2707 chanmask = 0x00; 2708 break; 2709 case 4: 2710 chanmask = 0x08; 2711 break; 2712 case 6: 2713 chanmask = 0x0b; 2714 break; 2715 case 8: 2716 chanmask = 0x13; 2717 break; 2718 } 2719 2720 /* Set the audio infoframe channel allocation and checksum fields. The 2721 * channel count is computed implicitly by the hardware. */ 2722 snd_hda_codec_write(codec, 0x1, 0, 2723 Nv_VERB_SET_Channel_Allocation, chanmask); 2724 2725 snd_hda_codec_write(codec, 0x1, 0, 2726 Nv_VERB_SET_Info_Frame_Checksum, 2727 (0x71 - chan - chanmask)); 2728} 2729 2730static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 2731 struct hda_codec *codec, 2732 struct snd_pcm_substream *substream) 2733{ 2734 struct hdmi_spec *spec = codec->spec; 2735 int i; 2736 2737 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 2738 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 2739 for (i = 0; i < 4; i++) { 2740 /* set the stream id */ 2741 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 2742 AC_VERB_SET_CHANNEL_STREAMID, 0); 2743 /* set the stream format */ 2744 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 2745 AC_VERB_SET_STREAM_FORMAT, 0); 2746 } 2747 2748 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 2749 * streams are disabled. */ 2750 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 2751 2752 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 2753} 2754 2755static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 2756 struct hda_codec *codec, 2757 unsigned int stream_tag, 2758 unsigned int format, 2759 struct snd_pcm_substream *substream) 2760{ 2761 int chs; 2762 unsigned int dataDCC2, channel_id; 2763 int i; 2764 struct hdmi_spec *spec = codec->spec; 2765 struct hda_spdif_out *spdif; 2766 struct hdmi_spec_per_cvt *per_cvt; 2767 2768 mutex_lock(&codec->spdif_mutex); 2769 per_cvt = get_cvt(spec, 0); 2770 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 2771 2772 chs = substream->runtime->channels; 2773 2774 dataDCC2 = 0x2; 2775 2776 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 2777 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 2778 snd_hda_codec_write(codec, 2779 nvhdmi_master_con_nid_7x, 2780 0, 2781 AC_VERB_SET_DIGI_CONVERT_1, 2782 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 2783 2784 /* set the stream id */ 2785 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 2786 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 2787 2788 /* set the stream format */ 2789 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 2790 AC_VERB_SET_STREAM_FORMAT, format); 2791 2792 /* turn on again (if needed) */ 2793 /* enable and set the channel status audio/data flag */ 2794 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 2795 snd_hda_codec_write(codec, 2796 nvhdmi_master_con_nid_7x, 2797 0, 2798 AC_VERB_SET_DIGI_CONVERT_1, 2799 spdif->ctls & 0xff); 2800 snd_hda_codec_write(codec, 2801 nvhdmi_master_con_nid_7x, 2802 0, 2803 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 2804 } 2805 2806 for (i = 0; i < 4; i++) { 2807 if (chs == 2) 2808 channel_id = 0; 2809 else 2810 channel_id = i * 2; 2811 2812 /* turn off SPDIF once; 2813 *otherwise the IEC958 bits won't be updated 2814 */ 2815 if (codec->spdif_status_reset && 2816 (spdif->ctls & AC_DIG1_ENABLE)) 2817 snd_hda_codec_write(codec, 2818 nvhdmi_con_nids_7x[i], 2819 0, 2820 AC_VERB_SET_DIGI_CONVERT_1, 2821 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 2822 /* set the stream id */ 2823 snd_hda_codec_write(codec, 2824 nvhdmi_con_nids_7x[i], 2825 0, 2826 AC_VERB_SET_CHANNEL_STREAMID, 2827 (stream_tag << 4) | channel_id); 2828 /* set the stream format */ 2829 snd_hda_codec_write(codec, 2830 nvhdmi_con_nids_7x[i], 2831 0, 2832 AC_VERB_SET_STREAM_FORMAT, 2833 format); 2834 /* turn on again (if needed) */ 2835 /* enable and set the channel status audio/data flag */ 2836 if (codec->spdif_status_reset && 2837 (spdif->ctls & AC_DIG1_ENABLE)) { 2838 snd_hda_codec_write(codec, 2839 nvhdmi_con_nids_7x[i], 2840 0, 2841 AC_VERB_SET_DIGI_CONVERT_1, 2842 spdif->ctls & 0xff); 2843 snd_hda_codec_write(codec, 2844 nvhdmi_con_nids_7x[i], 2845 0, 2846 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 2847 } 2848 } 2849 2850 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 2851 2852 mutex_unlock(&codec->spdif_mutex); 2853 return 0; 2854} 2855 2856static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 2857 .substreams = 1, 2858 .channels_min = 2, 2859 .channels_max = 8, 2860 .nid = nvhdmi_master_con_nid_7x, 2861 .rates = SUPPORTED_RATES, 2862 .maxbps = SUPPORTED_MAXBPS, 2863 .formats = SUPPORTED_FORMATS, 2864 .ops = { 2865 .open = simple_playback_pcm_open, 2866 .close = nvhdmi_8ch_7x_pcm_close, 2867 .prepare = nvhdmi_8ch_7x_pcm_prepare 2868 }, 2869}; 2870 2871static int patch_nvhdmi_2ch(struct hda_codec *codec) 2872{ 2873 struct hdmi_spec *spec; 2874 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 2875 nvhdmi_master_pin_nid_7x); 2876 if (err < 0) 2877 return err; 2878 2879 codec->patch_ops.init = nvhdmi_7x_init_2ch; 2880 /* override the PCM rates, etc, as the codec doesn't give full list */ 2881 spec = codec->spec; 2882 spec->pcm_playback.rates = SUPPORTED_RATES; 2883 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 2884 spec->pcm_playback.formats = SUPPORTED_FORMATS; 2885 return 0; 2886} 2887 2888static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 2889{ 2890 struct hdmi_spec *spec = codec->spec; 2891 int err = simple_playback_build_pcms(codec); 2892 if (!err) { 2893 struct hda_pcm *info = get_pcm_rec(spec, 0); 2894 info->own_chmap = true; 2895 } 2896 return err; 2897} 2898 2899static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 2900{ 2901 struct hdmi_spec *spec = codec->spec; 2902 struct hda_pcm *info; 2903 struct snd_pcm_chmap *chmap; 2904 int err; 2905 2906 err = simple_playback_build_controls(codec); 2907 if (err < 0) 2908 return err; 2909 2910 /* add channel maps */ 2911 info = get_pcm_rec(spec, 0); 2912 err = snd_pcm_add_chmap_ctls(info->pcm, 2913 SNDRV_PCM_STREAM_PLAYBACK, 2914 snd_pcm_alt_chmaps, 8, 0, &chmap); 2915 if (err < 0) 2916 return err; 2917 switch (codec->preset->vendor_id) { 2918 case 0x10de0002: 2919 case 0x10de0003: 2920 case 0x10de0005: 2921 case 0x10de0006: 2922 chmap->channel_mask = (1U << 2) | (1U << 8); 2923 break; 2924 case 0x10de0007: 2925 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 2926 } 2927 return 0; 2928} 2929 2930static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 2931{ 2932 struct hdmi_spec *spec; 2933 int err = patch_nvhdmi_2ch(codec); 2934 if (err < 0) 2935 return err; 2936 spec = codec->spec; 2937 spec->multiout.max_channels = 8; 2938 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 2939 codec->patch_ops.init = nvhdmi_7x_init_8ch; 2940 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 2941 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 2942 2943 /* Initialize the audio infoframe channel mask and checksum to something 2944 * valid */ 2945 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 2946 2947 return 0; 2948} 2949 2950/* 2951 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 2952 * - 0x10de0015 2953 * - 0x10de0040 2954 */ 2955static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap, 2956 int channels) 2957{ 2958 if (cap->ca_index == 0x00 && channels == 2) 2959 return SNDRV_CTL_TLVT_CHMAP_FIXED; 2960 2961 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels); 2962} 2963 2964static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map) 2965{ 2966 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 2967 return -EINVAL; 2968 2969 return 0; 2970} 2971 2972static int patch_nvhdmi(struct hda_codec *codec) 2973{ 2974 struct hdmi_spec *spec; 2975 int err; 2976 2977 err = patch_generic_hdmi(codec); 2978 if (err) 2979 return err; 2980 2981 spec = codec->spec; 2982 spec->dyn_pin_out = true; 2983 2984 spec->ops.chmap_cea_alloc_validate_get_type = 2985 nvhdmi_chmap_cea_alloc_validate_get_type; 2986 spec->ops.chmap_validate = nvhdmi_chmap_validate; 2987 2988 return 0; 2989} 2990 2991/* 2992 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 2993 * accessed using vendor-defined verbs. These registers can be used for 2994 * interoperability between the HDA and HDMI drivers. 2995 */ 2996 2997/* Audio Function Group node */ 2998#define NVIDIA_AFG_NID 0x01 2999 3000/* 3001 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3002 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3003 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3004 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3005 * additional bit (at position 30) to signal the validity of the format. 3006 * 3007 * | 31 | 30 | 29 16 | 15 0 | 3008 * +---------+-------+--------+--------+ 3009 * | TRIGGER | VALID | UNUSED | FORMAT | 3010 * +-----------------------------------| 3011 * 3012 * Note that for the trigger bit to take effect it needs to change value 3013 * (i.e. it needs to be toggled). 3014 */ 3015#define NVIDIA_GET_SCRATCH0 0xfa6 3016#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3017#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3018#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3019#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3020#define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3021#define NVIDIA_SCRATCH_VALID (1 << 6) 3022 3023#define NVIDIA_GET_SCRATCH1 0xfab 3024#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3025#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3026#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3027#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3028 3029/* 3030 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3031 * the format is invalidated so that the HDMI codec can be disabled. 3032 */ 3033static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3034{ 3035 unsigned int value; 3036 3037 /* bits [31:30] contain the trigger and valid bits */ 3038 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3039 NVIDIA_GET_SCRATCH0, 0); 3040 value = (value >> 24) & 0xff; 3041 3042 /* bits [15:0] are used to store the HDA format */ 3043 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3044 NVIDIA_SET_SCRATCH0_BYTE0, 3045 (format >> 0) & 0xff); 3046 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3047 NVIDIA_SET_SCRATCH0_BYTE1, 3048 (format >> 8) & 0xff); 3049 3050 /* bits [16:24] are unused */ 3051 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3052 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3053 3054 /* 3055 * Bit 30 signals that the data is valid and hence that HDMI audio can 3056 * be enabled. 3057 */ 3058 if (format == 0) 3059 value &= ~NVIDIA_SCRATCH_VALID; 3060 else 3061 value |= NVIDIA_SCRATCH_VALID; 3062 3063 /* 3064 * Whenever the trigger bit is toggled, an interrupt is raised in the 3065 * HDMI codec. The HDMI driver will use that as trigger to update its 3066 * configuration. 3067 */ 3068 value ^= NVIDIA_SCRATCH_TRIGGER; 3069 3070 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3071 NVIDIA_SET_SCRATCH0_BYTE3, value); 3072} 3073 3074static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3075 struct hda_codec *codec, 3076 unsigned int stream_tag, 3077 unsigned int format, 3078 struct snd_pcm_substream *substream) 3079{ 3080 int err; 3081 3082 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3083 format, substream); 3084 if (err < 0) 3085 return err; 3086 3087 /* notify the HDMI codec of the format change */ 3088 tegra_hdmi_set_format(codec, format); 3089 3090 return 0; 3091} 3092 3093static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3094 struct hda_codec *codec, 3095 struct snd_pcm_substream *substream) 3096{ 3097 /* invalidate the format in the HDMI codec */ 3098 tegra_hdmi_set_format(codec, 0); 3099 3100 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3101} 3102 3103static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3104{ 3105 struct hdmi_spec *spec = codec->spec; 3106 unsigned int i; 3107 3108 for (i = 0; i < spec->num_pins; i++) { 3109 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3110 3111 if (pcm->pcm_type == type) 3112 return pcm; 3113 } 3114 3115 return NULL; 3116} 3117 3118static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3119{ 3120 struct hda_pcm_stream *stream; 3121 struct hda_pcm *pcm; 3122 int err; 3123 3124 err = generic_hdmi_build_pcms(codec); 3125 if (err < 0) 3126 return err; 3127 3128 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3129 if (!pcm) 3130 return -ENODEV; 3131 3132 /* 3133 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3134 * codec about format changes. 3135 */ 3136 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3137 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3138 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3139 3140 return 0; 3141} 3142 3143static int patch_tegra_hdmi(struct hda_codec *codec) 3144{ 3145 int err; 3146 3147 err = patch_generic_hdmi(codec); 3148 if (err) 3149 return err; 3150 3151 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3152 3153 return 0; 3154} 3155 3156/* 3157 * ATI/AMD-specific implementations 3158 */ 3159 3160#define is_amdhdmi_rev3_or_later(codec) \ 3161 ((codec)->core.vendor_id == 0x1002aa01 && \ 3162 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3163#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3164 3165/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3166#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3167#define ATI_VERB_SET_DOWNMIX_INFO 0x772 3168#define ATI_VERB_SET_MULTICHANNEL_01 0x777 3169#define ATI_VERB_SET_MULTICHANNEL_23 0x778 3170#define ATI_VERB_SET_MULTICHANNEL_45 0x779 3171#define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3172#define ATI_VERB_SET_HBR_CONTROL 0x77c 3173#define ATI_VERB_SET_MULTICHANNEL_1 0x785 3174#define ATI_VERB_SET_MULTICHANNEL_3 0x786 3175#define ATI_VERB_SET_MULTICHANNEL_5 0x787 3176#define ATI_VERB_SET_MULTICHANNEL_7 0x788 3177#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3178#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3179#define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3180#define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3181#define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3182#define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3183#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3184#define ATI_VERB_GET_HBR_CONTROL 0xf7c 3185#define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3186#define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3187#define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3188#define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3189#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3190 3191/* AMD specific HDA cvt verbs */ 3192#define ATI_VERB_SET_RAMP_RATE 0x770 3193#define ATI_VERB_GET_RAMP_RATE 0xf70 3194 3195#define ATI_OUT_ENABLE 0x1 3196 3197#define ATI_MULTICHANNEL_MODE_PAIRED 0 3198#define ATI_MULTICHANNEL_MODE_SINGLE 1 3199 3200#define ATI_HBR_CAPABLE 0x01 3201#define ATI_HBR_ENABLE 0x10 3202 3203static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3204 unsigned char *buf, int *eld_size) 3205{ 3206 /* call hda_eld.c ATI/AMD-specific function */ 3207 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3208 is_amdhdmi_rev3_or_later(codec)); 3209} 3210 3211static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca, 3212 int active_channels, int conn_type) 3213{ 3214 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3215} 3216 3217static int atihdmi_paired_swap_fc_lfe(int pos) 3218{ 3219 /* 3220 * ATI/AMD have automatic FC/LFE swap built-in 3221 * when in pairwise mapping mode. 3222 */ 3223 3224 switch (pos) { 3225 /* see channel_allocations[].speakers[] */ 3226 case 2: return 3; 3227 case 3: return 2; 3228 default: break; 3229 } 3230 3231 return pos; 3232} 3233 3234static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map) 3235{ 3236 struct cea_channel_speaker_allocation *cap; 3237 int i, j; 3238 3239 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3240 3241 cap = &channel_allocations[get_channel_allocation_order(ca)]; 3242 for (i = 0; i < chs; ++i) { 3243 int mask = to_spk_mask(map[i]); 3244 bool ok = false; 3245 bool companion_ok = false; 3246 3247 if (!mask) 3248 continue; 3249 3250 for (j = 0 + i % 2; j < 8; j += 2) { 3251 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3252 if (cap->speakers[chan_idx] == mask) { 3253 /* channel is in a supported position */ 3254 ok = true; 3255 3256 if (i % 2 == 0 && i + 1 < chs) { 3257 /* even channel, check the odd companion */ 3258 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3259 int comp_mask_req = to_spk_mask(map[i+1]); 3260 int comp_mask_act = cap->speakers[comp_chan_idx]; 3261 3262 if (comp_mask_req == comp_mask_act) 3263 companion_ok = true; 3264 else 3265 return -EINVAL; 3266 } 3267 break; 3268 } 3269 } 3270 3271 if (!ok) 3272 return -EINVAL; 3273 3274 if (companion_ok) 3275 i++; /* companion channel already checked */ 3276 } 3277 3278 return 0; 3279} 3280 3281static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid, 3282 int hdmi_slot, int stream_channel) 3283{ 3284 int verb; 3285 int ati_channel_setup = 0; 3286 3287 if (hdmi_slot > 7) 3288 return -EINVAL; 3289 3290 if (!has_amd_full_remap_support(codec)) { 3291 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3292 3293 /* In case this is an odd slot but without stream channel, do not 3294 * disable the slot since the corresponding even slot could have a 3295 * channel. In case neither have a channel, the slot pair will be 3296 * disabled when this function is called for the even slot. */ 3297 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3298 return 0; 3299 3300 hdmi_slot -= hdmi_slot % 2; 3301 3302 if (stream_channel != 0xf) 3303 stream_channel -= stream_channel % 2; 3304 } 3305 3306 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3307 3308 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3309 3310 if (stream_channel != 0xf) 3311 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3312 3313 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3314} 3315 3316static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid, 3317 int asp_slot) 3318{ 3319 bool was_odd = false; 3320 int ati_asp_slot = asp_slot; 3321 int verb; 3322 int ati_channel_setup; 3323 3324 if (asp_slot > 7) 3325 return -EINVAL; 3326 3327 if (!has_amd_full_remap_support(codec)) { 3328 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3329 if (ati_asp_slot % 2 != 0) { 3330 ati_asp_slot -= 1; 3331 was_odd = true; 3332 } 3333 } 3334 3335 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3336 3337 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3338 3339 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3340 return 0xf; 3341 3342 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3343} 3344 3345static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap, 3346 int channels) 3347{ 3348 int c; 3349 3350 /* 3351 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3352 * we need to take that into account (a single channel may take 2 3353 * channel slots if we need to carry a silent channel next to it). 3354 * On Rev3+ AMD codecs this function is not used. 3355 */ 3356 int chanpairs = 0; 3357 3358 /* We only produce even-numbered channel count TLVs */ 3359 if ((channels % 2) != 0) 3360 return -1; 3361 3362 for (c = 0; c < 7; c += 2) { 3363 if (cap->speakers[c] || cap->speakers[c+1]) 3364 chanpairs++; 3365 } 3366 3367 if (chanpairs * 2 != channels) 3368 return -1; 3369 3370 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 3371} 3372 3373static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap, 3374 unsigned int *chmap, int channels) 3375{ 3376 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 3377 int count = 0; 3378 int c; 3379 3380 for (c = 7; c >= 0; c--) { 3381 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 3382 int spk = cap->speakers[chan]; 3383 if (!spk) { 3384 /* add N/A channel if the companion channel is occupied */ 3385 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 3386 chmap[count++] = SNDRV_CHMAP_NA; 3387 3388 continue; 3389 } 3390 3391 chmap[count++] = spk_to_chmap(spk); 3392 } 3393 3394 WARN_ON(count != channels); 3395} 3396 3397static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 3398 bool hbr) 3399{ 3400 int hbr_ctl, hbr_ctl_new; 3401 3402 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 3403 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 3404 if (hbr) 3405 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 3406 else 3407 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 3408 3409 codec_dbg(codec, 3410 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 3411 pin_nid, 3412 hbr_ctl == hbr_ctl_new ? "" : "new-", 3413 hbr_ctl_new); 3414 3415 if (hbr_ctl != hbr_ctl_new) 3416 snd_hda_codec_write(codec, pin_nid, 0, 3417 ATI_VERB_SET_HBR_CONTROL, 3418 hbr_ctl_new); 3419 3420 } else if (hbr) 3421 return -EINVAL; 3422 3423 return 0; 3424} 3425 3426static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 3427 hda_nid_t pin_nid, u32 stream_tag, int format) 3428{ 3429 3430 if (is_amdhdmi_rev3_or_later(codec)) { 3431 int ramp_rate = 180; /* default as per AMD spec */ 3432 /* disable ramp-up/down for non-pcm as per AMD spec */ 3433 if (format & AC_FMT_TYPE_NON_PCM) 3434 ramp_rate = 0; 3435 3436 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 3437 } 3438 3439 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 3440} 3441 3442 3443static int atihdmi_init(struct hda_codec *codec) 3444{ 3445 struct hdmi_spec *spec = codec->spec; 3446 int pin_idx, err; 3447 3448 err = generic_hdmi_init(codec); 3449 3450 if (err) 3451 return err; 3452 3453 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 3454 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 3455 3456 /* make sure downmix information in infoframe is zero */ 3457 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 3458 3459 /* enable channel-wise remap mode if supported */ 3460 if (has_amd_full_remap_support(codec)) 3461 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 3462 ATI_VERB_SET_MULTICHANNEL_MODE, 3463 ATI_MULTICHANNEL_MODE_SINGLE); 3464 } 3465 3466 return 0; 3467} 3468 3469static int patch_atihdmi(struct hda_codec *codec) 3470{ 3471 struct hdmi_spec *spec; 3472 struct hdmi_spec_per_cvt *per_cvt; 3473 int err, cvt_idx; 3474 3475 err = patch_generic_hdmi(codec); 3476 3477 if (err) 3478 return err; 3479 3480 codec->patch_ops.init = atihdmi_init; 3481 3482 spec = codec->spec; 3483 3484 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 3485 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 3486 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 3487 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 3488 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 3489 spec->ops.setup_stream = atihdmi_setup_stream; 3490 3491 if (!has_amd_full_remap_support(codec)) { 3492 /* override to ATI/AMD-specific versions with pairwise mapping */ 3493 spec->ops.chmap_cea_alloc_validate_get_type = 3494 atihdmi_paired_chmap_cea_alloc_validate_get_type; 3495 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap; 3496 spec->ops.chmap_validate = atihdmi_paired_chmap_validate; 3497 } 3498 3499 /* ATI/AMD converters do not advertise all of their capabilities */ 3500 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 3501 per_cvt = get_cvt(spec, cvt_idx); 3502 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 3503 per_cvt->rates |= SUPPORTED_RATES; 3504 per_cvt->formats |= SUPPORTED_FORMATS; 3505 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 3506 } 3507 3508 spec->channels_max = max(spec->channels_max, 8u); 3509 3510 return 0; 3511} 3512 3513/* VIA HDMI Implementation */ 3514#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 3515#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 3516 3517static int patch_via_hdmi(struct hda_codec *codec) 3518{ 3519 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 3520} 3521 3522/* 3523 * patch entries 3524 */ 3525static const struct hda_device_id snd_hda_id_hdmi[] = { 3526HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 3527HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 3528HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 3529HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 3530HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 3531HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 3532HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 3533HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3534HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3535HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3536HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3537HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 3538HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi), 3539HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi), 3540HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi), 3541HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi), 3542HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi), 3543HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi), 3544HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi), 3545HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi), 3546HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi), 3547HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi), 3548HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi), 3549/* 17 is known to be absent */ 3550HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi), 3551HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi), 3552HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi), 3553HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi), 3554HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi), 3555HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 3556HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 3557HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 3558HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 3559HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 3560HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 3561HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 3562HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 3563HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 3564HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 3565HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 3566HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 3567HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 3568HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 3569HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 3570HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 3571HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 3572HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 3573HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 3574HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 3575HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 3576HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi), 3577HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 3578HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 3579HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 3580HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi), 3581HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi), 3582HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi), 3583HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi), 3584HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi), 3585HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi), 3586HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi), 3587HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 3588HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi), 3589HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi), 3590HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 3591/* special ID for generic HDMI */ 3592HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 3593{} /* terminator */ 3594}; 3595MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 3596 3597MODULE_LICENSE("GPL"); 3598MODULE_DESCRIPTION("HDMI HD-audio codec"); 3599MODULE_ALIAS("snd-hda-codec-intelhdmi"); 3600MODULE_ALIAS("snd-hda-codec-nvhdmi"); 3601MODULE_ALIAS("snd-hda-codec-atihdmi"); 3602 3603static struct hda_codec_driver hdmi_driver = { 3604 .id = snd_hda_id_hdmi, 3605}; 3606 3607module_hda_codec_driver(hdmi_driver); 3608