1/* 2 * Driver for the Synopsys DesignWare DMA Controller 3 * 4 * Copyright (C) 2007 Atmel Corporation 5 * Copyright (C) 2010-2011 ST Microelectronics 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#ifndef _PLATFORM_DATA_DMA_DW_H 12#define _PLATFORM_DATA_DMA_DW_H 13 14#include <linux/device.h> 15 16#define DW_DMA_MAX_NR_MASTERS 4 17 18/** 19 * struct dw_dma_slave - Controller-specific information about a slave 20 * 21 * @dma_dev: required DMA master device 22 * @src_id: src request line 23 * @dst_id: dst request line 24 * @src_master: src master for transfers on allocated channel. 25 * @dst_master: dest master for transfers on allocated channel. 26 */ 27struct dw_dma_slave { 28 struct device *dma_dev; 29 u8 src_id; 30 u8 dst_id; 31 u8 src_master; 32 u8 dst_master; 33}; 34 35/** 36 * struct dw_dma_platform_data - Controller configuration parameters 37 * @nr_channels: Number of channels supported by hardware (max 8) 38 * @is_private: The device channels should be marked as private and not for 39 * by the general purpose DMA channel allocator. 40 * @is_memcpy: The device channels do support memory-to-memory transfers. 41 * @chan_allocation_order: Allocate channels starting from 0 or 7 42 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. 43 * @block_size: Maximum block size supported by the controller 44 * @nr_masters: Number of AHB masters supported by the controller 45 * @data_width: Maximum data width supported by hardware per AHB master 46 * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) 47 */ 48struct dw_dma_platform_data { 49 unsigned int nr_channels; 50 bool is_private; 51 bool is_memcpy; 52#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ 53#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ 54 unsigned char chan_allocation_order; 55#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ 56#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ 57 unsigned char chan_priority; 58 unsigned short block_size; 59 unsigned char nr_masters; 60 unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; 61}; 62 63#endif /* _PLATFORM_DATA_DMA_DW_H */ 64