1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16 #ifndef LINUX_PCI_H
17 #define LINUX_PCI_H
18
19
20 #include <linux/mod_devicetable.h>
21
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
31 #include <linux/io.h>
32 #include <linux/resource_ext.h>
33 #include <uapi/linux/pci.h>
34
35 #include <linux/pci_ids.h>
36
37 /*
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
41 *
42 * 7:3 = slot
43 * 2:0 = function
44 *
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
48 */
49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
52
53 /* pci_slot represents a physical slot */
54 struct pci_slot {
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
59 struct kobject kobj;
60 };
61
pci_slot_name(const struct pci_slot * slot)62 static inline const char *pci_slot_name(const struct pci_slot *slot)
63 {
64 return kobject_name(&slot->kobj);
65 }
66
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
68 enum pci_mmap_state {
69 pci_mmap_io,
70 pci_mmap_mem
71 };
72
73 /* This defines the direction arg to the DMA mapping routines. */
74 #define PCI_DMA_BIDIRECTIONAL 0
75 #define PCI_DMA_TODEVICE 1
76 #define PCI_DMA_FROMDEVICE 2
77 #define PCI_DMA_NONE 3
78
79 /*
80 * For PCI devices, the region numbers are assigned this way:
81 */
82 enum {
83 /* #0-5: standard PCI resources */
84 PCI_STD_RESOURCES,
85 PCI_STD_RESOURCE_END = 5,
86
87 /* #6: expansion ROM resource */
88 PCI_ROM_RESOURCE,
89
90 /* device specific resources */
91 #ifdef CONFIG_PCI_IOV
92 PCI_IOV_RESOURCES,
93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
94 #endif
95
96 /* resources assigned to buses behind the bridge */
97 #define PCI_BRIDGE_RESOURCE_NUM 4
98
99 PCI_BRIDGE_RESOURCES,
100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101 PCI_BRIDGE_RESOURCE_NUM - 1,
102
103 /* total resources associated with a PCI device */
104 PCI_NUM_RESOURCES,
105
106 /* preserve this for compatibility */
107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
108 };
109
110 typedef int __bitwise pci_power_t;
111
112 #define PCI_D0 ((pci_power_t __force) 0)
113 #define PCI_D1 ((pci_power_t __force) 1)
114 #define PCI_D2 ((pci_power_t __force) 2)
115 #define PCI_D3hot ((pci_power_t __force) 3)
116 #define PCI_D3cold ((pci_power_t __force) 4)
117 #define PCI_UNKNOWN ((pci_power_t __force) 5)
118 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
119
120 /* Remember to update this when the list above changes! */
121 extern const char *pci_power_names[];
122
pci_power_name(pci_power_t state)123 static inline const char *pci_power_name(pci_power_t state)
124 {
125 return pci_power_names[1 + (int) state];
126 }
127
128 #define PCI_PM_D2_DELAY 200
129 #define PCI_PM_D3_WAIT 10
130 #define PCI_PM_D3COLD_WAIT 100
131 #define PCI_PM_BUS_WAIT 50
132
133 /** The pci_channel state describes connectivity between the CPU and
134 * the pci device. If some PCI bus between here and the pci device
135 * has crashed or locked up, this info is reflected here.
136 */
137 typedef unsigned int __bitwise pci_channel_state_t;
138
139 enum pci_channel_state {
140 /* I/O channel is in normal state */
141 pci_channel_io_normal = (__force pci_channel_state_t) 1,
142
143 /* I/O to channel is blocked */
144 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
145
146 /* PCI card is dead */
147 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
148 };
149
150 typedef unsigned int __bitwise pcie_reset_state_t;
151
152 enum pcie_reset_state {
153 /* Reset is NOT asserted (Use to deassert reset) */
154 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
155
156 /* Use #PERST to reset PCIe device */
157 pcie_warm_reset = (__force pcie_reset_state_t) 2,
158
159 /* Use PCIe Hot Reset to reset device */
160 pcie_hot_reset = (__force pcie_reset_state_t) 3
161 };
162
163 typedef unsigned short __bitwise pci_dev_flags_t;
164 enum pci_dev_flags {
165 /* INTX_DISABLE in PCI_COMMAND register disables MSI
166 * generation too.
167 */
168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
169 /* Device configuration is irrevocably lost if disabled into D3 */
170 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
171 /* Provide indication device is assigned by a Virtual Machine Manager */
172 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
173 /* Flag for quirk use to store if quirk-specific ACS is enabled */
174 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
175 /* Flag to indicate the device uses dma_alias_devfn */
176 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4),
177 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
178 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
179 /* Do not use bus resets for device */
180 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
181 /* Do not use PM reset even if device advertises NoSoftRst- */
182 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
183 /* Get VPD from function 0 VPD */
184 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
185 };
186
187 enum pci_irq_reroute_variant {
188 INTEL_IRQ_REROUTE_VARIANT = 1,
189 MAX_IRQ_REROUTE_VARIANTS = 3
190 };
191
192 typedef unsigned short __bitwise pci_bus_flags_t;
193 enum pci_bus_flags {
194 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
195 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
196 };
197
198 /* These values come from the PCI Express Spec */
199 enum pcie_link_width {
200 PCIE_LNK_WIDTH_RESRV = 0x00,
201 PCIE_LNK_X1 = 0x01,
202 PCIE_LNK_X2 = 0x02,
203 PCIE_LNK_X4 = 0x04,
204 PCIE_LNK_X8 = 0x08,
205 PCIE_LNK_X12 = 0x0C,
206 PCIE_LNK_X16 = 0x10,
207 PCIE_LNK_X32 = 0x20,
208 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
209 };
210
211 /* Based on the PCI Hotplug Spec, but some values are made up by us */
212 enum pci_bus_speed {
213 PCI_SPEED_33MHz = 0x00,
214 PCI_SPEED_66MHz = 0x01,
215 PCI_SPEED_66MHz_PCIX = 0x02,
216 PCI_SPEED_100MHz_PCIX = 0x03,
217 PCI_SPEED_133MHz_PCIX = 0x04,
218 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
219 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
220 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
221 PCI_SPEED_66MHz_PCIX_266 = 0x09,
222 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
223 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
224 AGP_UNKNOWN = 0x0c,
225 AGP_1X = 0x0d,
226 AGP_2X = 0x0e,
227 AGP_4X = 0x0f,
228 AGP_8X = 0x10,
229 PCI_SPEED_66MHz_PCIX_533 = 0x11,
230 PCI_SPEED_100MHz_PCIX_533 = 0x12,
231 PCI_SPEED_133MHz_PCIX_533 = 0x13,
232 PCIE_SPEED_2_5GT = 0x14,
233 PCIE_SPEED_5_0GT = 0x15,
234 PCIE_SPEED_8_0GT = 0x16,
235 PCI_SPEED_UNKNOWN = 0xff,
236 };
237
238 struct pci_cap_saved_data {
239 u16 cap_nr;
240 bool cap_extended;
241 unsigned int size;
242 u32 data[0];
243 };
244
245 struct pci_cap_saved_state {
246 struct hlist_node next;
247 struct pci_cap_saved_data cap;
248 };
249
250 struct pcie_link_state;
251 struct pci_vpd;
252 struct pci_sriov;
253 struct pci_ats;
254
255 /*
256 * The pci_dev structure is used to describe PCI devices.
257 */
258 struct pci_dev {
259 struct list_head bus_list; /* node in per-bus list */
260 struct pci_bus *bus; /* bus this device is on */
261 struct pci_bus *subordinate; /* bus this device bridges to */
262
263 void *sysdata; /* hook for sys-specific extension */
264 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
265 struct pci_slot *slot; /* Physical slot this device is in */
266
267 unsigned int devfn; /* encoded device & function index */
268 unsigned short vendor;
269 unsigned short device;
270 unsigned short subsystem_vendor;
271 unsigned short subsystem_device;
272 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
273 u8 revision; /* PCI revision, low byte of class word */
274 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
275 u8 pcie_cap; /* PCIe capability offset */
276 u8 msi_cap; /* MSI capability offset */
277 u8 msix_cap; /* MSI-X capability offset */
278 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
279 u8 rom_base_reg; /* which config register controls the ROM */
280 u8 pin; /* which interrupt pin this device uses */
281 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
282 u8 dma_alias_devfn;/* devfn of DMA alias, if any */
283
284 struct pci_driver *driver; /* which driver has allocated this device */
285 u64 dma_mask; /* Mask of the bits of bus address this
286 device implements. Normally this is
287 0xffffffff. You only need to change
288 this if your device has broken DMA
289 or supports 64-bit transfers. */
290
291 struct device_dma_parameters dma_parms;
292
293 pci_power_t current_state; /* Current operating state. In ACPI-speak,
294 this is D0-D3, D0 being fully functional,
295 and D3 being off. */
296 u8 pm_cap; /* PM capability offset */
297 unsigned int pme_support:5; /* Bitmask of states from which PME#
298 can be generated */
299 unsigned int pme_interrupt:1;
300 unsigned int pme_poll:1; /* Poll device's PME status bit */
301 unsigned int d1_support:1; /* Low power state D1 is supported */
302 unsigned int d2_support:1; /* Low power state D2 is supported */
303 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
304 unsigned int no_d3cold:1; /* D3cold is forbidden */
305 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
306 unsigned int mmio_always_on:1; /* disallow turning off io/mem
307 decoding during bar sizing */
308 unsigned int wakeup_prepared:1;
309 unsigned int runtime_d3cold:1; /* whether go through runtime
310 D3cold, not set for devices
311 powered on/off by the
312 corresponding bridge */
313 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
314 unsigned int d3_delay; /* D3->D0 transition time in ms */
315 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
316
317 #ifdef CONFIG_PCIEASPM
318 struct pcie_link_state *link_state; /* ASPM link state */
319 #endif
320
321 pci_channel_state_t error_state; /* current connectivity state */
322 struct device dev; /* Generic device interface */
323
324 int cfg_size; /* Size of configuration space */
325
326 /*
327 * Instead of touching interrupt line and base address registers
328 * directly, use the values stored here. They might be different!
329 */
330 unsigned int irq;
331 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
332
333 bool match_driver; /* Skip attaching driver */
334 /* These fields are used by common fixups */
335 unsigned int transparent:1; /* Subtractive decode PCI bridge */
336 unsigned int multifunction:1;/* Part of multi-function device */
337 /* keep track of device state */
338 unsigned int is_added:1;
339 unsigned int is_busmaster:1; /* device is busmaster */
340 unsigned int no_msi:1; /* device may not use msi */
341 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
342 unsigned int block_cfg_access:1; /* config space access is blocked */
343 unsigned int broken_parity_status:1; /* Device generates false positive parity */
344 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
345 unsigned int msi_enabled:1;
346 unsigned int msix_enabled:1;
347 unsigned int ari_enabled:1; /* ARI forwarding */
348 unsigned int ats_enabled:1; /* Address Translation Service */
349 unsigned int is_managed:1;
350 unsigned int needs_freset:1; /* Dev requires fundamental reset */
351 unsigned int state_saved:1;
352 unsigned int is_physfn:1;
353 unsigned int is_virtfn:1;
354 unsigned int reset_fn:1;
355 unsigned int is_hotplug_bridge:1;
356 unsigned int __aer_firmware_first_valid:1;
357 unsigned int __aer_firmware_first:1;
358 unsigned int broken_intx_masking:1;
359 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
360 unsigned int irq_managed:1;
361 unsigned int has_secondary_link:1;
362 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
363 pci_dev_flags_t dev_flags;
364 atomic_t enable_cnt; /* pci_enable_device has been called */
365
366 u32 saved_config_space[16]; /* config space saved at suspend time */
367 struct hlist_head saved_cap_space;
368 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
369 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
370 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
371 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
372 #ifdef CONFIG_PCI_MSI
373 const struct attribute_group **msi_irq_groups;
374 #endif
375 struct pci_vpd *vpd;
376 #ifdef CONFIG_PCI_ATS
377 union {
378 struct pci_sriov *sriov; /* SR-IOV capability related */
379 struct pci_dev *physfn; /* the PF this VF is associated with */
380 };
381 u16 ats_cap; /* ATS Capability offset */
382 u8 ats_stu; /* ATS Smallest Translation Unit */
383 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
384 #endif
385 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
386 size_t romlen; /* Length of ROM if it's not from the BAR */
387 char *driver_override; /* Driver name to force a match */
388 };
389
pci_physfn(struct pci_dev * dev)390 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
391 {
392 #ifdef CONFIG_PCI_IOV
393 if (dev->is_virtfn)
394 dev = dev->physfn;
395 #endif
396 return dev;
397 }
398
399 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
400
401 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
402 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
403
pci_channel_offline(struct pci_dev * pdev)404 static inline int pci_channel_offline(struct pci_dev *pdev)
405 {
406 return (pdev->error_state != pci_channel_io_normal);
407 }
408
409 struct pci_host_bridge {
410 struct device dev;
411 struct pci_bus *bus; /* root bus */
412 struct list_head windows; /* resource_entry */
413 void (*release_fn)(struct pci_host_bridge *);
414 void *release_data;
415 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
416 /* Resource alignment requirements */
417 resource_size_t (*align_resource)(struct pci_dev *dev,
418 const struct resource *res,
419 resource_size_t start,
420 resource_size_t size,
421 resource_size_t align);
422 };
423
424 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
425
426 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
427
428 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
429 void (*release_fn)(struct pci_host_bridge *),
430 void *release_data);
431
432 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
433
434 /*
435 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
436 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
437 * buses below host bridges or subtractive decode bridges) go in the list.
438 * Use pci_bus_for_each_resource() to iterate through all the resources.
439 */
440
441 /*
442 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
443 * and there's no way to program the bridge with the details of the window.
444 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
445 * decode bit set, because they are explicit and can be programmed with _SRS.
446 */
447 #define PCI_SUBTRACTIVE_DECODE 0x1
448
449 struct pci_bus_resource {
450 struct list_head list;
451 struct resource *res;
452 unsigned int flags;
453 };
454
455 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
456
457 struct pci_bus {
458 struct list_head node; /* node in list of buses */
459 struct pci_bus *parent; /* parent bus this bridge is on */
460 struct list_head children; /* list of child buses */
461 struct list_head devices; /* list of devices on this bus */
462 struct pci_dev *self; /* bridge device as seen by parent */
463 struct list_head slots; /* list of slots on this bus;
464 protected by pci_slot_mutex */
465 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
466 struct list_head resources; /* address space routed to this bus */
467 struct resource busn_res; /* bus numbers routed to this bus */
468
469 struct pci_ops *ops; /* configuration access functions */
470 struct msi_controller *msi; /* MSI controller */
471 void *sysdata; /* hook for sys-specific extension */
472 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
473
474 unsigned char number; /* bus number */
475 unsigned char primary; /* number of primary bridge */
476 unsigned char max_bus_speed; /* enum pci_bus_speed */
477 unsigned char cur_bus_speed; /* enum pci_bus_speed */
478 #ifdef CONFIG_PCI_DOMAINS_GENERIC
479 int domain_nr;
480 #endif
481
482 char name[48];
483
484 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
485 pci_bus_flags_t bus_flags; /* inherited by child buses */
486 struct device *bridge;
487 struct device dev;
488 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
489 struct bin_attribute *legacy_mem; /* legacy mem */
490 unsigned int is_added:1;
491 };
492
493 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
494
495 /*
496 * Returns true if the PCI bus is root (behind host-PCI bridge),
497 * false otherwise
498 *
499 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
500 * This is incorrect because "virtual" buses added for SR-IOV (via
501 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
502 */
pci_is_root_bus(struct pci_bus * pbus)503 static inline bool pci_is_root_bus(struct pci_bus *pbus)
504 {
505 return !(pbus->parent);
506 }
507
508 /**
509 * pci_is_bridge - check if the PCI device is a bridge
510 * @dev: PCI device
511 *
512 * Return true if the PCI device is bridge whether it has subordinate
513 * or not.
514 */
pci_is_bridge(struct pci_dev * dev)515 static inline bool pci_is_bridge(struct pci_dev *dev)
516 {
517 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
518 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
519 }
520
pci_upstream_bridge(struct pci_dev * dev)521 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
522 {
523 dev = pci_physfn(dev);
524 if (pci_is_root_bus(dev->bus))
525 return NULL;
526
527 return dev->bus->self;
528 }
529
530 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
531 void pci_put_host_bridge_device(struct device *dev);
532
533 #ifdef CONFIG_PCI_MSI
pci_dev_msi_enabled(struct pci_dev * pci_dev)534 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
535 {
536 return pci_dev->msi_enabled || pci_dev->msix_enabled;
537 }
538 #else
pci_dev_msi_enabled(struct pci_dev * pci_dev)539 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
540 #endif
541
542 /*
543 * Error values that may be returned by PCI functions.
544 */
545 #define PCIBIOS_SUCCESSFUL 0x00
546 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
547 #define PCIBIOS_BAD_VENDOR_ID 0x83
548 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
549 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
550 #define PCIBIOS_SET_FAILED 0x88
551 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
552
553 /*
554 * Translate above to generic errno for passing back through non-PCI code.
555 */
pcibios_err_to_errno(int err)556 static inline int pcibios_err_to_errno(int err)
557 {
558 if (err <= PCIBIOS_SUCCESSFUL)
559 return err; /* Assume already errno */
560
561 switch (err) {
562 case PCIBIOS_FUNC_NOT_SUPPORTED:
563 return -ENOENT;
564 case PCIBIOS_BAD_VENDOR_ID:
565 return -ENOTTY;
566 case PCIBIOS_DEVICE_NOT_FOUND:
567 return -ENODEV;
568 case PCIBIOS_BAD_REGISTER_NUMBER:
569 return -EFAULT;
570 case PCIBIOS_SET_FAILED:
571 return -EIO;
572 case PCIBIOS_BUFFER_TOO_SMALL:
573 return -ENOSPC;
574 }
575
576 return -ERANGE;
577 }
578
579 /* Low-level architecture-dependent routines */
580
581 struct pci_ops {
582 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
583 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
584 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
585 };
586
587 /*
588 * ACPI needs to be able to access PCI config space before we've done a
589 * PCI bus scan and created pci_bus structures.
590 */
591 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
592 int reg, int len, u32 *val);
593 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
594 int reg, int len, u32 val);
595
596 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
597 typedef u64 pci_bus_addr_t;
598 #else
599 typedef u32 pci_bus_addr_t;
600 #endif
601
602 struct pci_bus_region {
603 pci_bus_addr_t start;
604 pci_bus_addr_t end;
605 };
606
607 struct pci_dynids {
608 spinlock_t lock; /* protects list, index */
609 struct list_head list; /* for IDs added at runtime */
610 };
611
612
613 /*
614 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
615 * a set of callbacks in struct pci_error_handlers, that device driver
616 * will be notified of PCI bus errors, and will be driven to recovery
617 * when an error occurs.
618 */
619
620 typedef unsigned int __bitwise pci_ers_result_t;
621
622 enum pci_ers_result {
623 /* no result/none/not supported in device driver */
624 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
625
626 /* Device driver can recover without slot reset */
627 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
628
629 /* Device driver wants slot to be reset. */
630 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
631
632 /* Device has completely failed, is unrecoverable */
633 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
634
635 /* Device driver is fully recovered and operational */
636 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
637
638 /* No AER capabilities registered for the driver */
639 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
640 };
641
642 /* PCI bus error event callbacks */
643 struct pci_error_handlers {
644 /* PCI bus error detected on this device */
645 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
646 enum pci_channel_state error);
647
648 /* MMIO has been re-enabled, but not DMA */
649 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
650
651 /* PCI Express link has been reset */
652 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
653
654 /* PCI slot has been reset */
655 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
656
657 /* PCI function reset prepare or completed */
658 void (*reset_notify)(struct pci_dev *dev, bool prepare);
659
660 /* Device driver may resume normal operations */
661 void (*resume)(struct pci_dev *dev);
662 };
663
664
665 struct module;
666 struct pci_driver {
667 struct list_head node;
668 const char *name;
669 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
670 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
671 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
672 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
673 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
674 int (*resume_early) (struct pci_dev *dev);
675 int (*resume) (struct pci_dev *dev); /* Device woken up */
676 void (*shutdown) (struct pci_dev *dev);
677 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
678 const struct pci_error_handlers *err_handler;
679 struct device_driver driver;
680 struct pci_dynids dynids;
681 };
682
683 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
684
685 /**
686 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
687 * @_table: device table name
688 *
689 * This macro is deprecated and should not be used in new code.
690 */
691 #define DEFINE_PCI_DEVICE_TABLE(_table) \
692 const struct pci_device_id _table[]
693
694 /**
695 * PCI_DEVICE - macro used to describe a specific pci device
696 * @vend: the 16 bit PCI Vendor ID
697 * @dev: the 16 bit PCI Device ID
698 *
699 * This macro is used to create a struct pci_device_id that matches a
700 * specific device. The subvendor and subdevice fields will be set to
701 * PCI_ANY_ID.
702 */
703 #define PCI_DEVICE(vend,dev) \
704 .vendor = (vend), .device = (dev), \
705 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
706
707 /**
708 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
709 * @vend: the 16 bit PCI Vendor ID
710 * @dev: the 16 bit PCI Device ID
711 * @subvend: the 16 bit PCI Subvendor ID
712 * @subdev: the 16 bit PCI Subdevice ID
713 *
714 * This macro is used to create a struct pci_device_id that matches a
715 * specific device with subsystem information.
716 */
717 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
718 .vendor = (vend), .device = (dev), \
719 .subvendor = (subvend), .subdevice = (subdev)
720
721 /**
722 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
723 * @dev_class: the class, subclass, prog-if triple for this device
724 * @dev_class_mask: the class mask for this device
725 *
726 * This macro is used to create a struct pci_device_id that matches a
727 * specific PCI class. The vendor, device, subvendor, and subdevice
728 * fields will be set to PCI_ANY_ID.
729 */
730 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
731 .class = (dev_class), .class_mask = (dev_class_mask), \
732 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
733 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
734
735 /**
736 * PCI_VDEVICE - macro used to describe a specific pci device in short form
737 * @vend: the vendor name
738 * @dev: the 16 bit PCI Device ID
739 *
740 * This macro is used to create a struct pci_device_id that matches a
741 * specific PCI device. The subvendor, and subdevice fields will be set
742 * to PCI_ANY_ID. The macro allows the next field to follow as the device
743 * private data.
744 */
745
746 #define PCI_VDEVICE(vend, dev) \
747 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
748 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
749
750 /* these external functions are only available when PCI support is enabled */
751 #ifdef CONFIG_PCI
752
753 void pcie_bus_configure_settings(struct pci_bus *bus);
754
755 enum pcie_bus_config_types {
756 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
757 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
758 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
759 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
760 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
761 };
762
763 extern enum pcie_bus_config_types pcie_bus_config;
764
765 extern struct bus_type pci_bus_type;
766
767 /* Do NOT directly access these two variables, unless you are arch-specific PCI
768 * code, or PCI core code. */
769 extern struct list_head pci_root_buses; /* list of all known PCI buses */
770 /* Some device drivers need know if PCI is initiated */
771 int no_pci_devices(void);
772
773 void pcibios_resource_survey_bus(struct pci_bus *bus);
774 void pcibios_add_bus(struct pci_bus *bus);
775 void pcibios_remove_bus(struct pci_bus *bus);
776 void pcibios_fixup_bus(struct pci_bus *);
777 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
778 /* Architecture-specific versions may override this (weak) */
779 char *pcibios_setup(char *str);
780
781 /* Used only when drivers/pci/setup.c is used */
782 resource_size_t pcibios_align_resource(void *, const struct resource *,
783 resource_size_t,
784 resource_size_t);
785 void pcibios_update_irq(struct pci_dev *, int irq);
786
787 /* Weak but can be overriden by arch */
788 void pci_fixup_cardbus(struct pci_bus *);
789
790 /* Generic PCI functions used internally */
791
792 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
793 struct resource *res);
794 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
795 struct pci_bus_region *region);
796 void pcibios_scan_specific_bus(int busn);
797 struct pci_bus *pci_find_bus(int domain, int busnr);
798 void pci_bus_add_devices(const struct pci_bus *bus);
799 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
800 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
801 struct pci_ops *ops, void *sysdata,
802 struct list_head *resources);
803 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
804 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
805 void pci_bus_release_busn_res(struct pci_bus *b);
806 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
807 struct pci_ops *ops, void *sysdata,
808 struct list_head *resources,
809 struct msi_controller *msi);
810 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
811 struct pci_ops *ops, void *sysdata,
812 struct list_head *resources);
813 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
814 int busnr);
815 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
816 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
817 const char *name,
818 struct hotplug_slot *hotplug);
819 void pci_destroy_slot(struct pci_slot *slot);
820 #ifdef CONFIG_SYSFS
821 void pci_dev_assign_slot(struct pci_dev *dev);
822 #else
pci_dev_assign_slot(struct pci_dev * dev)823 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
824 #endif
825 int pci_scan_slot(struct pci_bus *bus, int devfn);
826 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
827 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
828 unsigned int pci_scan_child_bus(struct pci_bus *bus);
829 void pci_bus_add_device(struct pci_dev *dev);
830 void pci_read_bridge_bases(struct pci_bus *child);
831 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
832 struct resource *res);
833 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
834 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
835 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
836 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
837 struct pci_dev *pci_dev_get(struct pci_dev *dev);
838 void pci_dev_put(struct pci_dev *dev);
839 void pci_remove_bus(struct pci_bus *b);
840 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
841 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
842 void pci_stop_root_bus(struct pci_bus *bus);
843 void pci_remove_root_bus(struct pci_bus *bus);
844 void pci_setup_cardbus(struct pci_bus *bus);
845 void pci_sort_breadthfirst(void);
846 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
847 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
848 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
849
850 /* Generic PCI functions exported to card drivers */
851
852 enum pci_lost_interrupt_reason {
853 PCI_LOST_IRQ_NO_INFORMATION = 0,
854 PCI_LOST_IRQ_DISABLE_MSI,
855 PCI_LOST_IRQ_DISABLE_MSIX,
856 PCI_LOST_IRQ_DISABLE_ACPI,
857 };
858 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
859 int pci_find_capability(struct pci_dev *dev, int cap);
860 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
861 int pci_find_ext_capability(struct pci_dev *dev, int cap);
862 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
863 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
864 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
865 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
866
867 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
868 struct pci_dev *from);
869 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
870 unsigned int ss_vendor, unsigned int ss_device,
871 struct pci_dev *from);
872 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
873 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
874 unsigned int devfn);
pci_get_bus_and_slot(unsigned int bus,unsigned int devfn)875 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
876 unsigned int devfn)
877 {
878 return pci_get_domain_bus_and_slot(0, bus, devfn);
879 }
880 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
881 int pci_dev_present(const struct pci_device_id *ids);
882
883 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
884 int where, u8 *val);
885 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
886 int where, u16 *val);
887 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
888 int where, u32 *val);
889 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
890 int where, u8 val);
891 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
892 int where, u16 val);
893 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
894 int where, u32 val);
895
896 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
897 int where, int size, u32 *val);
898 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
899 int where, int size, u32 val);
900 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
901 int where, int size, u32 *val);
902 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
903 int where, int size, u32 val);
904
905 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
906
pci_read_config_byte(const struct pci_dev * dev,int where,u8 * val)907 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
908 {
909 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
910 }
pci_read_config_word(const struct pci_dev * dev,int where,u16 * val)911 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
912 {
913 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
914 }
pci_read_config_dword(const struct pci_dev * dev,int where,u32 * val)915 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
916 u32 *val)
917 {
918 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
919 }
pci_write_config_byte(const struct pci_dev * dev,int where,u8 val)920 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
921 {
922 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
923 }
pci_write_config_word(const struct pci_dev * dev,int where,u16 val)924 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
925 {
926 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
927 }
pci_write_config_dword(const struct pci_dev * dev,int where,u32 val)928 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
929 u32 val)
930 {
931 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
932 }
933
934 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
935 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
936 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
937 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
938 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
939 u16 clear, u16 set);
940 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
941 u32 clear, u32 set);
942
pcie_capability_set_word(struct pci_dev * dev,int pos,u16 set)943 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
944 u16 set)
945 {
946 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
947 }
948
pcie_capability_set_dword(struct pci_dev * dev,int pos,u32 set)949 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
950 u32 set)
951 {
952 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
953 }
954
pcie_capability_clear_word(struct pci_dev * dev,int pos,u16 clear)955 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
956 u16 clear)
957 {
958 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
959 }
960
pcie_capability_clear_dword(struct pci_dev * dev,int pos,u32 clear)961 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
962 u32 clear)
963 {
964 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
965 }
966
967 /* user-space driven config access */
968 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
969 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
970 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
971 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
972 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
973 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
974
975 int __must_check pci_enable_device(struct pci_dev *dev);
976 int __must_check pci_enable_device_io(struct pci_dev *dev);
977 int __must_check pci_enable_device_mem(struct pci_dev *dev);
978 int __must_check pci_reenable_device(struct pci_dev *);
979 int __must_check pcim_enable_device(struct pci_dev *pdev);
980 void pcim_pin_device(struct pci_dev *pdev);
981
pci_is_enabled(struct pci_dev * pdev)982 static inline int pci_is_enabled(struct pci_dev *pdev)
983 {
984 return (atomic_read(&pdev->enable_cnt) > 0);
985 }
986
pci_is_managed(struct pci_dev * pdev)987 static inline int pci_is_managed(struct pci_dev *pdev)
988 {
989 return pdev->is_managed;
990 }
991
992 void pci_disable_device(struct pci_dev *dev);
993
994 extern unsigned int pcibios_max_latency;
995 void pci_set_master(struct pci_dev *dev);
996 void pci_clear_master(struct pci_dev *dev);
997
998 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
999 int pci_set_cacheline_size(struct pci_dev *dev);
1000 #define HAVE_PCI_SET_MWI
1001 int __must_check pci_set_mwi(struct pci_dev *dev);
1002 int pci_try_set_mwi(struct pci_dev *dev);
1003 void pci_clear_mwi(struct pci_dev *dev);
1004 void pci_intx(struct pci_dev *dev, int enable);
1005 bool pci_intx_mask_supported(struct pci_dev *dev);
1006 bool pci_check_and_mask_intx(struct pci_dev *dev);
1007 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1008 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
1009 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
1010 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1011 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1012 int pcix_get_max_mmrbc(struct pci_dev *dev);
1013 int pcix_get_mmrbc(struct pci_dev *dev);
1014 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1015 int pcie_get_readrq(struct pci_dev *dev);
1016 int pcie_set_readrq(struct pci_dev *dev, int rq);
1017 int pcie_get_mps(struct pci_dev *dev);
1018 int pcie_set_mps(struct pci_dev *dev, int mps);
1019 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1020 enum pcie_link_width *width);
1021 int __pci_reset_function(struct pci_dev *dev);
1022 int __pci_reset_function_locked(struct pci_dev *dev);
1023 int pci_reset_function(struct pci_dev *dev);
1024 int pci_try_reset_function(struct pci_dev *dev);
1025 int pci_probe_reset_slot(struct pci_slot *slot);
1026 int pci_reset_slot(struct pci_slot *slot);
1027 int pci_try_reset_slot(struct pci_slot *slot);
1028 int pci_probe_reset_bus(struct pci_bus *bus);
1029 int pci_reset_bus(struct pci_bus *bus);
1030 int pci_try_reset_bus(struct pci_bus *bus);
1031 void pci_reset_secondary_bus(struct pci_dev *dev);
1032 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1033 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1034 void pci_update_resource(struct pci_dev *dev, int resno);
1035 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1036 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1037 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1038 bool pci_device_is_present(struct pci_dev *pdev);
1039 void pci_ignore_hotplug(struct pci_dev *dev);
1040
1041 /* ROM control related routines */
1042 int pci_enable_rom(struct pci_dev *pdev);
1043 void pci_disable_rom(struct pci_dev *pdev);
1044 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1045 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1046 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1047 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1048
1049 /* Power management related routines */
1050 int pci_save_state(struct pci_dev *dev);
1051 void pci_restore_state(struct pci_dev *dev);
1052 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1053 int pci_load_saved_state(struct pci_dev *dev,
1054 struct pci_saved_state *state);
1055 int pci_load_and_free_saved_state(struct pci_dev *dev,
1056 struct pci_saved_state **state);
1057 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1058 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1059 u16 cap);
1060 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1061 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1062 u16 cap, unsigned int size);
1063 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1064 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1065 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1066 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1067 void pci_pme_active(struct pci_dev *dev, bool enable);
1068 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1069 bool runtime, bool enable);
1070 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1071 int pci_prepare_to_sleep(struct pci_dev *dev);
1072 int pci_back_from_sleep(struct pci_dev *dev);
1073 bool pci_dev_run_wake(struct pci_dev *dev);
1074 bool pci_check_pme_status(struct pci_dev *dev);
1075 void pci_pme_wakeup_bus(struct pci_bus *bus);
1076
pci_enable_wake(struct pci_dev * dev,pci_power_t state,bool enable)1077 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1078 bool enable)
1079 {
1080 return __pci_enable_wake(dev, state, false, enable);
1081 }
1082
1083 /* PCI Virtual Channel */
1084 int pci_save_vc_state(struct pci_dev *dev);
1085 void pci_restore_vc_state(struct pci_dev *dev);
1086 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1087
1088 /* For use by arch with custom probe code */
1089 void set_pcie_port_type(struct pci_dev *pdev);
1090 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1091
1092 /* Functions for PCI Hotplug drivers to use */
1093 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1094 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1095 unsigned int pci_rescan_bus(struct pci_bus *bus);
1096 void pci_lock_rescan_remove(void);
1097 void pci_unlock_rescan_remove(void);
1098
1099 /* Vital product data routines */
1100 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1101 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1102
1103 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1104 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1105 void pci_bus_assign_resources(const struct pci_bus *bus);
1106 void pci_bus_size_bridges(struct pci_bus *bus);
1107 int pci_claim_resource(struct pci_dev *, int);
1108 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1109 void pci_assign_unassigned_resources(void);
1110 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1111 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1112 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1113 void pdev_enable_device(struct pci_dev *);
1114 int pci_enable_resources(struct pci_dev *, int mask);
1115 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1116 int (*)(const struct pci_dev *, u8, u8));
1117 #define HAVE_PCI_REQ_REGIONS 2
1118 int __must_check pci_request_regions(struct pci_dev *, const char *);
1119 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1120 void pci_release_regions(struct pci_dev *);
1121 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1122 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1123 void pci_release_region(struct pci_dev *, int);
1124 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1125 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1126 void pci_release_selected_regions(struct pci_dev *, int);
1127
1128 /* drivers/pci/bus.c */
1129 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1130 void pci_bus_put(struct pci_bus *bus);
1131 void pci_add_resource(struct list_head *resources, struct resource *res);
1132 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1133 resource_size_t offset);
1134 void pci_free_resource_list(struct list_head *resources);
1135 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1136 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1137 void pci_bus_remove_resources(struct pci_bus *bus);
1138
1139 #define pci_bus_for_each_resource(bus, res, i) \
1140 for (i = 0; \
1141 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1142 i++)
1143
1144 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1145 struct resource *res, resource_size_t size,
1146 resource_size_t align, resource_size_t min,
1147 unsigned long type_mask,
1148 resource_size_t (*alignf)(void *,
1149 const struct resource *,
1150 resource_size_t,
1151 resource_size_t),
1152 void *alignf_data);
1153
1154
1155 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1156
pci_bus_address(struct pci_dev * pdev,int bar)1157 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1158 {
1159 struct pci_bus_region region;
1160
1161 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1162 return region.start;
1163 }
1164
1165 /* Proper probing supporting hot-pluggable devices */
1166 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1167 const char *mod_name);
1168
1169 /*
1170 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1171 */
1172 #define pci_register_driver(driver) \
1173 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1174
1175 void pci_unregister_driver(struct pci_driver *dev);
1176
1177 /**
1178 * module_pci_driver() - Helper macro for registering a PCI driver
1179 * @__pci_driver: pci_driver struct
1180 *
1181 * Helper macro for PCI drivers which do not do anything special in module
1182 * init/exit. This eliminates a lot of boilerplate. Each module may only
1183 * use this macro once, and calling it replaces module_init() and module_exit()
1184 */
1185 #define module_pci_driver(__pci_driver) \
1186 module_driver(__pci_driver, pci_register_driver, \
1187 pci_unregister_driver)
1188
1189 /**
1190 * builtin_pci_driver() - Helper macro for registering a PCI driver
1191 * @__pci_driver: pci_driver struct
1192 *
1193 * Helper macro for PCI drivers which do not do anything special in their
1194 * init code. This eliminates a lot of boilerplate. Each driver may only
1195 * use this macro once, and calling it replaces device_initcall(...)
1196 */
1197 #define builtin_pci_driver(__pci_driver) \
1198 builtin_driver(__pci_driver, pci_register_driver)
1199
1200 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1201 int pci_add_dynid(struct pci_driver *drv,
1202 unsigned int vendor, unsigned int device,
1203 unsigned int subvendor, unsigned int subdevice,
1204 unsigned int class, unsigned int class_mask,
1205 unsigned long driver_data);
1206 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1207 struct pci_dev *dev);
1208 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1209 int pass);
1210
1211 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1212 void *userdata);
1213 int pci_cfg_space_size(struct pci_dev *dev);
1214 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1215 void pci_setup_bridge(struct pci_bus *bus);
1216 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1217 unsigned long type);
1218 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1219
1220 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1221 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1222
1223 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1224 unsigned int command_bits, u32 flags);
1225 /* kmem_cache style wrapper around pci_alloc_consistent() */
1226
1227 #include <linux/pci-dma.h>
1228 #include <linux/dmapool.h>
1229
1230 #define pci_pool dma_pool
1231 #define pci_pool_create(name, pdev, size, align, allocation) \
1232 dma_pool_create(name, &pdev->dev, size, align, allocation)
1233 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1234 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1235 #define pci_pool_zalloc(pool, flags, handle) \
1236 dma_pool_zalloc(pool, flags, handle)
1237 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1238
1239 struct msix_entry {
1240 u32 vector; /* kernel uses to write allocated vector */
1241 u16 entry; /* driver uses to specify entry, OS writes */
1242 };
1243
1244 void pci_msi_setup_pci_dev(struct pci_dev *dev);
1245
1246 #ifdef CONFIG_PCI_MSI
1247 int pci_msi_vec_count(struct pci_dev *dev);
1248 void pci_msi_shutdown(struct pci_dev *dev);
1249 void pci_disable_msi(struct pci_dev *dev);
1250 int pci_msix_vec_count(struct pci_dev *dev);
1251 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1252 void pci_msix_shutdown(struct pci_dev *dev);
1253 void pci_disable_msix(struct pci_dev *dev);
1254 void pci_restore_msi_state(struct pci_dev *dev);
1255 int pci_msi_enabled(void);
1256 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
pci_enable_msi_exact(struct pci_dev * dev,int nvec)1257 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1258 {
1259 int rc = pci_enable_msi_range(dev, nvec, nvec);
1260 if (rc < 0)
1261 return rc;
1262 return 0;
1263 }
1264 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1265 int minvec, int maxvec);
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1266 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1267 struct msix_entry *entries, int nvec)
1268 {
1269 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1270 if (rc < 0)
1271 return rc;
1272 return 0;
1273 }
1274 #else
pci_msi_vec_count(struct pci_dev * dev)1275 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_msi_shutdown(struct pci_dev * dev)1276 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
pci_disable_msi(struct pci_dev * dev)1277 static inline void pci_disable_msi(struct pci_dev *dev) { }
pci_msix_vec_count(struct pci_dev * dev)1278 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_enable_msix(struct pci_dev * dev,struct msix_entry * entries,int nvec)1279 static inline int pci_enable_msix(struct pci_dev *dev,
1280 struct msix_entry *entries, int nvec)
1281 { return -ENOSYS; }
pci_msix_shutdown(struct pci_dev * dev)1282 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
pci_disable_msix(struct pci_dev * dev)1283 static inline void pci_disable_msix(struct pci_dev *dev) { }
pci_restore_msi_state(struct pci_dev * dev)1284 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
pci_msi_enabled(void)1285 static inline int pci_msi_enabled(void) { return 0; }
pci_enable_msi_range(struct pci_dev * dev,int minvec,int maxvec)1286 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1287 int maxvec)
1288 { return -ENOSYS; }
pci_enable_msi_exact(struct pci_dev * dev,int nvec)1289 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1290 { return -ENOSYS; }
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1291 static inline int pci_enable_msix_range(struct pci_dev *dev,
1292 struct msix_entry *entries, int minvec, int maxvec)
1293 { return -ENOSYS; }
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1294 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1295 struct msix_entry *entries, int nvec)
1296 { return -ENOSYS; }
1297 #endif
1298
1299 #ifdef CONFIG_PCIEPORTBUS
1300 extern bool pcie_ports_disabled;
1301 extern bool pcie_ports_auto;
1302 #else
1303 #define pcie_ports_disabled true
1304 #define pcie_ports_auto false
1305 #endif
1306
1307 #ifdef CONFIG_PCIEASPM
1308 bool pcie_aspm_support_enabled(void);
1309 #else
pcie_aspm_support_enabled(void)1310 static inline bool pcie_aspm_support_enabled(void) { return false; }
1311 #endif
1312
1313 #ifdef CONFIG_PCIEAER
1314 void pci_no_aer(void);
1315 bool pci_aer_available(void);
1316 #else
pci_no_aer(void)1317 static inline void pci_no_aer(void) { }
pci_aer_available(void)1318 static inline bool pci_aer_available(void) { return false; }
1319 #endif
1320
1321 #ifdef CONFIG_PCIE_ECRC
1322 void pcie_set_ecrc_checking(struct pci_dev *dev);
1323 void pcie_ecrc_get_policy(char *str);
1324 #else
pcie_set_ecrc_checking(struct pci_dev * dev)1325 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
pcie_ecrc_get_policy(char * str)1326 static inline void pcie_ecrc_get_policy(char *str) { }
1327 #endif
1328
1329 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1330
1331 #ifdef CONFIG_HT_IRQ
1332 /* The functions a driver should call */
1333 int ht_create_irq(struct pci_dev *dev, int idx);
1334 void ht_destroy_irq(unsigned int irq);
1335 #endif /* CONFIG_HT_IRQ */
1336
1337 #ifdef CONFIG_PCI_ATS
1338 /* Address Translation Service */
1339 void pci_ats_init(struct pci_dev *dev);
1340 int pci_enable_ats(struct pci_dev *dev, int ps);
1341 void pci_disable_ats(struct pci_dev *dev);
1342 int pci_ats_queue_depth(struct pci_dev *dev);
1343 #else
pci_ats_init(struct pci_dev * d)1344 static inline void pci_ats_init(struct pci_dev *d) { }
pci_enable_ats(struct pci_dev * d,int ps)1345 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
pci_disable_ats(struct pci_dev * d)1346 static inline void pci_disable_ats(struct pci_dev *d) { }
pci_ats_queue_depth(struct pci_dev * d)1347 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1348 #endif
1349
1350 void pci_cfg_access_lock(struct pci_dev *dev);
1351 bool pci_cfg_access_trylock(struct pci_dev *dev);
1352 void pci_cfg_access_unlock(struct pci_dev *dev);
1353
1354 /*
1355 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1356 * a PCI domain is defined to be a set of PCI buses which share
1357 * configuration space.
1358 */
1359 #ifdef CONFIG_PCI_DOMAINS
1360 extern int pci_domains_supported;
1361 int pci_get_new_domain_nr(void);
1362 #else
1363 enum { pci_domains_supported = 0 };
pci_domain_nr(struct pci_bus * bus)1364 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_proc_domain(struct pci_bus * bus)1365 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
pci_get_new_domain_nr(void)1366 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1367 #endif /* CONFIG_PCI_DOMAINS */
1368
1369 /*
1370 * Generic implementation for PCI domain support. If your
1371 * architecture does not need custom management of PCI
1372 * domains then this implementation will be used
1373 */
1374 #ifdef CONFIG_PCI_DOMAINS_GENERIC
pci_domain_nr(struct pci_bus * bus)1375 static inline int pci_domain_nr(struct pci_bus *bus)
1376 {
1377 return bus->domain_nr;
1378 }
1379 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent);
1380 #else
pci_bus_assign_domain_nr(struct pci_bus * bus,struct device * parent)1381 static inline void pci_bus_assign_domain_nr(struct pci_bus *bus,
1382 struct device *parent)
1383 {
1384 }
1385 #endif
1386
1387 /* some architectures require additional setup to direct VGA traffic */
1388 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1389 unsigned int command_bits, u32 flags);
1390 void pci_register_set_vga_state(arch_set_vga_state_t func);
1391
1392 #else /* CONFIG_PCI is not enabled */
1393
1394 /*
1395 * If the system does not have PCI, clearly these return errors. Define
1396 * these as simple inline functions to avoid hair in drivers.
1397 */
1398
1399 #define _PCI_NOP(o, s, t) \
1400 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1401 int where, t val) \
1402 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1403
1404 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1405 _PCI_NOP(o, word, u16 x) \
1406 _PCI_NOP(o, dword, u32 x)
1407 _PCI_NOP_ALL(read, *)
1408 _PCI_NOP_ALL(write,)
1409
pci_get_device(unsigned int vendor,unsigned int device,struct pci_dev * from)1410 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1411 unsigned int device,
1412 struct pci_dev *from)
1413 { return NULL; }
1414
pci_get_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,struct pci_dev * from)1415 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1416 unsigned int device,
1417 unsigned int ss_vendor,
1418 unsigned int ss_device,
1419 struct pci_dev *from)
1420 { return NULL; }
1421
pci_get_class(unsigned int class,struct pci_dev * from)1422 static inline struct pci_dev *pci_get_class(unsigned int class,
1423 struct pci_dev *from)
1424 { return NULL; }
1425
1426 #define pci_dev_present(ids) (0)
1427 #define no_pci_devices() (1)
1428 #define pci_dev_put(dev) do { } while (0)
1429
pci_set_master(struct pci_dev * dev)1430 static inline void pci_set_master(struct pci_dev *dev) { }
pci_enable_device(struct pci_dev * dev)1431 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)1432 static inline void pci_disable_device(struct pci_dev *dev) { }
pci_set_dma_mask(struct pci_dev * dev,u64 mask)1433 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1434 { return -EIO; }
pci_set_consistent_dma_mask(struct pci_dev * dev,u64 mask)1435 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1436 { return -EIO; }
pci_set_dma_max_seg_size(struct pci_dev * dev,unsigned int size)1437 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1438 unsigned int size)
1439 { return -EIO; }
pci_set_dma_seg_boundary(struct pci_dev * dev,unsigned long mask)1440 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1441 unsigned long mask)
1442 { return -EIO; }
pci_assign_resource(struct pci_dev * dev,int i)1443 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1444 { return -EBUSY; }
__pci_register_driver(struct pci_driver * drv,struct module * owner)1445 static inline int __pci_register_driver(struct pci_driver *drv,
1446 struct module *owner)
1447 { return 0; }
pci_register_driver(struct pci_driver * drv)1448 static inline int pci_register_driver(struct pci_driver *drv)
1449 { return 0; }
pci_unregister_driver(struct pci_driver * drv)1450 static inline void pci_unregister_driver(struct pci_driver *drv) { }
pci_find_capability(struct pci_dev * dev,int cap)1451 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1452 { return 0; }
pci_find_next_capability(struct pci_dev * dev,u8 post,int cap)1453 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1454 int cap)
1455 { return 0; }
pci_find_ext_capability(struct pci_dev * dev,int cap)1456 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1457 { return 0; }
1458
1459 /* Power management related routines */
pci_save_state(struct pci_dev * dev)1460 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
pci_restore_state(struct pci_dev * dev)1461 static inline void pci_restore_state(struct pci_dev *dev) { }
pci_set_power_state(struct pci_dev * dev,pci_power_t state)1462 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1463 { return 0; }
pci_wake_from_d3(struct pci_dev * dev,bool enable)1464 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1465 { return 0; }
pci_choose_state(struct pci_dev * dev,pm_message_t state)1466 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1467 pm_message_t state)
1468 { return PCI_D0; }
pci_enable_wake(struct pci_dev * dev,pci_power_t state,int enable)1469 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1470 int enable)
1471 { return 0; }
1472
pci_request_regions(struct pci_dev * dev,const char * res_name)1473 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1474 { return -EIO; }
pci_release_regions(struct pci_dev * dev)1475 static inline void pci_release_regions(struct pci_dev *dev) { }
1476
pci_block_cfg_access(struct pci_dev * dev)1477 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
pci_block_cfg_access_in_atomic(struct pci_dev * dev)1478 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1479 { return 0; }
pci_unblock_cfg_access(struct pci_dev * dev)1480 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1481
pci_find_next_bus(const struct pci_bus * from)1482 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1483 { return NULL; }
pci_get_slot(struct pci_bus * bus,unsigned int devfn)1484 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1485 unsigned int devfn)
1486 { return NULL; }
pci_get_bus_and_slot(unsigned int bus,unsigned int devfn)1487 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1488 unsigned int devfn)
1489 { return NULL; }
1490
pci_domain_nr(struct pci_bus * bus)1491 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_dev_get(struct pci_dev * dev)1492 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
pci_get_new_domain_nr(void)1493 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1494
1495 #define dev_is_pci(d) (false)
1496 #define dev_is_pf(d) (false)
1497 #define dev_num_vf(d) (0)
1498 #endif /* CONFIG_PCI */
1499
1500 /* Include architecture-dependent settings and functions */
1501
1502 #include <asm/pci.h>
1503
1504 /* these helpers provide future and backwards compatibility
1505 * for accessing popular PCI BAR info */
1506 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1507 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1508 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1509 #define pci_resource_len(dev,bar) \
1510 ((pci_resource_start((dev), (bar)) == 0 && \
1511 pci_resource_end((dev), (bar)) == \
1512 pci_resource_start((dev), (bar))) ? 0 : \
1513 \
1514 (pci_resource_end((dev), (bar)) - \
1515 pci_resource_start((dev), (bar)) + 1))
1516
1517 /* Similar to the helpers above, these manipulate per-pci_dev
1518 * driver-specific data. They are really just a wrapper around
1519 * the generic device structure functions of these calls.
1520 */
pci_get_drvdata(struct pci_dev * pdev)1521 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1522 {
1523 return dev_get_drvdata(&pdev->dev);
1524 }
1525
pci_set_drvdata(struct pci_dev * pdev,void * data)1526 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1527 {
1528 dev_set_drvdata(&pdev->dev, data);
1529 }
1530
1531 /* If you want to know what to call your pci_dev, ask this function.
1532 * Again, it's a wrapper around the generic device.
1533 */
pci_name(const struct pci_dev * pdev)1534 static inline const char *pci_name(const struct pci_dev *pdev)
1535 {
1536 return dev_name(&pdev->dev);
1537 }
1538
1539
1540 /* Some archs don't want to expose struct resource to userland as-is
1541 * in sysfs and /proc
1542 */
1543 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
pci_resource_to_user(const struct pci_dev * dev,int bar,const struct resource * rsrc,resource_size_t * start,resource_size_t * end)1544 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1545 const struct resource *rsrc, resource_size_t *start,
1546 resource_size_t *end)
1547 {
1548 *start = rsrc->start;
1549 *end = rsrc->end;
1550 }
1551 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1552
1553
1554 /*
1555 * The world is not perfect and supplies us with broken PCI devices.
1556 * For at least a part of these bugs we need a work-around, so both
1557 * generic (drivers/pci/quirks.c) and per-architecture code can define
1558 * fixup hooks to be called for particular buggy devices.
1559 */
1560
1561 struct pci_fixup {
1562 u16 vendor; /* You can use PCI_ANY_ID here of course */
1563 u16 device; /* You can use PCI_ANY_ID here of course */
1564 u32 class; /* You can use PCI_ANY_ID here too */
1565 unsigned int class_shift; /* should be 0, 8, 16 */
1566 void (*hook)(struct pci_dev *dev);
1567 };
1568
1569 enum pci_fixup_pass {
1570 pci_fixup_early, /* Before probing BARs */
1571 pci_fixup_header, /* After reading configuration header */
1572 pci_fixup_final, /* Final phase of device fixups */
1573 pci_fixup_enable, /* pci_enable_device() time */
1574 pci_fixup_resume, /* pci_device_resume() */
1575 pci_fixup_suspend, /* pci_device_suspend() */
1576 pci_fixup_resume_early, /* pci_device_resume_early() */
1577 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1578 };
1579
1580 /* Anonymous variables would be nice... */
1581 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1582 class_shift, hook) \
1583 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1584 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1585 = { vendor, device, class, class_shift, hook };
1586
1587 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1588 class_shift, hook) \
1589 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1590 hook, vendor, device, class, class_shift, hook)
1591 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1592 class_shift, hook) \
1593 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1594 hook, vendor, device, class, class_shift, hook)
1595 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1596 class_shift, hook) \
1597 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1598 hook, vendor, device, class, class_shift, hook)
1599 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1600 class_shift, hook) \
1601 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1602 hook, vendor, device, class, class_shift, hook)
1603 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1604 class_shift, hook) \
1605 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1606 resume##hook, vendor, device, class, \
1607 class_shift, hook)
1608 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1609 class_shift, hook) \
1610 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1611 resume_early##hook, vendor, device, \
1612 class, class_shift, hook)
1613 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1614 class_shift, hook) \
1615 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1616 suspend##hook, vendor, device, class, \
1617 class_shift, hook)
1618 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1619 class_shift, hook) \
1620 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1621 suspend_late##hook, vendor, device, \
1622 class, class_shift, hook)
1623
1624 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1625 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1626 hook, vendor, device, PCI_ANY_ID, 0, hook)
1627 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1628 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1629 hook, vendor, device, PCI_ANY_ID, 0, hook)
1630 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1631 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1632 hook, vendor, device, PCI_ANY_ID, 0, hook)
1633 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1634 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1635 hook, vendor, device, PCI_ANY_ID, 0, hook)
1636 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1637 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1638 resume##hook, vendor, device, \
1639 PCI_ANY_ID, 0, hook)
1640 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1641 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1642 resume_early##hook, vendor, device, \
1643 PCI_ANY_ID, 0, hook)
1644 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1645 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1646 suspend##hook, vendor, device, \
1647 PCI_ANY_ID, 0, hook)
1648 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1649 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1650 suspend_late##hook, vendor, device, \
1651 PCI_ANY_ID, 0, hook)
1652
1653 #ifdef CONFIG_PCI_QUIRKS
1654 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1655 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1656 void pci_dev_specific_enable_acs(struct pci_dev *dev);
1657 #else
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)1658 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1659 struct pci_dev *dev) { }
pci_dev_specific_acs_enabled(struct pci_dev * dev,u16 acs_flags)1660 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1661 u16 acs_flags)
1662 {
1663 return -ENOTTY;
1664 }
pci_dev_specific_enable_acs(struct pci_dev * dev)1665 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { }
1666 #endif
1667
1668 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1669 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1670 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1671 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1672 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1673 const char *name);
1674 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1675
1676 extern int pci_pci_problems;
1677 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1678 #define PCIPCI_TRITON 2
1679 #define PCIPCI_NATOMA 4
1680 #define PCIPCI_VIAETBF 8
1681 #define PCIPCI_VSFX 16
1682 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1683 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1684
1685 extern unsigned long pci_cardbus_io_size;
1686 extern unsigned long pci_cardbus_mem_size;
1687 extern u8 pci_dfl_cache_line_size;
1688 extern u8 pci_cache_line_size;
1689
1690 extern unsigned long pci_hotplug_io_size;
1691 extern unsigned long pci_hotplug_mem_size;
1692
1693 /* Architecture-specific versions may override these (weak) */
1694 void pcibios_disable_device(struct pci_dev *dev);
1695 void pcibios_set_master(struct pci_dev *dev);
1696 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1697 enum pcie_reset_state state);
1698 int pcibios_add_device(struct pci_dev *dev);
1699 void pcibios_release_device(struct pci_dev *dev);
1700 void pcibios_penalize_isa_irq(int irq, int active);
1701 int pcibios_alloc_irq(struct pci_dev *dev);
1702 void pcibios_free_irq(struct pci_dev *dev);
1703
1704 #ifdef CONFIG_HIBERNATE_CALLBACKS
1705 extern struct dev_pm_ops pcibios_pm_ops;
1706 #endif
1707
1708 #ifdef CONFIG_PCI_MMCONFIG
1709 void __init pci_mmcfg_early_init(void);
1710 void __init pci_mmcfg_late_init(void);
1711 #else
pci_mmcfg_early_init(void)1712 static inline void pci_mmcfg_early_init(void) { }
pci_mmcfg_late_init(void)1713 static inline void pci_mmcfg_late_init(void) { }
1714 #endif
1715
1716 int pci_ext_cfg_avail(void);
1717
1718 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1719 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1720
1721 #ifdef CONFIG_PCI_IOV
1722 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1723 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1724
1725 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1726 void pci_disable_sriov(struct pci_dev *dev);
1727 int pci_num_vf(struct pci_dev *dev);
1728 int pci_vfs_assigned(struct pci_dev *dev);
1729 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1730 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1731 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1732 #else
pci_iov_virtfn_bus(struct pci_dev * dev,int id)1733 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1734 {
1735 return -ENOSYS;
1736 }
pci_iov_virtfn_devfn(struct pci_dev * dev,int id)1737 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1738 {
1739 return -ENOSYS;
1740 }
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)1741 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1742 { return -ENODEV; }
pci_disable_sriov(struct pci_dev * dev)1743 static inline void pci_disable_sriov(struct pci_dev *dev) { }
pci_num_vf(struct pci_dev * dev)1744 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
pci_vfs_assigned(struct pci_dev * dev)1745 static inline int pci_vfs_assigned(struct pci_dev *dev)
1746 { return 0; }
pci_sriov_set_totalvfs(struct pci_dev * dev,u16 numvfs)1747 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1748 { return 0; }
pci_sriov_get_totalvfs(struct pci_dev * dev)1749 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1750 { return 0; }
pci_iov_resource_size(struct pci_dev * dev,int resno)1751 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1752 { return 0; }
1753 #endif
1754
1755 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1756 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1757 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1758 #endif
1759
1760 /**
1761 * pci_pcie_cap - get the saved PCIe capability offset
1762 * @dev: PCI device
1763 *
1764 * PCIe capability offset is calculated at PCI device initialization
1765 * time and saved in the data structure. This function returns saved
1766 * PCIe capability offset. Using this instead of pci_find_capability()
1767 * reduces unnecessary search in the PCI configuration space. If you
1768 * need to calculate PCIe capability offset from raw device for some
1769 * reasons, please use pci_find_capability() instead.
1770 */
pci_pcie_cap(struct pci_dev * dev)1771 static inline int pci_pcie_cap(struct pci_dev *dev)
1772 {
1773 return dev->pcie_cap;
1774 }
1775
1776 /**
1777 * pci_is_pcie - check if the PCI device is PCI Express capable
1778 * @dev: PCI device
1779 *
1780 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1781 */
pci_is_pcie(struct pci_dev * dev)1782 static inline bool pci_is_pcie(struct pci_dev *dev)
1783 {
1784 return pci_pcie_cap(dev);
1785 }
1786
1787 /**
1788 * pcie_caps_reg - get the PCIe Capabilities Register
1789 * @dev: PCI device
1790 */
pcie_caps_reg(const struct pci_dev * dev)1791 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1792 {
1793 return dev->pcie_flags_reg;
1794 }
1795
1796 /**
1797 * pci_pcie_type - get the PCIe device/port type
1798 * @dev: PCI device
1799 */
pci_pcie_type(const struct pci_dev * dev)1800 static inline int pci_pcie_type(const struct pci_dev *dev)
1801 {
1802 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1803 }
1804
1805 void pci_request_acs(void);
1806 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1807 bool pci_acs_path_enabled(struct pci_dev *start,
1808 struct pci_dev *end, u16 acs_flags);
1809
1810 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1811 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1812
1813 /* Large Resource Data Type Tag Item Names */
1814 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1815 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1816 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1817
1818 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1819 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1820 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1821
1822 /* Small Resource Data Type Tag Item Names */
1823 #define PCI_VPD_STIN_END 0x78 /* End */
1824
1825 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1826
1827 #define PCI_VPD_SRDT_TIN_MASK 0x78
1828 #define PCI_VPD_SRDT_LEN_MASK 0x07
1829
1830 #define PCI_VPD_LRDT_TAG_SIZE 3
1831 #define PCI_VPD_SRDT_TAG_SIZE 1
1832
1833 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1834
1835 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1836 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1837 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1838 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1839
1840 /**
1841 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1842 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1843 *
1844 * Returns the extracted Large Resource Data Type length.
1845 */
pci_vpd_lrdt_size(const u8 * lrdt)1846 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1847 {
1848 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1849 }
1850
1851 /**
1852 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1853 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1854 *
1855 * Returns the extracted Small Resource Data Type length.
1856 */
pci_vpd_srdt_size(const u8 * srdt)1857 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1858 {
1859 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1860 }
1861
1862 /**
1863 * pci_vpd_info_field_size - Extracts the information field length
1864 * @lrdt: Pointer to the beginning of an information field header
1865 *
1866 * Returns the extracted information field length.
1867 */
pci_vpd_info_field_size(const u8 * info_field)1868 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1869 {
1870 return info_field[2];
1871 }
1872
1873 /**
1874 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1875 * @buf: Pointer to buffered vpd data
1876 * @off: The offset into the buffer at which to begin the search
1877 * @len: The length of the vpd buffer
1878 * @rdt: The Resource Data Type to search for
1879 *
1880 * Returns the index where the Resource Data Type was found or
1881 * -ENOENT otherwise.
1882 */
1883 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1884
1885 /**
1886 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1887 * @buf: Pointer to buffered vpd data
1888 * @off: The offset into the buffer at which to begin the search
1889 * @len: The length of the buffer area, relative to off, in which to search
1890 * @kw: The keyword to search for
1891 *
1892 * Returns the index where the information field keyword was found or
1893 * -ENOENT otherwise.
1894 */
1895 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1896 unsigned int len, const char *kw);
1897
1898 /* PCI <-> OF binding helpers */
1899 #ifdef CONFIG_OF
1900 struct device_node;
1901 struct irq_domain;
1902 void pci_set_of_node(struct pci_dev *dev);
1903 void pci_release_of_node(struct pci_dev *dev);
1904 void pci_set_bus_of_node(struct pci_bus *bus);
1905 void pci_release_bus_of_node(struct pci_bus *bus);
1906 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
1907
1908 /* Arch may override this (weak) */
1909 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1910
1911 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)1912 pci_device_to_OF_node(const struct pci_dev *pdev)
1913 {
1914 return pdev ? pdev->dev.of_node : NULL;
1915 }
1916
pci_bus_to_OF_node(struct pci_bus * bus)1917 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1918 {
1919 return bus ? bus->dev.of_node : NULL;
1920 }
1921
1922 #else /* CONFIG_OF */
pci_set_of_node(struct pci_dev * dev)1923 static inline void pci_set_of_node(struct pci_dev *dev) { }
pci_release_of_node(struct pci_dev * dev)1924 static inline void pci_release_of_node(struct pci_dev *dev) { }
pci_set_bus_of_node(struct pci_bus * bus)1925 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
pci_release_bus_of_node(struct pci_bus * bus)1926 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1927 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)1928 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
1929 static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus * bus)1930 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
1931 #endif /* CONFIG_OF */
1932
1933 #ifdef CONFIG_EEH
pci_dev_to_eeh_dev(struct pci_dev * pdev)1934 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1935 {
1936 return pdev->dev.archdata.edev;
1937 }
1938 #endif
1939
1940 int pci_for_each_dma_alias(struct pci_dev *pdev,
1941 int (*fn)(struct pci_dev *pdev,
1942 u16 alias, void *data), void *data);
1943
1944 /* helper functions for operation of device flag */
pci_set_dev_assigned(struct pci_dev * pdev)1945 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
1946 {
1947 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
1948 }
pci_clear_dev_assigned(struct pci_dev * pdev)1949 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
1950 {
1951 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
1952 }
pci_is_dev_assigned(struct pci_dev * pdev)1953 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
1954 {
1955 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
1956 }
1957
1958 /**
1959 * pci_ari_enabled - query ARI forwarding status
1960 * @bus: the PCI bus
1961 *
1962 * Returns true if ARI forwarding is enabled.
1963 */
pci_ari_enabled(struct pci_bus * bus)1964 static inline bool pci_ari_enabled(struct pci_bus *bus)
1965 {
1966 return bus->self && bus->self->ari_enabled;
1967 }
1968 #endif /* LINUX_PCI_H */
1969