1 /*
2 * Atmel SMC (Static Memory Controller) register offsets and bit definitions.
3 *
4 * Copyright (C) 2014 Atmel
5 * Copyright (C) 2014 Free Electrons
6 *
7 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #ifndef _LINUX_MFD_SYSCON_ATMEL_SMC_H_
15 #define _LINUX_MFD_SYSCON_ATMEL_SMC_H_
16
17 #include <linux/kernel.h>
18 #include <linux/regmap.h>
19
20 #define AT91SAM9_SMC_GENERIC 0x00
21 #define AT91SAM9_SMC_GENERIC_BLK_SZ 0x10
22
23 #define SAMA5_SMC_GENERIC 0x600
24 #define SAMA5_SMC_GENERIC_BLK_SZ 0x14
25
26 #define AT91SAM9_SMC_SETUP(o) ((o) + 0x00)
27 #define AT91SAM9_SMC_NWESETUP(x) (x)
28 #define AT91SAM9_SMC_NCS_WRSETUP(x) ((x) << 8)
29 #define AT91SAM9_SMC_NRDSETUP(x) ((x) << 16)
30 #define AT91SAM9_SMC_NCS_NRDSETUP(x) ((x) << 24)
31
32 #define AT91SAM9_SMC_PULSE(o) ((o) + 0x04)
33 #define AT91SAM9_SMC_NWEPULSE(x) (x)
34 #define AT91SAM9_SMC_NCS_WRPULSE(x) ((x) << 8)
35 #define AT91SAM9_SMC_NRDPULSE(x) ((x) << 16)
36 #define AT91SAM9_SMC_NCS_NRDPULSE(x) ((x) << 24)
37
38 #define AT91SAM9_SMC_CYCLE(o) ((o) + 0x08)
39 #define AT91SAM9_SMC_NWECYCLE(x) (x)
40 #define AT91SAM9_SMC_NRDCYCLE(x) ((x) << 16)
41
42 #define AT91SAM9_SMC_MODE(o) ((o) + 0x0c)
43 #define SAMA5_SMC_MODE(o) ((o) + 0x10)
44 #define AT91_SMC_READMODE BIT(0)
45 #define AT91_SMC_READMODE_NCS (0 << 0)
46 #define AT91_SMC_READMODE_NRD (1 << 0)
47 #define AT91_SMC_WRITEMODE BIT(1)
48 #define AT91_SMC_WRITEMODE_NCS (0 << 1)
49 #define AT91_SMC_WRITEMODE_NWE (1 << 1)
50 #define AT91_SMC_EXNWMODE GENMASK(5, 4)
51 #define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
52 #define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
53 #define AT91_SMC_EXNWMODE_READY (3 << 4)
54 #define AT91_SMC_BAT BIT(8)
55 #define AT91_SMC_BAT_SELECT (0 << 8)
56 #define AT91_SMC_BAT_WRITE (1 << 8)
57 #define AT91_SMC_DBW GENMASK(13, 12)
58 #define AT91_SMC_DBW_8 (0 << 12)
59 #define AT91_SMC_DBW_16 (1 << 12)
60 #define AT91_SMC_DBW_32 (2 << 12)
61 #define AT91_SMC_TDF GENMASK(19, 16)
62 #define AT91_SMC_TDF_(x) ((((x) - 1) << 16) & AT91_SMC_TDF)
63 #define AT91_SMC_TDF_MAX 16
64 #define AT91_SMC_TDFMODE_OPTIMIZED BIT(20)
65 #define AT91_SMC_PMEN BIT(24)
66 #define AT91_SMC_PS GENMASK(29, 28)
67 #define AT91_SMC_PS_4 (0 << 28)
68 #define AT91_SMC_PS_8 (1 << 28)
69 #define AT91_SMC_PS_16 (2 << 28)
70 #define AT91_SMC_PS_32 (3 << 28)
71
72
73 /*
74 * This function converts a setup timing expressed in nanoseconds into an
75 * encoded value that can be written in the SMC_SETUP register.
76 *
77 * The following formula is described in atmel datasheets (section
78 * "SMC Setup Register"):
79 *
80 * setup length = (128* SETUP[5] + SETUP[4:0])
81 *
82 * where setup length is the timing expressed in cycles.
83 */
at91sam9_smc_setup_ns_to_cycles(unsigned int clk_rate,u32 timing_ns)84 static inline u32 at91sam9_smc_setup_ns_to_cycles(unsigned int clk_rate,
85 u32 timing_ns)
86 {
87 u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate);
88 u32 coded_cycles = 0;
89 u32 cycles;
90
91 cycles = DIV_ROUND_UP(timing_ns, clk_period);
92 if (cycles / 32) {
93 coded_cycles |= 1 << 5;
94 if (cycles < 128)
95 cycles = 0;
96 }
97
98 coded_cycles |= cycles % 32;
99
100 return coded_cycles;
101 }
102
103 /*
104 * This function converts a pulse timing expressed in nanoseconds into an
105 * encoded value that can be written in the SMC_PULSE register.
106 *
107 * The following formula is described in atmel datasheets (section
108 * "SMC Pulse Register"):
109 *
110 * pulse length = (256* PULSE[6] + PULSE[5:0])
111 *
112 * where pulse length is the timing expressed in cycles.
113 */
at91sam9_smc_pulse_ns_to_cycles(unsigned int clk_rate,u32 timing_ns)114 static inline u32 at91sam9_smc_pulse_ns_to_cycles(unsigned int clk_rate,
115 u32 timing_ns)
116 {
117 u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate);
118 u32 coded_cycles = 0;
119 u32 cycles;
120
121 cycles = DIV_ROUND_UP(timing_ns, clk_period);
122 if (cycles / 64) {
123 coded_cycles |= 1 << 6;
124 if (cycles < 256)
125 cycles = 0;
126 }
127
128 coded_cycles |= cycles % 64;
129
130 return coded_cycles;
131 }
132
133 /*
134 * This function converts a cycle timing expressed in nanoseconds into an
135 * encoded value that can be written in the SMC_CYCLE register.
136 *
137 * The following formula is described in atmel datasheets (section
138 * "SMC Cycle Register"):
139 *
140 * cycle length = (CYCLE[8:7]*256 + CYCLE[6:0])
141 *
142 * where cycle length is the timing expressed in cycles.
143 */
at91sam9_smc_cycle_ns_to_cycles(unsigned int clk_rate,u32 timing_ns)144 static inline u32 at91sam9_smc_cycle_ns_to_cycles(unsigned int clk_rate,
145 u32 timing_ns)
146 {
147 u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate);
148 u32 coded_cycles = 0;
149 u32 cycles;
150
151 cycles = DIV_ROUND_UP(timing_ns, clk_period);
152 if (cycles / 128) {
153 coded_cycles = cycles / 256;
154 cycles %= 256;
155 if (cycles >= 128) {
156 coded_cycles++;
157 cycles = 0;
158 }
159
160 if (coded_cycles > 0x3) {
161 coded_cycles = 0x3;
162 cycles = 0x7f;
163 }
164
165 coded_cycles <<= 7;
166 }
167
168 coded_cycles |= cycles % 128;
169
170 return coded_cycles;
171 }
172
173 #endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */
174