1/*
2 * Copyright (C) 2005 Ivan Kokshaysky
3 * Copyright (C) SAN People
4 *
5 * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals
6 * registers.
7 * Based on AT91RM9200 datasheet revision E.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef _LINUX_MFD_SYSCON_ATMEL_MC_H_
16#define _LINUX_MFD_SYSCON_ATMEL_MC_H_
17
18/* Memory Controller */
19#define AT91_MC_RCR			0x00
20#define AT91_MC_RCB			BIT(0)
21
22#define AT91_MC_ASR			0x04
23#define AT91_MC_UNADD			BIT(0)
24#define AT91_MC_MISADD			BIT(1)
25#define AT91_MC_ABTSZ			GENMASK(9, 8)
26#define AT91_MC_ABTSZ_BYTE		(0 << 8)
27#define AT91_MC_ABTSZ_HALFWORD		(1 << 8)
28#define AT91_MC_ABTSZ_WORD		(2 << 8)
29#define AT91_MC_ABTTYP			GENMASK(11, 10)
30#define AT91_MC_ABTTYP_DATAREAD		(0 << 10)
31#define AT91_MC_ABTTYP_DATAWRITE	(1 << 10)
32#define AT91_MC_ABTTYP_FETCH		(2 << 10)
33#define AT91_MC_MST(n)			BIT(16 + (n))
34#define AT91_MC_SVMST(n)		BIT(24 + (n))
35
36#define AT91_MC_AASR			0x08
37
38#define AT91_MC_MPR			0x0c
39#define AT91_MPR_MSTP(n)		GENMASK(2 + ((x) * 4), ((x) * 4))
40
41/* External Bus Interface (EBI) registers */
42#define AT91_MC_EBI_CSA			0x60
43#define AT91_MC_EBI_CS(n)		BIT(x)
44#define AT91_MC_EBI_NUM_CS		8
45
46#define AT91_MC_EBI_CFGR		0x64
47#define AT91_MC_EBI_DBPUC		BIT(0)
48
49/* Static Memory Controller (SMC) registers */
50#define AT91_MC_SMC_CSR(n)		(0x70 + ((n) * 4))
51#define AT91_MC_SMC_NWS			GENMASK(6, 0)
52#define AT91_MC_SMC_NWS_(x)		((x) << 0)
53#define AT91_MC_SMC_WSEN		BIT(7)
54#define AT91_MC_SMC_TDF			GENMASK(11, 8)
55#define AT91_MC_SMC_TDF_(x)		((x) << 8)
56#define AT91_MC_SMC_TDF_MAX		0xf
57#define AT91_MC_SMC_BAT			BIT(12)
58#define AT91_MC_SMC_DBW			GENMASK(14, 13)
59#define AT91_MC_SMC_DBW_16		(1 << 13)
60#define AT91_MC_SMC_DBW_8		(2 << 13)
61#define AT91_MC_SMC_DPR			BIT(15)
62#define AT91_MC_SMC_ACSS		GENMASK(17, 16)
63#define AT91_MC_SMC_ACSS_(x)		((x) << 16)
64#define AT91_MC_SMC_ACSS_MAX		3
65#define AT91_MC_SMC_RWSETUP		GENMASK(26, 24)
66#define AT91_MC_SMC_RWSETUP_(x)		((x) << 24)
67#define AT91_MC_SMC_RWHOLD		GENMASK(30, 28)
68#define AT91_MC_SMC_RWHOLD_(x)		((x) << 28)
69#define AT91_MC_SMC_RWHOLDSETUP_MAX	7
70
71/* SDRAM Controller registers */
72#define AT91_MC_SDRAMC_MR		0x90
73#define AT91_MC_SDRAMC_MODE		GENMASK(3, 0)
74#define AT91_MC_SDRAMC_MODE_NORMAL	(0 << 0)
75#define AT91_MC_SDRAMC_MODE_NOP		(1 << 0)
76#define AT91_MC_SDRAMC_MODE_PRECHARGE	(2 << 0)
77#define AT91_MC_SDRAMC_MODE_LMR		(3 << 0)
78#define AT91_MC_SDRAMC_MODE_REFRESH	(4 << 0)
79#define AT91_MC_SDRAMC_DBW_16		BIT(4)
80
81#define AT91_MC_SDRAMC_TR		0x94
82#define AT91_MC_SDRAMC_COUNT		GENMASK(11, 0)
83
84#define AT91_MC_SDRAMC_CR		0x98
85#define AT91_MC_SDRAMC_NC		GENMASK(1, 0)
86#define AT91_MC_SDRAMC_NC_8		(0 << 0)
87#define AT91_MC_SDRAMC_NC_9		(1 << 0)
88#define AT91_MC_SDRAMC_NC_10		(2 << 0)
89#define AT91_MC_SDRAMC_NC_11		(3 << 0)
90#define AT91_MC_SDRAMC_NR		GENMASK(3, 2)
91#define AT91_MC_SDRAMC_NR_11		(0 << 2)
92#define AT91_MC_SDRAMC_NR_12		(1 << 2)
93#define AT91_MC_SDRAMC_NR_13		(2 << 2)
94#define AT91_MC_SDRAMC_NB		BIT(4)
95#define AT91_MC_SDRAMC_NB_2		(0 << 4)
96#define AT91_MC_SDRAMC_NB_4		(1 << 4)
97#define AT91_MC_SDRAMC_CAS		GENMASK(6, 5)
98#define AT91_MC_SDRAMC_CAS_2		(2 << 5)
99#define AT91_MC_SDRAMC_TWR		GENMASK(10,  7)
100#define AT91_MC_SDRAMC_TRC		GENMASK(14, 11)
101#define AT91_MC_SDRAMC_TRP		GENMASK(18, 15)
102#define AT91_MC_SDRAMC_TRCD		GENMASK(22, 19)
103#define AT91_MC_SDRAMC_TRAS		GENMASK(26, 23)
104#define AT91_MC_SDRAMC_TXSR		GENMASK(30, 27)
105
106#define AT91_MC_SDRAMC_SRR		0x9c
107#define AT91_MC_SDRAMC_SRCB		BIT(0)
108
109#define AT91_MC_SDRAMC_LPR		0xa0
110#define AT91_MC_SDRAMC_LPCB		BIT(0)
111
112#define AT91_MC_SDRAMC_IER		0xa4
113#define AT91_MC_SDRAMC_IDR		0xa8
114#define AT91_MC_SDRAMC_IMR		0xac
115#define AT91_MC_SDRAMC_ISR		0xb0
116#define AT91_MC_SDRAMC_RES		BIT(0)
117
118/* Burst Flash Controller register */
119#define AT91_MC_BFC_MR			0xc0
120#define AT91_MC_BFC_BFCOM		GENMASK(1, 0)
121#define AT91_MC_BFC_BFCOM_DISABLED	(0 << 0)
122#define AT91_MC_BFC_BFCOM_ASYNC		(1 << 0)
123#define AT91_MC_BFC_BFCOM_BURST		(2 << 0)
124#define AT91_MC_BFC_BFCC		GENMASK(3, 2)
125#define AT91_MC_BFC_BFCC_MCK		(1 << 2)
126#define AT91_MC_BFC_BFCC_DIV2		(2 << 2)
127#define AT91_MC_BFC_BFCC_DIV4		(3 << 2)
128#define AT91_MC_BFC_AVL			GENMASK(7,  4)
129#define AT91_MC_BFC_PAGES		GENMASK(10, 8)
130#define AT91_MC_BFC_PAGES_NO_PAGE	(0 << 8)
131#define AT91_MC_BFC_PAGES_16		(1 << 8)
132#define AT91_MC_BFC_PAGES_32		(2 << 8)
133#define AT91_MC_BFC_PAGES_64		(3 << 8)
134#define AT91_MC_BFC_PAGES_128		(4 << 8)
135#define AT91_MC_BFC_PAGES_256		(5 << 8)
136#define AT91_MC_BFC_PAGES_512		(6 << 8)
137#define AT91_MC_BFC_PAGES_1024		(7 << 8)
138#define AT91_MC_BFC_OEL			GENMASK(13, 12)
139#define AT91_MC_BFC_BAAEN		BIT(16)
140#define AT91_MC_BFC_BFOEH		BIT(17)
141#define AT91_MC_BFC_MUXEN		BIT(18)
142#define AT91_MC_BFC_RDYEN		BIT(19)
143
144#endif /* _LINUX_MFD_SYSCON_ATMEL_MC_H_ */
145