1#ifndef _LINUX_IRQ_H 2#define _LINUX_IRQ_H 3 4/* 5 * Please do not include this file in generic code. There is currently 6 * no requirement for any architecture to implement anything held 7 * within this file. 8 * 9 * Thanks. --rmk 10 */ 11 12#include <linux/smp.h> 13#include <linux/linkage.h> 14#include <linux/cache.h> 15#include <linux/spinlock.h> 16#include <linux/cpumask.h> 17#include <linux/gfp.h> 18#include <linux/irqhandler.h> 19#include <linux/irqreturn.h> 20#include <linux/irqnr.h> 21#include <linux/errno.h> 22#include <linux/topology.h> 23#include <linux/wait.h> 24#include <linux/io.h> 25 26#include <asm/irq.h> 27#include <asm/ptrace.h> 28#include <asm/irq_regs.h> 29 30struct seq_file; 31struct module; 32struct msi_msg; 33enum irqchip_irq_state; 34 35/* 36 * IRQ line status. 37 * 38 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 39 * 40 * IRQ_TYPE_NONE - default, unspecified type 41 * IRQ_TYPE_EDGE_RISING - rising edge triggered 42 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 43 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 44 * IRQ_TYPE_LEVEL_HIGH - high level triggered 45 * IRQ_TYPE_LEVEL_LOW - low level triggered 46 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 47 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 48 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 49 * to setup the HW to a sane default (used 50 * by irqdomain map() callbacks to synchronize 51 * the HW state and SW flags for a newly 52 * allocated descriptor). 53 * 54 * IRQ_TYPE_PROBE - Special flag for probing in progress 55 * 56 * Bits which can be modified via irq_set/clear/modify_status_flags() 57 * IRQ_LEVEL - Interrupt is level type. Will be also 58 * updated in the code when the above trigger 59 * bits are modified via irq_set_irq_type() 60 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 61 * it from affinity setting 62 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 63 * IRQ_NOREQUEST - Interrupt cannot be requested via 64 * request_irq() 65 * IRQ_NOTHREAD - Interrupt cannot be threaded 66 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 67 * request/setup_irq() 68 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 69 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 70 * IRQ_NESTED_THREAD - Interrupt nests into another thread 71 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 72 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude 73 * it from the spurious interrupt detection 74 * mechanism and from core side polling. 75 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable 76 */ 77enum { 78 IRQ_TYPE_NONE = 0x00000000, 79 IRQ_TYPE_EDGE_RISING = 0x00000001, 80 IRQ_TYPE_EDGE_FALLING = 0x00000002, 81 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 82 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 83 IRQ_TYPE_LEVEL_LOW = 0x00000008, 84 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 85 IRQ_TYPE_SENSE_MASK = 0x0000000f, 86 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 87 88 IRQ_TYPE_PROBE = 0x00000010, 89 90 IRQ_LEVEL = (1 << 8), 91 IRQ_PER_CPU = (1 << 9), 92 IRQ_NOPROBE = (1 << 10), 93 IRQ_NOREQUEST = (1 << 11), 94 IRQ_NOAUTOEN = (1 << 12), 95 IRQ_NO_BALANCING = (1 << 13), 96 IRQ_MOVE_PCNTXT = (1 << 14), 97 IRQ_NESTED_THREAD = (1 << 15), 98 IRQ_NOTHREAD = (1 << 16), 99 IRQ_PER_CPU_DEVID = (1 << 17), 100 IRQ_IS_POLLED = (1 << 18), 101 IRQ_DISABLE_UNLAZY = (1 << 19), 102}; 103 104#define IRQF_MODIFY_MASK \ 105 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 106 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 107 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ 108 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY) 109 110#define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 111 112/* 113 * Return value for chip->irq_set_affinity() 114 * 115 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity 116 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity 117 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to 118 * support stacked irqchips, which indicates skipping 119 * all descendent irqchips. 120 */ 121enum { 122 IRQ_SET_MASK_OK = 0, 123 IRQ_SET_MASK_OK_NOCOPY, 124 IRQ_SET_MASK_OK_DONE, 125}; 126 127struct msi_desc; 128struct irq_domain; 129 130/** 131 * struct irq_common_data - per irq data shared by all irqchips 132 * @state_use_accessors: status information for irq chip functions. 133 * Use accessor functions to deal with it 134 * @node: node index useful for balancing 135 * @handler_data: per-IRQ data for the irq_chip methods 136 * @affinity: IRQ affinity on SMP 137 * @msi_desc: MSI descriptor 138 */ 139struct irq_common_data { 140 unsigned int state_use_accessors; 141#ifdef CONFIG_NUMA 142 unsigned int node; 143#endif 144 void *handler_data; 145 struct msi_desc *msi_desc; 146 cpumask_var_t affinity; 147}; 148 149/** 150 * struct irq_data - per irq chip data passed down to chip functions 151 * @mask: precomputed bitmask for accessing the chip registers 152 * @irq: interrupt number 153 * @hwirq: hardware interrupt number, local to the interrupt domain 154 * @common: point to data shared by all irqchips 155 * @chip: low level interrupt hardware access 156 * @domain: Interrupt translation domain; responsible for mapping 157 * between hwirq number and linux irq number. 158 * @parent_data: pointer to parent struct irq_data to support hierarchy 159 * irq_domain 160 * @chip_data: platform-specific per-chip private data for the chip 161 * methods, to allow shared chip implementations 162 */ 163struct irq_data { 164 u32 mask; 165 unsigned int irq; 166 unsigned long hwirq; 167 struct irq_common_data *common; 168 struct irq_chip *chip; 169 struct irq_domain *domain; 170#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 171 struct irq_data *parent_data; 172#endif 173 void *chip_data; 174}; 175 176/* 177 * Bit masks for irq_common_data.state_use_accessors 178 * 179 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 180 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 181 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 182 * IRQD_PER_CPU - Interrupt is per cpu 183 * IRQD_AFFINITY_SET - Interrupt affinity was set 184 * IRQD_LEVEL - Interrupt is level triggered 185 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 186 * from suspend 187 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process 188 * context 189 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 190 * IRQD_IRQ_MASKED - Masked state of the interrupt 191 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 192 * IRQD_WAKEUP_ARMED - Wakeup mode armed 193 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU 194 */ 195enum { 196 IRQD_TRIGGER_MASK = 0xf, 197 IRQD_SETAFFINITY_PENDING = (1 << 8), 198 IRQD_NO_BALANCING = (1 << 10), 199 IRQD_PER_CPU = (1 << 11), 200 IRQD_AFFINITY_SET = (1 << 12), 201 IRQD_LEVEL = (1 << 13), 202 IRQD_WAKEUP_STATE = (1 << 14), 203 IRQD_MOVE_PCNTXT = (1 << 15), 204 IRQD_IRQ_DISABLED = (1 << 16), 205 IRQD_IRQ_MASKED = (1 << 17), 206 IRQD_IRQ_INPROGRESS = (1 << 18), 207 IRQD_WAKEUP_ARMED = (1 << 19), 208 IRQD_FORWARDED_TO_VCPU = (1 << 20), 209}; 210 211#define __irqd_to_state(d) ((d)->common->state_use_accessors) 212 213static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 214{ 215 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; 216} 217 218static inline bool irqd_is_per_cpu(struct irq_data *d) 219{ 220 return __irqd_to_state(d) & IRQD_PER_CPU; 221} 222 223static inline bool irqd_can_balance(struct irq_data *d) 224{ 225 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 226} 227 228static inline bool irqd_affinity_was_set(struct irq_data *d) 229{ 230 return __irqd_to_state(d) & IRQD_AFFINITY_SET; 231} 232 233static inline void irqd_mark_affinity_was_set(struct irq_data *d) 234{ 235 __irqd_to_state(d) |= IRQD_AFFINITY_SET; 236} 237 238static inline u32 irqd_get_trigger_type(struct irq_data *d) 239{ 240 return __irqd_to_state(d) & IRQD_TRIGGER_MASK; 241} 242 243/* 244 * Must only be called inside irq_chip.irq_set_type() functions. 245 */ 246static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 247{ 248 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; 249 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; 250} 251 252static inline bool irqd_is_level_type(struct irq_data *d) 253{ 254 return __irqd_to_state(d) & IRQD_LEVEL; 255} 256 257static inline bool irqd_is_wakeup_set(struct irq_data *d) 258{ 259 return __irqd_to_state(d) & IRQD_WAKEUP_STATE; 260} 261 262static inline bool irqd_can_move_in_process_context(struct irq_data *d) 263{ 264 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; 265} 266 267static inline bool irqd_irq_disabled(struct irq_data *d) 268{ 269 return __irqd_to_state(d) & IRQD_IRQ_DISABLED; 270} 271 272static inline bool irqd_irq_masked(struct irq_data *d) 273{ 274 return __irqd_to_state(d) & IRQD_IRQ_MASKED; 275} 276 277static inline bool irqd_irq_inprogress(struct irq_data *d) 278{ 279 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; 280} 281 282static inline bool irqd_is_wakeup_armed(struct irq_data *d) 283{ 284 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; 285} 286 287static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) 288{ 289 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; 290} 291 292static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) 293{ 294 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; 295} 296 297static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) 298{ 299 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; 300} 301 302static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 303{ 304 return d->hwirq; 305} 306 307/** 308 * struct irq_chip - hardware interrupt chip descriptor 309 * 310 * @name: name for /proc/interrupts 311 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 312 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 313 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 314 * @irq_disable: disable the interrupt 315 * @irq_ack: start of a new interrupt 316 * @irq_mask: mask an interrupt source 317 * @irq_mask_ack: ack and mask an interrupt source 318 * @irq_unmask: unmask an interrupt source 319 * @irq_eoi: end of interrupt 320 * @irq_set_affinity: set the CPU affinity on SMP machines 321 * @irq_retrigger: resend an IRQ to the CPU 322 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 323 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 324 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 325 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 326 * @irq_cpu_online: configure an interrupt source for a secondary CPU 327 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 328 * @irq_suspend: function called from core code on suspend once per 329 * chip, when one or more interrupts are installed 330 * @irq_resume: function called from core code on resume once per chip, 331 * when one ore more interrupts are installed 332 * @irq_pm_shutdown: function called from core code on shutdown once per chip 333 * @irq_calc_mask: Optional function to set irq_data.mask for special cases 334 * @irq_print_chip: optional to print special chip info in show_interrupts 335 * @irq_request_resources: optional to request resources before calling 336 * any other callback related to this irq 337 * @irq_release_resources: optional to release resources acquired with 338 * irq_request_resources 339 * @irq_compose_msi_msg: optional to compose message content for MSI 340 * @irq_write_msi_msg: optional to write message content for MSI 341 * @irq_get_irqchip_state: return the internal state of an interrupt 342 * @irq_set_irqchip_state: set the internal state of a interrupt 343 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine 344 * @flags: chip specific flags 345 */ 346struct irq_chip { 347 const char *name; 348 unsigned int (*irq_startup)(struct irq_data *data); 349 void (*irq_shutdown)(struct irq_data *data); 350 void (*irq_enable)(struct irq_data *data); 351 void (*irq_disable)(struct irq_data *data); 352 353 void (*irq_ack)(struct irq_data *data); 354 void (*irq_mask)(struct irq_data *data); 355 void (*irq_mask_ack)(struct irq_data *data); 356 void (*irq_unmask)(struct irq_data *data); 357 void (*irq_eoi)(struct irq_data *data); 358 359 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 360 int (*irq_retrigger)(struct irq_data *data); 361 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 362 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 363 364 void (*irq_bus_lock)(struct irq_data *data); 365 void (*irq_bus_sync_unlock)(struct irq_data *data); 366 367 void (*irq_cpu_online)(struct irq_data *data); 368 void (*irq_cpu_offline)(struct irq_data *data); 369 370 void (*irq_suspend)(struct irq_data *data); 371 void (*irq_resume)(struct irq_data *data); 372 void (*irq_pm_shutdown)(struct irq_data *data); 373 374 void (*irq_calc_mask)(struct irq_data *data); 375 376 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 377 int (*irq_request_resources)(struct irq_data *data); 378 void (*irq_release_resources)(struct irq_data *data); 379 380 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); 381 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); 382 383 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); 384 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); 385 386 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); 387 388 unsigned long flags; 389}; 390 391/* 392 * irq_chip specific flags 393 * 394 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 395 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 396 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 397 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 398 * when irq enabled 399 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 400 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask 401 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode 402 */ 403enum { 404 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 405 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 406 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 407 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 408 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 409 IRQCHIP_ONESHOT_SAFE = (1 << 5), 410 IRQCHIP_EOI_THREADED = (1 << 6), 411}; 412 413#include <linux/irqdesc.h> 414 415/* 416 * Pick up the arch-dependent methods: 417 */ 418#include <asm/hw_irq.h> 419 420#ifndef NR_IRQS_LEGACY 421# define NR_IRQS_LEGACY 0 422#endif 423 424#ifndef ARCH_IRQ_INIT_FLAGS 425# define ARCH_IRQ_INIT_FLAGS 0 426#endif 427 428#define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 429 430struct irqaction; 431extern int setup_irq(unsigned int irq, struct irqaction *new); 432extern void remove_irq(unsigned int irq, struct irqaction *act); 433extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 434extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 435 436extern void irq_cpu_online(void); 437extern void irq_cpu_offline(void); 438extern int irq_set_affinity_locked(struct irq_data *data, 439 const struct cpumask *cpumask, bool force); 440extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); 441 442extern void irq_migrate_all_off_this_cpu(void); 443 444#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 445void irq_move_irq(struct irq_data *data); 446void irq_move_masked_irq(struct irq_data *data); 447#else 448static inline void irq_move_irq(struct irq_data *data) { } 449static inline void irq_move_masked_irq(struct irq_data *data) { } 450#endif 451 452extern int no_irq_affinity; 453 454#ifdef CONFIG_HARDIRQS_SW_RESEND 455int irq_set_parent(int irq, int parent_irq); 456#else 457static inline int irq_set_parent(int irq, int parent_irq) 458{ 459 return 0; 460} 461#endif 462 463/* 464 * Built-in IRQ handlers for various IRQ types, 465 * callable via desc->handle_irq() 466 */ 467extern void handle_level_irq(struct irq_desc *desc); 468extern void handle_fasteoi_irq(struct irq_desc *desc); 469extern void handle_edge_irq(struct irq_desc *desc); 470extern void handle_edge_eoi_irq(struct irq_desc *desc); 471extern void handle_simple_irq(struct irq_desc *desc); 472extern void handle_percpu_irq(struct irq_desc *desc); 473extern void handle_percpu_devid_irq(struct irq_desc *desc); 474extern void handle_bad_irq(struct irq_desc *desc); 475extern void handle_nested_irq(unsigned int irq); 476 477extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); 478#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 479extern void irq_chip_enable_parent(struct irq_data *data); 480extern void irq_chip_disable_parent(struct irq_data *data); 481extern void irq_chip_ack_parent(struct irq_data *data); 482extern int irq_chip_retrigger_hierarchy(struct irq_data *data); 483extern void irq_chip_mask_parent(struct irq_data *data); 484extern void irq_chip_unmask_parent(struct irq_data *data); 485extern void irq_chip_eoi_parent(struct irq_data *data); 486extern int irq_chip_set_affinity_parent(struct irq_data *data, 487 const struct cpumask *dest, 488 bool force); 489extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); 490extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, 491 void *vcpu_info); 492extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); 493#endif 494 495/* Handling of unhandled and spurious interrupts: */ 496extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); 497 498 499/* Enable/disable irq debugging output: */ 500extern int noirqdebug_setup(char *str); 501 502/* Checks whether the interrupt can be requested by request_irq(): */ 503extern int can_request_irq(unsigned int irq, unsigned long irqflags); 504 505/* Dummy irq-chip implementations: */ 506extern struct irq_chip no_irq_chip; 507extern struct irq_chip dummy_irq_chip; 508 509extern void 510irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 511 irq_flow_handler_t handle, const char *name); 512 513static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 514 irq_flow_handler_t handle) 515{ 516 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 517} 518 519extern int irq_set_percpu_devid(unsigned int irq); 520 521extern void 522__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 523 const char *name); 524 525static inline void 526irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 527{ 528 __irq_set_handler(irq, handle, 0, NULL); 529} 530 531/* 532 * Set a highlevel chained flow handler for a given IRQ. 533 * (a chained handler is automatically enabled and set to 534 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 535 */ 536static inline void 537irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 538{ 539 __irq_set_handler(irq, handle, 1, NULL); 540} 541 542/* 543 * Set a highlevel chained flow handler and its data for a given IRQ. 544 * (a chained handler is automatically enabled and set to 545 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 546 */ 547void 548irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, 549 void *data); 550 551void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 552 553static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 554{ 555 irq_modify_status(irq, 0, set); 556} 557 558static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 559{ 560 irq_modify_status(irq, clr, 0); 561} 562 563static inline void irq_set_noprobe(unsigned int irq) 564{ 565 irq_modify_status(irq, 0, IRQ_NOPROBE); 566} 567 568static inline void irq_set_probe(unsigned int irq) 569{ 570 irq_modify_status(irq, IRQ_NOPROBE, 0); 571} 572 573static inline void irq_set_nothread(unsigned int irq) 574{ 575 irq_modify_status(irq, 0, IRQ_NOTHREAD); 576} 577 578static inline void irq_set_thread(unsigned int irq) 579{ 580 irq_modify_status(irq, IRQ_NOTHREAD, 0); 581} 582 583static inline void irq_set_nested_thread(unsigned int irq, bool nest) 584{ 585 if (nest) 586 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 587 else 588 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 589} 590 591static inline void irq_set_percpu_devid_flags(unsigned int irq) 592{ 593 irq_set_status_flags(irq, 594 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 595 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 596} 597 598/* Set/get chip/data for an IRQ: */ 599extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 600extern int irq_set_handler_data(unsigned int irq, void *data); 601extern int irq_set_chip_data(unsigned int irq, void *data); 602extern int irq_set_irq_type(unsigned int irq, unsigned int type); 603extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 604extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, 605 struct msi_desc *entry); 606extern struct irq_data *irq_get_irq_data(unsigned int irq); 607 608static inline struct irq_chip *irq_get_chip(unsigned int irq) 609{ 610 struct irq_data *d = irq_get_irq_data(irq); 611 return d ? d->chip : NULL; 612} 613 614static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 615{ 616 return d->chip; 617} 618 619static inline void *irq_get_chip_data(unsigned int irq) 620{ 621 struct irq_data *d = irq_get_irq_data(irq); 622 return d ? d->chip_data : NULL; 623} 624 625static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 626{ 627 return d->chip_data; 628} 629 630static inline void *irq_get_handler_data(unsigned int irq) 631{ 632 struct irq_data *d = irq_get_irq_data(irq); 633 return d ? d->common->handler_data : NULL; 634} 635 636static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 637{ 638 return d->common->handler_data; 639} 640 641static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 642{ 643 struct irq_data *d = irq_get_irq_data(irq); 644 return d ? d->common->msi_desc : NULL; 645} 646 647static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) 648{ 649 return d->common->msi_desc; 650} 651 652static inline u32 irq_get_trigger_type(unsigned int irq) 653{ 654 struct irq_data *d = irq_get_irq_data(irq); 655 return d ? irqd_get_trigger_type(d) : 0; 656} 657 658static inline int irq_common_data_get_node(struct irq_common_data *d) 659{ 660#ifdef CONFIG_NUMA 661 return d->node; 662#else 663 return 0; 664#endif 665} 666 667static inline int irq_data_get_node(struct irq_data *d) 668{ 669 return irq_common_data_get_node(d->common); 670} 671 672static inline struct cpumask *irq_get_affinity_mask(int irq) 673{ 674 struct irq_data *d = irq_get_irq_data(irq); 675 676 return d ? d->common->affinity : NULL; 677} 678 679static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) 680{ 681 return d->common->affinity; 682} 683 684unsigned int arch_dynirq_lower_bound(unsigned int from); 685 686int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 687 struct module *owner); 688 689/* use macros to avoid needing export.h for THIS_MODULE */ 690#define irq_alloc_descs(irq, from, cnt, node) \ 691 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE) 692 693#define irq_alloc_desc(node) \ 694 irq_alloc_descs(-1, 0, 1, node) 695 696#define irq_alloc_desc_at(at, node) \ 697 irq_alloc_descs(at, at, 1, node) 698 699#define irq_alloc_desc_from(from, node) \ 700 irq_alloc_descs(-1, from, 1, node) 701 702#define irq_alloc_descs_from(from, cnt, node) \ 703 irq_alloc_descs(-1, from, cnt, node) 704 705void irq_free_descs(unsigned int irq, unsigned int cnt); 706static inline void irq_free_desc(unsigned int irq) 707{ 708 irq_free_descs(irq, 1); 709} 710 711#ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ 712unsigned int irq_alloc_hwirqs(int cnt, int node); 713static inline unsigned int irq_alloc_hwirq(int node) 714{ 715 return irq_alloc_hwirqs(1, node); 716} 717void irq_free_hwirqs(unsigned int from, int cnt); 718static inline void irq_free_hwirq(unsigned int irq) 719{ 720 return irq_free_hwirqs(irq, 1); 721} 722int arch_setup_hwirq(unsigned int irq, int node); 723void arch_teardown_hwirq(unsigned int irq); 724#endif 725 726#ifdef CONFIG_GENERIC_IRQ_LEGACY 727void irq_init_desc(unsigned int irq); 728#endif 729 730/** 731 * struct irq_chip_regs - register offsets for struct irq_gci 732 * @enable: Enable register offset to reg_base 733 * @disable: Disable register offset to reg_base 734 * @mask: Mask register offset to reg_base 735 * @ack: Ack register offset to reg_base 736 * @eoi: Eoi register offset to reg_base 737 * @type: Type configuration register offset to reg_base 738 * @polarity: Polarity configuration register offset to reg_base 739 */ 740struct irq_chip_regs { 741 unsigned long enable; 742 unsigned long disable; 743 unsigned long mask; 744 unsigned long ack; 745 unsigned long eoi; 746 unsigned long type; 747 unsigned long polarity; 748}; 749 750/** 751 * struct irq_chip_type - Generic interrupt chip instance for a flow type 752 * @chip: The real interrupt chip which provides the callbacks 753 * @regs: Register offsets for this chip 754 * @handler: Flow handler associated with this chip 755 * @type: Chip can handle these flow types 756 * @mask_cache_priv: Cached mask register private to the chip type 757 * @mask_cache: Pointer to cached mask register 758 * 759 * A irq_generic_chip can have several instances of irq_chip_type when 760 * it requires different functions and register offsets for different 761 * flow types. 762 */ 763struct irq_chip_type { 764 struct irq_chip chip; 765 struct irq_chip_regs regs; 766 irq_flow_handler_t handler; 767 u32 type; 768 u32 mask_cache_priv; 769 u32 *mask_cache; 770}; 771 772/** 773 * struct irq_chip_generic - Generic irq chip data structure 774 * @lock: Lock to protect register and cache data access 775 * @reg_base: Register base address (virtual) 776 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) 777 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) 778 * @suspend: Function called from core code on suspend once per 779 * chip; can be useful instead of irq_chip::suspend to 780 * handle chip details even when no interrupts are in use 781 * @resume: Function called from core code on resume once per chip; 782 * can be useful instead of irq_chip::suspend to handle 783 * chip details even when no interrupts are in use 784 * @irq_base: Interrupt base nr for this chip 785 * @irq_cnt: Number of interrupts handled by this chip 786 * @mask_cache: Cached mask register shared between all chip types 787 * @type_cache: Cached type register 788 * @polarity_cache: Cached polarity register 789 * @wake_enabled: Interrupt can wakeup from suspend 790 * @wake_active: Interrupt is marked as an wakeup from suspend source 791 * @num_ct: Number of available irq_chip_type instances (usually 1) 792 * @private: Private data for non generic chip callbacks 793 * @installed: bitfield to denote installed interrupts 794 * @unused: bitfield to denote unused interrupts 795 * @domain: irq domain pointer 796 * @list: List head for keeping track of instances 797 * @chip_types: Array of interrupt irq_chip_types 798 * 799 * Note, that irq_chip_generic can have multiple irq_chip_type 800 * implementations which can be associated to a particular irq line of 801 * an irq_chip_generic instance. That allows to share and protect 802 * state in an irq_chip_generic instance when we need to implement 803 * different flow mechanisms (level/edge) for it. 804 */ 805struct irq_chip_generic { 806 raw_spinlock_t lock; 807 void __iomem *reg_base; 808 u32 (*reg_readl)(void __iomem *addr); 809 void (*reg_writel)(u32 val, void __iomem *addr); 810 void (*suspend)(struct irq_chip_generic *gc); 811 void (*resume)(struct irq_chip_generic *gc); 812 unsigned int irq_base; 813 unsigned int irq_cnt; 814 u32 mask_cache; 815 u32 type_cache; 816 u32 polarity_cache; 817 u32 wake_enabled; 818 u32 wake_active; 819 unsigned int num_ct; 820 void *private; 821 unsigned long installed; 822 unsigned long unused; 823 struct irq_domain *domain; 824 struct list_head list; 825 struct irq_chip_type chip_types[0]; 826}; 827 828/** 829 * enum irq_gc_flags - Initialization flags for generic irq chips 830 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 831 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 832 * irq chips which need to call irq_set_wake() on 833 * the parent irq. Usually GPIO implementations 834 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private 835 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask 836 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) 837 */ 838enum irq_gc_flags { 839 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 840 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 841 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, 842 IRQ_GC_NO_MASK = 1 << 3, 843 IRQ_GC_BE_IO = 1 << 4, 844}; 845 846/* 847 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains 848 * @irqs_per_chip: Number of interrupts per chip 849 * @num_chips: Number of chips 850 * @irq_flags_to_set: IRQ* flags to set on irq setup 851 * @irq_flags_to_clear: IRQ* flags to clear on irq setup 852 * @gc_flags: Generic chip specific setup flags 853 * @gc: Array of pointers to generic interrupt chips 854 */ 855struct irq_domain_chip_generic { 856 unsigned int irqs_per_chip; 857 unsigned int num_chips; 858 unsigned int irq_flags_to_clear; 859 unsigned int irq_flags_to_set; 860 enum irq_gc_flags gc_flags; 861 struct irq_chip_generic *gc[0]; 862}; 863 864/* Generic chip callback functions */ 865void irq_gc_noop(struct irq_data *d); 866void irq_gc_mask_disable_reg(struct irq_data *d); 867void irq_gc_mask_set_bit(struct irq_data *d); 868void irq_gc_mask_clr_bit(struct irq_data *d); 869void irq_gc_unmask_enable_reg(struct irq_data *d); 870void irq_gc_ack_set_bit(struct irq_data *d); 871void irq_gc_ack_clr_bit(struct irq_data *d); 872void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); 873void irq_gc_eoi(struct irq_data *d); 874int irq_gc_set_wake(struct irq_data *d, unsigned int on); 875 876/* Setup functions for irq_chip_generic */ 877int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 878 irq_hw_number_t hw_irq); 879struct irq_chip_generic * 880irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 881 void __iomem *reg_base, irq_flow_handler_t handler); 882void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 883 enum irq_gc_flags flags, unsigned int clr, 884 unsigned int set); 885int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 886void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 887 unsigned int clr, unsigned int set); 888 889struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); 890int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, 891 int num_ct, const char *name, 892 irq_flow_handler_t handler, 893 unsigned int clr, unsigned int set, 894 enum irq_gc_flags flags); 895 896 897static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 898{ 899 return container_of(d->chip, struct irq_chip_type, chip); 900} 901 902#define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 903 904#ifdef CONFIG_SMP 905static inline void irq_gc_lock(struct irq_chip_generic *gc) 906{ 907 raw_spin_lock(&gc->lock); 908} 909 910static inline void irq_gc_unlock(struct irq_chip_generic *gc) 911{ 912 raw_spin_unlock(&gc->lock); 913} 914#else 915static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 916static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 917#endif 918 919static inline void irq_reg_writel(struct irq_chip_generic *gc, 920 u32 val, int reg_offset) 921{ 922 if (gc->reg_writel) 923 gc->reg_writel(val, gc->reg_base + reg_offset); 924 else 925 writel(val, gc->reg_base + reg_offset); 926} 927 928static inline u32 irq_reg_readl(struct irq_chip_generic *gc, 929 int reg_offset) 930{ 931 if (gc->reg_readl) 932 return gc->reg_readl(gc->reg_base + reg_offset); 933 else 934 return readl(gc->reg_base + reg_offset); 935} 936 937#endif /* _LINUX_IRQ_H */ 938