1/* 2 * intel TCO Watchdog Driver 3 * 4 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor 12 * provide warranty for any of this software. This material is 13 * provided "AS-IS" and at no charge. 14 * 15 * The TCO watchdog is implemented in the following I/O controller hubs: 16 * (See the intel documentation on http://developer.intel.com.) 17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) 18 * document number 290687-002, 298242-027: 82801BA (ICH2) 19 * document number 290733-003, 290739-013: 82801CA (ICH3-S) 20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M) 21 * document number 290744-001, 290745-025: 82801DB (ICH4) 22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M) 23 * document number 273599-001, 273645-002: 82801E (C-ICH) 24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) 25 * document number 300641-004, 300884-013: 6300ESB 26 * document number 301473-002, 301474-026: 82801F (ICH6) 27 * document number 313082-001, 313075-006: 631xESB, 632xESB 28 * document number 307013-003, 307014-024: 82801G (ICH7) 29 * document number 322896-001, 322897-001: NM10 30 * document number 313056-003, 313057-017: 82801H (ICH8) 31 * document number 316972-004, 316973-012: 82801I (ICH9) 32 * document number 319973-002, 319974-002: 82801J (ICH10) 33 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) 34 * document number 320066-003, 320257-008: EP80597 (IICH) 35 * document number 324645-001, 324646-001: Cougar Point (CPT) 36 * document number TBD : Patsburg (PBG) 37 * document number TBD : DH89xxCC 38 * document number TBD : Panther Point 39 * document number TBD : Lynx Point 40 * document number TBD : Lynx Point-LP 41 */ 42 43/* 44 * Includes, defines, variables, module parameters, ... 45 */ 46 47#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 48 49/* Module and version information */ 50#define DRV_NAME "iTCO_wdt" 51#define DRV_VERSION "1.11" 52 53/* Includes */ 54#include <linux/acpi.h> /* For ACPI support */ 55#include <linux/module.h> /* For module specific items */ 56#include <linux/moduleparam.h> /* For new moduleparam's */ 57#include <linux/types.h> /* For standard types (like size_t) */ 58#include <linux/errno.h> /* For the -ENODEV/... values */ 59#include <linux/kernel.h> /* For printk/panic/... */ 60#include <linux/watchdog.h> /* For the watchdog specific items */ 61#include <linux/init.h> /* For __init/__exit/... */ 62#include <linux/fs.h> /* For file operations */ 63#include <linux/platform_device.h> /* For platform_driver framework */ 64#include <linux/pci.h> /* For pci functions */ 65#include <linux/ioport.h> /* For io-port access */ 66#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ 67#include <linux/uaccess.h> /* For copy_to_user/put_user/... */ 68#include <linux/io.h> /* For inb/outb/... */ 69#include <linux/platform_data/itco_wdt.h> 70 71#include "iTCO_vendor.h" 72 73/* Address definitions for the TCO */ 74/* TCO base address */ 75#define TCOBASE (iTCO_wdt_private.tco_res->start) 76/* SMI Control and Enable Register */ 77#define SMI_EN (iTCO_wdt_private.smi_res->start) 78 79#define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */ 80#define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */ 81#define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */ 82#define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */ 83#define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */ 84#define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */ 85#define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */ 86#define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */ 87#define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */ 88 89/* internal variables */ 90static struct { /* this is private data for the iTCO_wdt device */ 91 /* TCO version/generation */ 92 unsigned int iTCO_version; 93 struct resource *tco_res; 94 struct resource *smi_res; 95 /* 96 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2), 97 * or memory-mapped PMC register bit 4 (TCO version 3). 98 */ 99 struct resource *gcs_pmc_res; 100 unsigned long __iomem *gcs_pmc; 101 /* the lock for io operations */ 102 spinlock_t io_lock; 103 struct platform_device *dev; 104 /* the PCI-device */ 105 struct pci_dev *pdev; 106 /* whether or not the watchdog has been suspended */ 107 bool suspended; 108} iTCO_wdt_private; 109 110/* module parameters */ 111#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */ 112static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */ 113module_param(heartbeat, int, 0); 114MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. " 115 "5..76 (TCO v1) or 3..614 (TCO v2), default=" 116 __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); 117 118static bool nowayout = WATCHDOG_NOWAYOUT; 119module_param(nowayout, bool, 0); 120MODULE_PARM_DESC(nowayout, 121 "Watchdog cannot be stopped once started (default=" 122 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 123 124static int turn_SMI_watchdog_clear_off = 1; 125module_param(turn_SMI_watchdog_clear_off, int, 0); 126MODULE_PARM_DESC(turn_SMI_watchdog_clear_off, 127 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)"); 128 129/* 130 * Some TCO specific functions 131 */ 132 133/* 134 * The iTCO v1 and v2's internal timer is stored as ticks which decrement 135 * every 0.6 seconds. v3's internal timer is stored as seconds (some 136 * datasheets incorrectly state 0.6 seconds). 137 */ 138static inline unsigned int seconds_to_ticks(int secs) 139{ 140 return iTCO_wdt_private.iTCO_version == 3 ? secs : (secs * 10) / 6; 141} 142 143static inline unsigned int ticks_to_seconds(int ticks) 144{ 145 return iTCO_wdt_private.iTCO_version == 3 ? ticks : (ticks * 6) / 10; 146} 147 148static inline u32 no_reboot_bit(void) 149{ 150 u32 enable_bit; 151 152 switch (iTCO_wdt_private.iTCO_version) { 153 case 3: 154 enable_bit = 0x00000010; 155 break; 156 case 2: 157 enable_bit = 0x00000020; 158 break; 159 case 4: 160 case 1: 161 default: 162 enable_bit = 0x00000002; 163 break; 164 } 165 166 return enable_bit; 167} 168 169static void iTCO_wdt_set_NO_REBOOT_bit(void) 170{ 171 u32 val32; 172 173 /* Set the NO_REBOOT bit: this disables reboots */ 174 if (iTCO_wdt_private.iTCO_version >= 2) { 175 val32 = readl(iTCO_wdt_private.gcs_pmc); 176 val32 |= no_reboot_bit(); 177 writel(val32, iTCO_wdt_private.gcs_pmc); 178 } else if (iTCO_wdt_private.iTCO_version == 1) { 179 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); 180 val32 |= no_reboot_bit(); 181 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32); 182 } 183} 184 185static int iTCO_wdt_unset_NO_REBOOT_bit(void) 186{ 187 u32 enable_bit = no_reboot_bit(); 188 u32 val32 = 0; 189 190 /* Unset the NO_REBOOT bit: this enables reboots */ 191 if (iTCO_wdt_private.iTCO_version >= 2) { 192 val32 = readl(iTCO_wdt_private.gcs_pmc); 193 val32 &= ~enable_bit; 194 writel(val32, iTCO_wdt_private.gcs_pmc); 195 196 val32 = readl(iTCO_wdt_private.gcs_pmc); 197 } else if (iTCO_wdt_private.iTCO_version == 1) { 198 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); 199 val32 &= ~enable_bit; 200 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32); 201 202 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); 203 } 204 205 if (val32 & enable_bit) 206 return -EIO; 207 208 return 0; 209} 210 211static int iTCO_wdt_start(struct watchdog_device *wd_dev) 212{ 213 unsigned int val; 214 215 spin_lock(&iTCO_wdt_private.io_lock); 216 217 iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout); 218 219 /* disable chipset's NO_REBOOT bit */ 220 if (iTCO_wdt_unset_NO_REBOOT_bit()) { 221 spin_unlock(&iTCO_wdt_private.io_lock); 222 pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n"); 223 return -EIO; 224 } 225 226 /* Force the timer to its reload value by writing to the TCO_RLD 227 register */ 228 if (iTCO_wdt_private.iTCO_version >= 2) 229 outw(0x01, TCO_RLD); 230 else if (iTCO_wdt_private.iTCO_version == 1) 231 outb(0x01, TCO_RLD); 232 233 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */ 234 val = inw(TCO1_CNT); 235 val &= 0xf7ff; 236 outw(val, TCO1_CNT); 237 val = inw(TCO1_CNT); 238 spin_unlock(&iTCO_wdt_private.io_lock); 239 240 if (val & 0x0800) 241 return -1; 242 return 0; 243} 244 245static int iTCO_wdt_stop(struct watchdog_device *wd_dev) 246{ 247 unsigned int val; 248 249 spin_lock(&iTCO_wdt_private.io_lock); 250 251 iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res); 252 253 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */ 254 val = inw(TCO1_CNT); 255 val |= 0x0800; 256 outw(val, TCO1_CNT); 257 val = inw(TCO1_CNT); 258 259 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ 260 iTCO_wdt_set_NO_REBOOT_bit(); 261 262 spin_unlock(&iTCO_wdt_private.io_lock); 263 264 if ((val & 0x0800) == 0) 265 return -1; 266 return 0; 267} 268 269static int iTCO_wdt_ping(struct watchdog_device *wd_dev) 270{ 271 spin_lock(&iTCO_wdt_private.io_lock); 272 273 iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout); 274 275 /* Reload the timer by writing to the TCO Timer Counter register */ 276 if (iTCO_wdt_private.iTCO_version >= 2) { 277 outw(0x01, TCO_RLD); 278 } else if (iTCO_wdt_private.iTCO_version == 1) { 279 /* Reset the timeout status bit so that the timer 280 * needs to count down twice again before rebooting */ 281 outw(0x0008, TCO1_STS); /* write 1 to clear bit */ 282 283 outb(0x01, TCO_RLD); 284 } 285 286 spin_unlock(&iTCO_wdt_private.io_lock); 287 return 0; 288} 289 290static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t) 291{ 292 unsigned int val16; 293 unsigned char val8; 294 unsigned int tmrval; 295 296 tmrval = seconds_to_ticks(t); 297 298 /* For TCO v1 the timer counts down twice before rebooting */ 299 if (iTCO_wdt_private.iTCO_version == 1) 300 tmrval /= 2; 301 302 /* from the specs: */ 303 /* "Values of 0h-3h are ignored and should not be attempted" */ 304 if (tmrval < 0x04) 305 return -EINVAL; 306 if (((iTCO_wdt_private.iTCO_version >= 2) && (tmrval > 0x3ff)) || 307 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f))) 308 return -EINVAL; 309 310 iTCO_vendor_pre_set_heartbeat(tmrval); 311 312 /* Write new heartbeat to watchdog */ 313 if (iTCO_wdt_private.iTCO_version >= 2) { 314 spin_lock(&iTCO_wdt_private.io_lock); 315 val16 = inw(TCOv2_TMR); 316 val16 &= 0xfc00; 317 val16 |= tmrval; 318 outw(val16, TCOv2_TMR); 319 val16 = inw(TCOv2_TMR); 320 spin_unlock(&iTCO_wdt_private.io_lock); 321 322 if ((val16 & 0x3ff) != tmrval) 323 return -EINVAL; 324 } else if (iTCO_wdt_private.iTCO_version == 1) { 325 spin_lock(&iTCO_wdt_private.io_lock); 326 val8 = inb(TCOv1_TMR); 327 val8 &= 0xc0; 328 val8 |= (tmrval & 0xff); 329 outb(val8, TCOv1_TMR); 330 val8 = inb(TCOv1_TMR); 331 spin_unlock(&iTCO_wdt_private.io_lock); 332 333 if ((val8 & 0x3f) != tmrval) 334 return -EINVAL; 335 } 336 337 wd_dev->timeout = t; 338 return 0; 339} 340 341static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev) 342{ 343 unsigned int val16; 344 unsigned char val8; 345 unsigned int time_left = 0; 346 347 /* read the TCO Timer */ 348 if (iTCO_wdt_private.iTCO_version >= 2) { 349 spin_lock(&iTCO_wdt_private.io_lock); 350 val16 = inw(TCO_RLD); 351 val16 &= 0x3ff; 352 spin_unlock(&iTCO_wdt_private.io_lock); 353 354 time_left = ticks_to_seconds(val16); 355 } else if (iTCO_wdt_private.iTCO_version == 1) { 356 spin_lock(&iTCO_wdt_private.io_lock); 357 val8 = inb(TCO_RLD); 358 val8 &= 0x3f; 359 if (!(inw(TCO1_STS) & 0x0008)) 360 val8 += (inb(TCOv1_TMR) & 0x3f); 361 spin_unlock(&iTCO_wdt_private.io_lock); 362 363 time_left = ticks_to_seconds(val8); 364 } 365 return time_left; 366} 367 368/* 369 * Kernel Interfaces 370 */ 371 372static const struct watchdog_info ident = { 373 .options = WDIOF_SETTIMEOUT | 374 WDIOF_KEEPALIVEPING | 375 WDIOF_MAGICCLOSE, 376 .firmware_version = 0, 377 .identity = DRV_NAME, 378}; 379 380static const struct watchdog_ops iTCO_wdt_ops = { 381 .owner = THIS_MODULE, 382 .start = iTCO_wdt_start, 383 .stop = iTCO_wdt_stop, 384 .ping = iTCO_wdt_ping, 385 .set_timeout = iTCO_wdt_set_timeout, 386 .get_timeleft = iTCO_wdt_get_timeleft, 387}; 388 389static struct watchdog_device iTCO_wdt_watchdog_dev = { 390 .info = &ident, 391 .ops = &iTCO_wdt_ops, 392}; 393 394/* 395 * Init & exit routines 396 */ 397 398static void iTCO_wdt_cleanup(void) 399{ 400 /* Stop the timer before we leave */ 401 if (!nowayout) 402 iTCO_wdt_stop(&iTCO_wdt_watchdog_dev); 403 404 /* Deregister */ 405 watchdog_unregister_device(&iTCO_wdt_watchdog_dev); 406 407 /* release resources */ 408 release_region(iTCO_wdt_private.tco_res->start, 409 resource_size(iTCO_wdt_private.tco_res)); 410 release_region(iTCO_wdt_private.smi_res->start, 411 resource_size(iTCO_wdt_private.smi_res)); 412 if (iTCO_wdt_private.iTCO_version >= 2) { 413 iounmap(iTCO_wdt_private.gcs_pmc); 414 release_mem_region(iTCO_wdt_private.gcs_pmc_res->start, 415 resource_size(iTCO_wdt_private.gcs_pmc_res)); 416 } 417 418 iTCO_wdt_private.tco_res = NULL; 419 iTCO_wdt_private.smi_res = NULL; 420 iTCO_wdt_private.gcs_pmc_res = NULL; 421 iTCO_wdt_private.gcs_pmc = NULL; 422} 423 424static int iTCO_wdt_probe(struct platform_device *dev) 425{ 426 int ret = -ENODEV; 427 unsigned long val32; 428 struct itco_wdt_platform_data *pdata = dev_get_platdata(&dev->dev); 429 430 if (!pdata) 431 goto out; 432 433 spin_lock_init(&iTCO_wdt_private.io_lock); 434 435 iTCO_wdt_private.tco_res = 436 platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO); 437 if (!iTCO_wdt_private.tco_res) 438 goto out; 439 440 iTCO_wdt_private.smi_res = 441 platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI); 442 if (!iTCO_wdt_private.smi_res) 443 goto out; 444 445 iTCO_wdt_private.iTCO_version = pdata->version; 446 iTCO_wdt_private.dev = dev; 447 iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent); 448 449 /* 450 * Get the Memory-Mapped GCS or PMC register, we need it for the 451 * NO_REBOOT flag (TCO v2 and v3). 452 */ 453 if (iTCO_wdt_private.iTCO_version >= 2) { 454 iTCO_wdt_private.gcs_pmc_res = platform_get_resource(dev, 455 IORESOURCE_MEM, 456 ICH_RES_MEM_GCS_PMC); 457 458 if (!iTCO_wdt_private.gcs_pmc_res) 459 goto out; 460 461 if (!request_mem_region(iTCO_wdt_private.gcs_pmc_res->start, 462 resource_size(iTCO_wdt_private.gcs_pmc_res), dev->name)) { 463 ret = -EBUSY; 464 goto out; 465 } 466 iTCO_wdt_private.gcs_pmc = ioremap(iTCO_wdt_private.gcs_pmc_res->start, 467 resource_size(iTCO_wdt_private.gcs_pmc_res)); 468 if (!iTCO_wdt_private.gcs_pmc) { 469 ret = -EIO; 470 goto unreg_gcs_pmc; 471 } 472 } 473 474 /* Check chipset's NO_REBOOT bit */ 475 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) { 476 pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n"); 477 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */ 478 goto unmap_gcs_pmc; 479 } 480 481 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ 482 iTCO_wdt_set_NO_REBOOT_bit(); 483 484 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */ 485 if (!request_region(iTCO_wdt_private.smi_res->start, 486 resource_size(iTCO_wdt_private.smi_res), dev->name)) { 487 pr_err("I/O address 0x%04llx already in use, device disabled\n", 488 (u64)SMI_EN); 489 ret = -EBUSY; 490 goto unmap_gcs_pmc; 491 } 492 if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) { 493 /* 494 * Bit 13: TCO_EN -> 0 495 * Disables TCO logic generating an SMI# 496 */ 497 val32 = inl(SMI_EN); 498 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ 499 outl(val32, SMI_EN); 500 } 501 502 if (!request_region(iTCO_wdt_private.tco_res->start, 503 resource_size(iTCO_wdt_private.tco_res), dev->name)) { 504 pr_err("I/O address 0x%04llx already in use, device disabled\n", 505 (u64)TCOBASE); 506 ret = -EBUSY; 507 goto unreg_smi; 508 } 509 510 pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n", 511 pdata->name, pdata->version, (u64)TCOBASE); 512 513 /* Clear out the (probably old) status */ 514 switch (iTCO_wdt_private.iTCO_version) { 515 case 4: 516 outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */ 517 outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */ 518 break; 519 case 3: 520 outl(0x20008, TCO1_STS); 521 break; 522 case 2: 523 case 1: 524 default: 525 outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */ 526 outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */ 527 outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */ 528 break; 529 } 530 531 iTCO_wdt_watchdog_dev.bootstatus = 0; 532 iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT; 533 watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout); 534 iTCO_wdt_watchdog_dev.parent = &dev->dev; 535 536 /* Make sure the watchdog is not running */ 537 iTCO_wdt_stop(&iTCO_wdt_watchdog_dev); 538 539 /* Check that the heartbeat value is within it's range; 540 if not reset to the default */ 541 if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) { 542 iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT); 543 pr_info("timeout value out of range, using %d\n", 544 WATCHDOG_TIMEOUT); 545 } 546 547 ret = watchdog_register_device(&iTCO_wdt_watchdog_dev); 548 if (ret != 0) { 549 pr_err("cannot register watchdog device (err=%d)\n", ret); 550 goto unreg_tco; 551 } 552 553 pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n", 554 heartbeat, nowayout); 555 556 return 0; 557 558unreg_tco: 559 release_region(iTCO_wdt_private.tco_res->start, 560 resource_size(iTCO_wdt_private.tco_res)); 561unreg_smi: 562 release_region(iTCO_wdt_private.smi_res->start, 563 resource_size(iTCO_wdt_private.smi_res)); 564unmap_gcs_pmc: 565 if (iTCO_wdt_private.iTCO_version >= 2) 566 iounmap(iTCO_wdt_private.gcs_pmc); 567unreg_gcs_pmc: 568 if (iTCO_wdt_private.iTCO_version >= 2) 569 release_mem_region(iTCO_wdt_private.gcs_pmc_res->start, 570 resource_size(iTCO_wdt_private.gcs_pmc_res)); 571out: 572 iTCO_wdt_private.tco_res = NULL; 573 iTCO_wdt_private.smi_res = NULL; 574 iTCO_wdt_private.gcs_pmc_res = NULL; 575 iTCO_wdt_private.gcs_pmc = NULL; 576 577 return ret; 578} 579 580static int iTCO_wdt_remove(struct platform_device *dev) 581{ 582 if (iTCO_wdt_private.tco_res || iTCO_wdt_private.smi_res) 583 iTCO_wdt_cleanup(); 584 585 return 0; 586} 587 588static void iTCO_wdt_shutdown(struct platform_device *dev) 589{ 590 iTCO_wdt_stop(NULL); 591} 592 593#ifdef CONFIG_PM_SLEEP 594/* 595 * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so 596 * the watchdog cannot be pinged while in that state. In ACPI sleep states the 597 * watchdog is stopped by the platform firmware. 598 */ 599 600#ifdef CONFIG_ACPI 601static inline bool need_suspend(void) 602{ 603 return acpi_target_system_state() == ACPI_STATE_S0; 604} 605#else 606static inline bool need_suspend(void) { return true; } 607#endif 608 609static int iTCO_wdt_suspend_noirq(struct device *dev) 610{ 611 int ret = 0; 612 613 iTCO_wdt_private.suspended = false; 614 if (watchdog_active(&iTCO_wdt_watchdog_dev) && need_suspend()) { 615 ret = iTCO_wdt_stop(&iTCO_wdt_watchdog_dev); 616 if (!ret) 617 iTCO_wdt_private.suspended = true; 618 } 619 return ret; 620} 621 622static int iTCO_wdt_resume_noirq(struct device *dev) 623{ 624 if (iTCO_wdt_private.suspended) 625 iTCO_wdt_start(&iTCO_wdt_watchdog_dev); 626 627 return 0; 628} 629 630static struct dev_pm_ops iTCO_wdt_pm = { 631 .suspend_noirq = iTCO_wdt_suspend_noirq, 632 .resume_noirq = iTCO_wdt_resume_noirq, 633}; 634 635#define ITCO_WDT_PM_OPS (&iTCO_wdt_pm) 636#else 637#define ITCO_WDT_PM_OPS NULL 638#endif /* CONFIG_PM_SLEEP */ 639 640static struct platform_driver iTCO_wdt_driver = { 641 .probe = iTCO_wdt_probe, 642 .remove = iTCO_wdt_remove, 643 .shutdown = iTCO_wdt_shutdown, 644 .driver = { 645 .name = DRV_NAME, 646 .pm = ITCO_WDT_PM_OPS, 647 }, 648}; 649 650static int __init iTCO_wdt_init_module(void) 651{ 652 int err; 653 654 pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION); 655 656 err = platform_driver_register(&iTCO_wdt_driver); 657 if (err) 658 return err; 659 660 return 0; 661} 662 663static void __exit iTCO_wdt_cleanup_module(void) 664{ 665 platform_driver_unregister(&iTCO_wdt_driver); 666 pr_info("Watchdog Module Unloaded\n"); 667} 668 669module_init(iTCO_wdt_init_module); 670module_exit(iTCO_wdt_cleanup_module); 671 672MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>"); 673MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver"); 674MODULE_VERSION(DRV_VERSION); 675MODULE_LICENSE("GPL"); 676MODULE_ALIAS("platform:" DRV_NAME); 677