1/* 2 * Cadence UART driver (found in Xilinx Zynq) 3 * 4 * 2011 - 2014 (C) Xilinx Inc. 5 * 6 * This program is free software; you can redistribute it 7 * and/or modify it under the terms of the GNU General Public 8 * License as published by the Free Software Foundation; 9 * either version 2 of the License, or (at your option) any 10 * later version. 11 * 12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This 13 * still shows in the naming of this file, the kconfig symbols and some symbols 14 * in the code. 15 */ 16 17#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 18#define SUPPORT_SYSRQ 19#endif 20 21#include <linux/platform_device.h> 22#include <linux/serial.h> 23#include <linux/console.h> 24#include <linux/serial_core.h> 25#include <linux/slab.h> 26#include <linux/tty.h> 27#include <linux/tty_flip.h> 28#include <linux/clk.h> 29#include <linux/irq.h> 30#include <linux/io.h> 31#include <linux/of.h> 32#include <linux/module.h> 33 34#define CDNS_UART_TTY_NAME "ttyPS" 35#define CDNS_UART_NAME "xuartps" 36#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */ 37#define CDNS_UART_MINOR 0 /* works best with devtmpfs */ 38#define CDNS_UART_NR_PORTS 2 39#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ 40#define CDNS_UART_REGISTER_SPACE 0x1000 41 42/* Rx Trigger level */ 43static int rx_trigger_level = 56; 44module_param(rx_trigger_level, uint, S_IRUGO); 45MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); 46 47/* Rx Timeout */ 48static int rx_timeout = 10; 49module_param(rx_timeout, uint, S_IRUGO); 50MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); 51 52/* Register offsets for the UART. */ 53#define CDNS_UART_CR_OFFSET 0x00 /* Control Register */ 54#define CDNS_UART_MR_OFFSET 0x04 /* Mode Register */ 55#define CDNS_UART_IER_OFFSET 0x08 /* Interrupt Enable */ 56#define CDNS_UART_IDR_OFFSET 0x0C /* Interrupt Disable */ 57#define CDNS_UART_IMR_OFFSET 0x10 /* Interrupt Mask */ 58#define CDNS_UART_ISR_OFFSET 0x14 /* Interrupt Status */ 59#define CDNS_UART_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator */ 60#define CDNS_UART_RXTOUT_OFFSET 0x1C /* RX Timeout */ 61#define CDNS_UART_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level */ 62#define CDNS_UART_MODEMCR_OFFSET 0x24 /* Modem Control */ 63#define CDNS_UART_MODEMSR_OFFSET 0x28 /* Modem Status */ 64#define CDNS_UART_SR_OFFSET 0x2C /* Channel Status */ 65#define CDNS_UART_FIFO_OFFSET 0x30 /* FIFO */ 66#define CDNS_UART_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider */ 67#define CDNS_UART_FLOWDEL_OFFSET 0x38 /* Flow Delay */ 68#define CDNS_UART_IRRX_PWIDTH_OFFSET 0x3C /* IR Min Received Pulse Width */ 69#define CDNS_UART_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse Width */ 70#define CDNS_UART_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level */ 71 72/* Control Register Bit Definitions */ 73#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */ 74#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */ 75#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */ 76#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */ 77#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */ 78#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */ 79#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */ 80#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */ 81#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ 82 83/* 84 * Mode Register: 85 * The mode register (MR) defines the mode of transfer as well as the data 86 * format. If this register is modified during transmission or reception, 87 * data validity cannot be guaranteed. 88 */ 89#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ 90#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ 91#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ 92 93#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ 94#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ 95 96#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ 97#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ 98#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ 99#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ 100#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ 101 102#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ 103#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ 104#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ 105 106/* 107 * Interrupt Registers: 108 * Interrupt control logic uses the interrupt enable register (IER) and the 109 * interrupt disable register (IDR) to set the value of the bits in the 110 * interrupt mask register (IMR). The IMR determines whether to pass an 111 * interrupt to the interrupt status register (ISR). 112 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an 113 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 114 * Reading either IER or IDR returns 0x00. 115 * All four registers have the same bit definitions. 116 */ 117#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ 118#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */ 119#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ 120#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ 121#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ 122#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ 123#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ 124#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ 125#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ 126#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ 127#define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */ 128 129/* Goes in read_status_mask for break detection as the HW doesn't do it*/ 130#define CDNS_UART_IXR_BRK 0x80000000 131 132/* 133 * Modem Control register: 134 * The read/write Modem Control register controls the interface with the modem 135 * or data set, or a peripheral device emulating a modem. 136 */ 137#define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */ 138#define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */ 139#define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */ 140 141/* 142 * Channel Status Register: 143 * The channel status register (CSR) is provided to enable the control logic 144 * to monitor the status of bits in the channel interrupt status register, 145 * even if these are masked out by the interrupt mask register. 146 */ 147#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ 148#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ 149#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ 150#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */ 151 152/* baud dividers min/max values */ 153#define CDNS_UART_BDIV_MIN 4 154#define CDNS_UART_BDIV_MAX 255 155#define CDNS_UART_CD_MAX 65535 156 157/** 158 * struct cdns_uart - device data 159 * @port: Pointer to the UART port 160 * @uartclk: Reference clock 161 * @pclk: APB clock 162 * @baud: Current baud rate 163 * @clk_rate_change_nb: Notifier block for clock changes 164 */ 165struct cdns_uart { 166 struct uart_port *port; 167 struct clk *uartclk; 168 struct clk *pclk; 169 unsigned int baud; 170 struct notifier_block clk_rate_change_nb; 171}; 172#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \ 173 clk_rate_change_nb); 174 175/** 176 * cdns_uart_isr - Interrupt handler 177 * @irq: Irq number 178 * @dev_id: Id of the port 179 * 180 * Return: IRQHANDLED 181 */ 182static irqreturn_t cdns_uart_isr(int irq, void *dev_id) 183{ 184 struct uart_port *port = (struct uart_port *)dev_id; 185 unsigned long flags; 186 unsigned int isrstatus, numbytes; 187 unsigned int data; 188 char status = TTY_NORMAL; 189 190 spin_lock_irqsave(&port->lock, flags); 191 192 /* Read the interrupt status register to determine which 193 * interrupt(s) is/are active. 194 */ 195 isrstatus = readl(port->membase + CDNS_UART_ISR_OFFSET); 196 197 /* 198 * There is no hardware break detection, so we interpret framing 199 * error with all-zeros data as a break sequence. Most of the time, 200 * there's another non-zero byte at the end of the sequence. 201 */ 202 if (isrstatus & CDNS_UART_IXR_FRAMING) { 203 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & 204 CDNS_UART_SR_RXEMPTY)) { 205 if (!readl(port->membase + CDNS_UART_FIFO_OFFSET)) { 206 port->read_status_mask |= CDNS_UART_IXR_BRK; 207 isrstatus &= ~CDNS_UART_IXR_FRAMING; 208 } 209 } 210 writel(CDNS_UART_IXR_FRAMING, 211 port->membase + CDNS_UART_ISR_OFFSET); 212 } 213 214 /* drop byte with parity error if IGNPAR specified */ 215 if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY) 216 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT); 217 218 isrstatus &= port->read_status_mask; 219 isrstatus &= ~port->ignore_status_mask; 220 221 if ((isrstatus & CDNS_UART_IXR_TOUT) || 222 (isrstatus & CDNS_UART_IXR_RXTRIG)) { 223 /* Receive Timeout Interrupt */ 224 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & 225 CDNS_UART_SR_RXEMPTY)) { 226 data = readl(port->membase + CDNS_UART_FIFO_OFFSET); 227 228 /* Non-NULL byte after BREAK is garbage (99%) */ 229 if (data && (port->read_status_mask & 230 CDNS_UART_IXR_BRK)) { 231 port->read_status_mask &= ~CDNS_UART_IXR_BRK; 232 port->icount.brk++; 233 if (uart_handle_break(port)) 234 continue; 235 } 236 237#ifdef SUPPORT_SYSRQ 238 /* 239 * uart_handle_sysrq_char() doesn't work if 240 * spinlocked, for some reason 241 */ 242 if (port->sysrq) { 243 spin_unlock(&port->lock); 244 if (uart_handle_sysrq_char(port, 245 (unsigned char)data)) { 246 spin_lock(&port->lock); 247 continue; 248 } 249 spin_lock(&port->lock); 250 } 251#endif 252 253 port->icount.rx++; 254 255 if (isrstatus & CDNS_UART_IXR_PARITY) { 256 port->icount.parity++; 257 status = TTY_PARITY; 258 } else if (isrstatus & CDNS_UART_IXR_FRAMING) { 259 port->icount.frame++; 260 status = TTY_FRAME; 261 } else if (isrstatus & CDNS_UART_IXR_OVERRUN) { 262 port->icount.overrun++; 263 } 264 265 uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN, 266 data, status); 267 } 268 spin_unlock(&port->lock); 269 tty_flip_buffer_push(&port->state->port); 270 spin_lock(&port->lock); 271 } 272 273 /* Dispatch an appropriate handler */ 274 if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) { 275 if (uart_circ_empty(&port->state->xmit)) { 276 writel(CDNS_UART_IXR_TXEMPTY, 277 port->membase + CDNS_UART_IDR_OFFSET); 278 } else { 279 numbytes = port->fifosize; 280 /* Break if no more data available in the UART buffer */ 281 while (numbytes--) { 282 if (uart_circ_empty(&port->state->xmit)) 283 break; 284 /* Get the data from the UART circular buffer 285 * and write it to the cdns_uart's TX_FIFO 286 * register. 287 */ 288 writel(port->state->xmit.buf[ 289 port->state->xmit.tail], 290 port->membase + CDNS_UART_FIFO_OFFSET); 291 292 port->icount.tx++; 293 294 /* Adjust the tail of the UART buffer and wrap 295 * the buffer if it reaches limit. 296 */ 297 port->state->xmit.tail = 298 (port->state->xmit.tail + 1) & 299 (UART_XMIT_SIZE - 1); 300 } 301 302 if (uart_circ_chars_pending( 303 &port->state->xmit) < WAKEUP_CHARS) 304 uart_write_wakeup(port); 305 } 306 } 307 308 writel(isrstatus, port->membase + CDNS_UART_ISR_OFFSET); 309 310 /* be sure to release the lock and tty before leaving */ 311 spin_unlock_irqrestore(&port->lock, flags); 312 313 return IRQ_HANDLED; 314} 315 316/** 317 * cdns_uart_calc_baud_divs - Calculate baud rate divisors 318 * @clk: UART module input clock 319 * @baud: Desired baud rate 320 * @rbdiv: BDIV value (return value) 321 * @rcd: CD value (return value) 322 * @div8: Value for clk_sel bit in mod (return value) 323 * Return: baud rate, requested baud when possible, or actual baud when there 324 * was too much error, zero if no valid divisors are found. 325 * 326 * Formula to obtain baud rate is 327 * baud_tx/rx rate = clk/CD * (BDIV + 1) 328 * input_clk = (Uart User Defined Clock or Apb Clock) 329 * depends on UCLKEN in MR Reg 330 * clk = input_clk or input_clk/8; 331 * depends on CLKS in MR reg 332 * CD and BDIV depends on values in 333 * baud rate generate register 334 * baud rate clock divisor register 335 */ 336static unsigned int cdns_uart_calc_baud_divs(unsigned int clk, 337 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8) 338{ 339 u32 cd, bdiv; 340 unsigned int calc_baud; 341 unsigned int bestbaud = 0; 342 unsigned int bauderror; 343 unsigned int besterror = ~0; 344 345 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) { 346 *div8 = 1; 347 clk /= 8; 348 } else { 349 *div8 = 0; 350 } 351 352 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) { 353 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); 354 if (cd < 1 || cd > CDNS_UART_CD_MAX) 355 continue; 356 357 calc_baud = clk / (cd * (bdiv + 1)); 358 359 if (baud > calc_baud) 360 bauderror = baud - calc_baud; 361 else 362 bauderror = calc_baud - baud; 363 364 if (besterror > bauderror) { 365 *rbdiv = bdiv; 366 *rcd = cd; 367 bestbaud = calc_baud; 368 besterror = bauderror; 369 } 370 } 371 /* use the values when percent error is acceptable */ 372 if (((besterror * 100) / baud) < 3) 373 bestbaud = baud; 374 375 return bestbaud; 376} 377 378/** 379 * cdns_uart_set_baud_rate - Calculate and set the baud rate 380 * @port: Handle to the uart port structure 381 * @baud: Baud rate to set 382 * Return: baud rate, requested baud when possible, or actual baud when there 383 * was too much error, zero if no valid divisors are found. 384 */ 385static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, 386 unsigned int baud) 387{ 388 unsigned int calc_baud; 389 u32 cd = 0, bdiv = 0; 390 u32 mreg; 391 int div8; 392 struct cdns_uart *cdns_uart = port->private_data; 393 394 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, 395 &div8); 396 397 /* Write new divisors to hardware */ 398 mreg = readl(port->membase + CDNS_UART_MR_OFFSET); 399 if (div8) 400 mreg |= CDNS_UART_MR_CLKSEL; 401 else 402 mreg &= ~CDNS_UART_MR_CLKSEL; 403 writel(mreg, port->membase + CDNS_UART_MR_OFFSET); 404 writel(cd, port->membase + CDNS_UART_BAUDGEN_OFFSET); 405 writel(bdiv, port->membase + CDNS_UART_BAUDDIV_OFFSET); 406 cdns_uart->baud = baud; 407 408 return calc_baud; 409} 410 411#ifdef CONFIG_COMMON_CLK 412/** 413 * cdns_uart_clk_notitifer_cb - Clock notifier callback 414 * @nb: Notifier block 415 * @event: Notify event 416 * @data: Notifier data 417 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. 418 */ 419static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, 420 unsigned long event, void *data) 421{ 422 u32 ctrl_reg; 423 struct uart_port *port; 424 int locked = 0; 425 struct clk_notifier_data *ndata = data; 426 unsigned long flags = 0; 427 struct cdns_uart *cdns_uart = to_cdns_uart(nb); 428 429 port = cdns_uart->port; 430 if (port->suspended) 431 return NOTIFY_OK; 432 433 switch (event) { 434 case PRE_RATE_CHANGE: 435 { 436 u32 bdiv, cd; 437 int div8; 438 439 /* 440 * Find out if current baud-rate can be achieved with new clock 441 * frequency. 442 */ 443 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud, 444 &bdiv, &cd, &div8)) { 445 dev_warn(port->dev, "clock rate change rejected\n"); 446 return NOTIFY_BAD; 447 } 448 449 spin_lock_irqsave(&cdns_uart->port->lock, flags); 450 451 /* Disable the TX and RX to set baud rate */ 452 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); 453 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 454 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); 455 456 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 457 458 return NOTIFY_OK; 459 } 460 case POST_RATE_CHANGE: 461 /* 462 * Set clk dividers to generate correct baud with new clock 463 * frequency. 464 */ 465 466 spin_lock_irqsave(&cdns_uart->port->lock, flags); 467 468 locked = 1; 469 port->uartclk = ndata->new_rate; 470 471 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port, 472 cdns_uart->baud); 473 /* fall through */ 474 case ABORT_RATE_CHANGE: 475 if (!locked) 476 spin_lock_irqsave(&cdns_uart->port->lock, flags); 477 478 /* Set TX/RX Reset */ 479 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); 480 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 481 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); 482 483 while (readl(port->membase + CDNS_UART_CR_OFFSET) & 484 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 485 cpu_relax(); 486 487 /* 488 * Clear the RX disable and TX disable bits and then set the TX 489 * enable bit and RX enable bit to enable the transmitter and 490 * receiver. 491 */ 492 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); 493 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); 494 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 495 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 496 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); 497 498 spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 499 500 return NOTIFY_OK; 501 default: 502 return NOTIFY_DONE; 503 } 504} 505#endif 506 507/** 508 * cdns_uart_start_tx - Start transmitting bytes 509 * @port: Handle to the uart port structure 510 */ 511static void cdns_uart_start_tx(struct uart_port *port) 512{ 513 unsigned int status, numbytes = port->fifosize; 514 515 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port)) 516 return; 517 518 status = readl(port->membase + CDNS_UART_CR_OFFSET); 519 /* Set the TX enable bit and clear the TX disable bit to enable the 520 * transmitter. 521 */ 522 writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN, 523 port->membase + CDNS_UART_CR_OFFSET); 524 525 while (numbytes-- && ((readl(port->membase + CDNS_UART_SR_OFFSET) & 526 CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) { 527 /* Break if no more data available in the UART buffer */ 528 if (uart_circ_empty(&port->state->xmit)) 529 break; 530 531 /* Get the data from the UART circular buffer and 532 * write it to the cdns_uart's TX_FIFO register. 533 */ 534 writel(port->state->xmit.buf[port->state->xmit.tail], 535 port->membase + CDNS_UART_FIFO_OFFSET); 536 port->icount.tx++; 537 538 /* Adjust the tail of the UART buffer and wrap 539 * the buffer if it reaches limit. 540 */ 541 port->state->xmit.tail = (port->state->xmit.tail + 1) & 542 (UART_XMIT_SIZE - 1); 543 } 544 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR_OFFSET); 545 /* Enable the TX Empty interrupt */ 546 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER_OFFSET); 547 548 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) 549 uart_write_wakeup(port); 550} 551 552/** 553 * cdns_uart_stop_tx - Stop TX 554 * @port: Handle to the uart port structure 555 */ 556static void cdns_uart_stop_tx(struct uart_port *port) 557{ 558 unsigned int regval; 559 560 regval = readl(port->membase + CDNS_UART_CR_OFFSET); 561 regval |= CDNS_UART_CR_TX_DIS; 562 /* Disable the transmitter */ 563 writel(regval, port->membase + CDNS_UART_CR_OFFSET); 564} 565 566/** 567 * cdns_uart_stop_rx - Stop RX 568 * @port: Handle to the uart port structure 569 */ 570static void cdns_uart_stop_rx(struct uart_port *port) 571{ 572 unsigned int regval; 573 574 regval = readl(port->membase + CDNS_UART_CR_OFFSET); 575 regval |= CDNS_UART_CR_RX_DIS; 576 /* Disable the receiver */ 577 writel(regval, port->membase + CDNS_UART_CR_OFFSET); 578} 579 580/** 581 * cdns_uart_tx_empty - Check whether TX is empty 582 * @port: Handle to the uart port structure 583 * 584 * Return: TIOCSER_TEMT on success, 0 otherwise 585 */ 586static unsigned int cdns_uart_tx_empty(struct uart_port *port) 587{ 588 unsigned int status; 589 590 status = readl(port->membase + CDNS_UART_SR_OFFSET) & 591 CDNS_UART_SR_TXEMPTY; 592 return status ? TIOCSER_TEMT : 0; 593} 594 595/** 596 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop 597 * transmitting char breaks 598 * @port: Handle to the uart port structure 599 * @ctl: Value based on which start or stop decision is taken 600 */ 601static void cdns_uart_break_ctl(struct uart_port *port, int ctl) 602{ 603 unsigned int status; 604 unsigned long flags; 605 606 spin_lock_irqsave(&port->lock, flags); 607 608 status = readl(port->membase + CDNS_UART_CR_OFFSET); 609 610 if (ctl == -1) 611 writel(CDNS_UART_CR_STARTBRK | status, 612 port->membase + CDNS_UART_CR_OFFSET); 613 else { 614 if ((status & CDNS_UART_CR_STOPBRK) == 0) 615 writel(CDNS_UART_CR_STOPBRK | status, 616 port->membase + CDNS_UART_CR_OFFSET); 617 } 618 spin_unlock_irqrestore(&port->lock, flags); 619} 620 621/** 622 * cdns_uart_set_termios - termios operations, handling data length, parity, 623 * stop bits, flow control, baud rate 624 * @port: Handle to the uart port structure 625 * @termios: Handle to the input termios structure 626 * @old: Values of the previously saved termios structure 627 */ 628static void cdns_uart_set_termios(struct uart_port *port, 629 struct ktermios *termios, struct ktermios *old) 630{ 631 unsigned int cval = 0; 632 unsigned int baud, minbaud, maxbaud; 633 unsigned long flags; 634 unsigned int ctrl_reg, mode_reg; 635 636 spin_lock_irqsave(&port->lock, flags); 637 638 /* Wait for the transmit FIFO to empty before making changes */ 639 if (!(readl(port->membase + CDNS_UART_CR_OFFSET) & 640 CDNS_UART_CR_TX_DIS)) { 641 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & 642 CDNS_UART_SR_TXEMPTY)) { 643 cpu_relax(); 644 } 645 } 646 647 /* Disable the TX and RX to set baud rate */ 648 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); 649 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 650 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); 651 652 /* 653 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk 654 * min and max baud should be calculated here based on port->uartclk. 655 * this way we get a valid baud and can safely call set_baud() 656 */ 657 minbaud = port->uartclk / 658 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8); 659 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1); 660 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); 661 baud = cdns_uart_set_baud_rate(port, baud); 662 if (tty_termios_baud_rate(termios)) 663 tty_termios_encode_baud_rate(termios, baud, baud); 664 665 /* Update the per-port timeout. */ 666 uart_update_timeout(port, termios->c_cflag, baud); 667 668 /* Set TX/RX Reset */ 669 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); 670 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 671 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); 672 673 /* 674 * Clear the RX disable and TX disable bits and then set the TX enable 675 * bit and RX enable bit to enable the transmitter and receiver. 676 */ 677 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); 678 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 679 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 680 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); 681 682 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); 683 684 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | 685 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; 686 port->ignore_status_mask = 0; 687 688 if (termios->c_iflag & INPCK) 689 port->read_status_mask |= CDNS_UART_IXR_PARITY | 690 CDNS_UART_IXR_FRAMING; 691 692 if (termios->c_iflag & IGNPAR) 693 port->ignore_status_mask |= CDNS_UART_IXR_PARITY | 694 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 695 696 /* ignore all characters if CREAD is not set */ 697 if ((termios->c_cflag & CREAD) == 0) 698 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG | 699 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | 700 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; 701 702 mode_reg = readl(port->membase + CDNS_UART_MR_OFFSET); 703 704 /* Handling Data Size */ 705 switch (termios->c_cflag & CSIZE) { 706 case CS6: 707 cval |= CDNS_UART_MR_CHARLEN_6_BIT; 708 break; 709 case CS7: 710 cval |= CDNS_UART_MR_CHARLEN_7_BIT; 711 break; 712 default: 713 case CS8: 714 cval |= CDNS_UART_MR_CHARLEN_8_BIT; 715 termios->c_cflag &= ~CSIZE; 716 termios->c_cflag |= CS8; 717 break; 718 } 719 720 /* Handling Parity and Stop Bits length */ 721 if (termios->c_cflag & CSTOPB) 722 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */ 723 else 724 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */ 725 726 if (termios->c_cflag & PARENB) { 727 /* Mark or Space parity */ 728 if (termios->c_cflag & CMSPAR) { 729 if (termios->c_cflag & PARODD) 730 cval |= CDNS_UART_MR_PARITY_MARK; 731 else 732 cval |= CDNS_UART_MR_PARITY_SPACE; 733 } else { 734 if (termios->c_cflag & PARODD) 735 cval |= CDNS_UART_MR_PARITY_ODD; 736 else 737 cval |= CDNS_UART_MR_PARITY_EVEN; 738 } 739 } else { 740 cval |= CDNS_UART_MR_PARITY_NONE; 741 } 742 cval |= mode_reg & 1; 743 writel(cval, port->membase + CDNS_UART_MR_OFFSET); 744 745 spin_unlock_irqrestore(&port->lock, flags); 746} 747 748/** 749 * cdns_uart_startup - Called when an application opens a cdns_uart port 750 * @port: Handle to the uart port structure 751 * 752 * Return: 0 on success, negative errno otherwise 753 */ 754static int cdns_uart_startup(struct uart_port *port) 755{ 756 unsigned int retval = 0, status = 0; 757 758 retval = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, 759 (void *)port); 760 if (retval) 761 return retval; 762 763 /* Disable the TX and RX */ 764 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 765 port->membase + CDNS_UART_CR_OFFSET); 766 767 /* Set the Control Register with TX/RX Enable, TX/RX Reset, 768 * no break chars. 769 */ 770 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, 771 port->membase + CDNS_UART_CR_OFFSET); 772 773 status = readl(port->membase + CDNS_UART_CR_OFFSET); 774 775 /* Clear the RX disable and TX disable bits and then set the TX enable 776 * bit and RX enable bit to enable the transmitter and receiver. 777 */ 778 writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS)) 779 | (CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN | 780 CDNS_UART_CR_STOPBRK), 781 port->membase + CDNS_UART_CR_OFFSET); 782 783 /* Set the Mode Register with normal mode,8 data bits,1 stop bit, 784 * no parity. 785 */ 786 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT 787 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, 788 port->membase + CDNS_UART_MR_OFFSET); 789 790 /* 791 * Set the RX FIFO Trigger level to use most of the FIFO, but it 792 * can be tuned with a module parameter 793 */ 794 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM_OFFSET); 795 796 /* 797 * Receive Timeout register is enabled but it 798 * can be tuned with a module parameter 799 */ 800 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); 801 802 /* Clear out any pending interrupts before enabling them */ 803 writel(readl(port->membase + CDNS_UART_ISR_OFFSET), 804 port->membase + CDNS_UART_ISR_OFFSET); 805 806 /* Set the Interrupt Registers with desired interrupts */ 807 writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY | 808 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN | 809 CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT, 810 port->membase + CDNS_UART_IER_OFFSET); 811 812 return retval; 813} 814 815/** 816 * cdns_uart_shutdown - Called when an application closes a cdns_uart port 817 * @port: Handle to the uart port structure 818 */ 819static void cdns_uart_shutdown(struct uart_port *port) 820{ 821 int status; 822 823 /* Disable interrupts */ 824 status = readl(port->membase + CDNS_UART_IMR_OFFSET); 825 writel(status, port->membase + CDNS_UART_IDR_OFFSET); 826 827 /* Disable the TX and RX */ 828 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 829 port->membase + CDNS_UART_CR_OFFSET); 830 free_irq(port->irq, port); 831} 832 833/** 834 * cdns_uart_type - Set UART type to cdns_uart port 835 * @port: Handle to the uart port structure 836 * 837 * Return: string on success, NULL otherwise 838 */ 839static const char *cdns_uart_type(struct uart_port *port) 840{ 841 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL; 842} 843 844/** 845 * cdns_uart_verify_port - Verify the port params 846 * @port: Handle to the uart port structure 847 * @ser: Handle to the structure whose members are compared 848 * 849 * Return: 0 on success, negative errno otherwise. 850 */ 851static int cdns_uart_verify_port(struct uart_port *port, 852 struct serial_struct *ser) 853{ 854 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) 855 return -EINVAL; 856 if (port->irq != ser->irq) 857 return -EINVAL; 858 if (ser->io_type != UPIO_MEM) 859 return -EINVAL; 860 if (port->iobase != ser->port) 861 return -EINVAL; 862 if (ser->hub6 != 0) 863 return -EINVAL; 864 return 0; 865} 866 867/** 868 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port, 869 * called when the driver adds a cdns_uart port via 870 * uart_add_one_port() 871 * @port: Handle to the uart port structure 872 * 873 * Return: 0 on success, negative errno otherwise. 874 */ 875static int cdns_uart_request_port(struct uart_port *port) 876{ 877 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE, 878 CDNS_UART_NAME)) { 879 return -ENOMEM; 880 } 881 882 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); 883 if (!port->membase) { 884 dev_err(port->dev, "Unable to map registers\n"); 885 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 886 return -ENOMEM; 887 } 888 return 0; 889} 890 891/** 892 * cdns_uart_release_port - Release UART port 893 * @port: Handle to the uart port structure 894 * 895 * Release the memory region attached to a cdns_uart port. Called when the 896 * driver removes a cdns_uart port via uart_remove_one_port(). 897 */ 898static void cdns_uart_release_port(struct uart_port *port) 899{ 900 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); 901 iounmap(port->membase); 902 port->membase = NULL; 903} 904 905/** 906 * cdns_uart_config_port - Configure UART port 907 * @port: Handle to the uart port structure 908 * @flags: If any 909 */ 910static void cdns_uart_config_port(struct uart_port *port, int flags) 911{ 912 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0) 913 port->type = PORT_XUARTPS; 914} 915 916/** 917 * cdns_uart_get_mctrl - Get the modem control state 918 * @port: Handle to the uart port structure 919 * 920 * Return: the modem control state 921 */ 922static unsigned int cdns_uart_get_mctrl(struct uart_port *port) 923{ 924 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 925} 926 927static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 928{ 929 u32 val; 930 931 val = readl(port->membase + CDNS_UART_MODEMCR_OFFSET); 932 933 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); 934 935 if (mctrl & TIOCM_RTS) 936 val |= CDNS_UART_MODEMCR_RTS; 937 if (mctrl & TIOCM_DTR) 938 val |= CDNS_UART_MODEMCR_DTR; 939 940 writel(val, port->membase + CDNS_UART_MODEMCR_OFFSET); 941} 942 943#ifdef CONFIG_CONSOLE_POLL 944static int cdns_uart_poll_get_char(struct uart_port *port) 945{ 946 u32 imr; 947 int c; 948 949 /* Disable all interrupts */ 950 imr = readl(port->membase + CDNS_UART_IMR_OFFSET); 951 writel(imr, port->membase + CDNS_UART_IDR_OFFSET); 952 953 /* Check if FIFO is empty */ 954 if (readl(port->membase + CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY) 955 c = NO_POLL_CHAR; 956 else /* Read a character */ 957 c = (unsigned char) readl( 958 port->membase + CDNS_UART_FIFO_OFFSET); 959 960 /* Enable interrupts */ 961 writel(imr, port->membase + CDNS_UART_IER_OFFSET); 962 963 return c; 964} 965 966static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) 967{ 968 u32 imr; 969 970 /* Disable all interrupts */ 971 imr = readl(port->membase + CDNS_UART_IMR_OFFSET); 972 writel(imr, port->membase + CDNS_UART_IDR_OFFSET); 973 974 /* Wait until FIFO is empty */ 975 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & 976 CDNS_UART_SR_TXEMPTY)) 977 cpu_relax(); 978 979 /* Write a character */ 980 writel(c, port->membase + CDNS_UART_FIFO_OFFSET); 981 982 /* Wait until FIFO is empty */ 983 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & 984 CDNS_UART_SR_TXEMPTY)) 985 cpu_relax(); 986 987 /* Enable interrupts */ 988 writel(imr, port->membase + CDNS_UART_IER_OFFSET); 989 990 return; 991} 992#endif 993 994static struct uart_ops cdns_uart_ops = { 995 .set_mctrl = cdns_uart_set_mctrl, 996 .get_mctrl = cdns_uart_get_mctrl, 997 .start_tx = cdns_uart_start_tx, 998 .stop_tx = cdns_uart_stop_tx, 999 .stop_rx = cdns_uart_stop_rx, 1000 .tx_empty = cdns_uart_tx_empty, 1001 .break_ctl = cdns_uart_break_ctl, 1002 .set_termios = cdns_uart_set_termios, 1003 .startup = cdns_uart_startup, 1004 .shutdown = cdns_uart_shutdown, 1005 .type = cdns_uart_type, 1006 .verify_port = cdns_uart_verify_port, 1007 .request_port = cdns_uart_request_port, 1008 .release_port = cdns_uart_release_port, 1009 .config_port = cdns_uart_config_port, 1010#ifdef CONFIG_CONSOLE_POLL 1011 .poll_get_char = cdns_uart_poll_get_char, 1012 .poll_put_char = cdns_uart_poll_put_char, 1013#endif 1014}; 1015 1016static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS]; 1017 1018/** 1019 * cdns_uart_get_port - Configure the port from platform device resource info 1020 * @id: Port id 1021 * 1022 * Return: a pointer to a uart_port or NULL for failure 1023 */ 1024static struct uart_port *cdns_uart_get_port(int id) 1025{ 1026 struct uart_port *port; 1027 1028 /* Try the given port id if failed use default method */ 1029 if (cdns_uart_port[id].mapbase != 0) { 1030 /* Find the next unused port */ 1031 for (id = 0; id < CDNS_UART_NR_PORTS; id++) 1032 if (cdns_uart_port[id].mapbase == 0) 1033 break; 1034 } 1035 1036 if (id >= CDNS_UART_NR_PORTS) 1037 return NULL; 1038 1039 port = &cdns_uart_port[id]; 1040 1041 /* At this point, we've got an empty uart_port struct, initialize it */ 1042 spin_lock_init(&port->lock); 1043 port->membase = NULL; 1044 port->irq = 0; 1045 port->type = PORT_UNKNOWN; 1046 port->iotype = UPIO_MEM32; 1047 port->flags = UPF_BOOT_AUTOCONF; 1048 port->ops = &cdns_uart_ops; 1049 port->fifosize = CDNS_UART_FIFO_SIZE; 1050 port->line = id; 1051 port->dev = NULL; 1052 return port; 1053} 1054 1055#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1056/** 1057 * cdns_uart_console_wait_tx - Wait for the TX to be full 1058 * @port: Handle to the uart port structure 1059 */ 1060static void cdns_uart_console_wait_tx(struct uart_port *port) 1061{ 1062 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & 1063 CDNS_UART_SR_TXEMPTY)) 1064 barrier(); 1065} 1066 1067/** 1068 * cdns_uart_console_putchar - write the character to the FIFO buffer 1069 * @port: Handle to the uart port structure 1070 * @ch: Character to be written 1071 */ 1072static void cdns_uart_console_putchar(struct uart_port *port, int ch) 1073{ 1074 cdns_uart_console_wait_tx(port); 1075 writel(ch, port->membase + CDNS_UART_FIFO_OFFSET); 1076} 1077 1078static void __init cdns_early_write(struct console *con, const char *s, 1079 unsigned n) 1080{ 1081 struct earlycon_device *dev = con->data; 1082 1083 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar); 1084} 1085 1086static int __init cdns_early_console_setup(struct earlycon_device *device, 1087 const char *opt) 1088{ 1089 if (!device->port.membase) 1090 return -ENODEV; 1091 1092 device->con->write = cdns_early_write; 1093 1094 return 0; 1095} 1096EARLYCON_DECLARE(cdns, cdns_early_console_setup); 1097 1098/** 1099 * cdns_uart_console_write - perform write operation 1100 * @co: Console handle 1101 * @s: Pointer to character array 1102 * @count: No of characters 1103 */ 1104static void cdns_uart_console_write(struct console *co, const char *s, 1105 unsigned int count) 1106{ 1107 struct uart_port *port = &cdns_uart_port[co->index]; 1108 unsigned long flags; 1109 unsigned int imr, ctrl; 1110 int locked = 1; 1111 1112 if (oops_in_progress) 1113 locked = spin_trylock_irqsave(&port->lock, flags); 1114 else 1115 spin_lock_irqsave(&port->lock, flags); 1116 1117 /* save and disable interrupt */ 1118 imr = readl(port->membase + CDNS_UART_IMR_OFFSET); 1119 writel(imr, port->membase + CDNS_UART_IDR_OFFSET); 1120 1121 /* 1122 * Make sure that the tx part is enabled. Set the TX enable bit and 1123 * clear the TX disable bit to enable the transmitter. 1124 */ 1125 ctrl = readl(port->membase + CDNS_UART_CR_OFFSET); 1126 writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN, 1127 port->membase + CDNS_UART_CR_OFFSET); 1128 1129 uart_console_write(port, s, count, cdns_uart_console_putchar); 1130 cdns_uart_console_wait_tx(port); 1131 1132 writel(ctrl, port->membase + CDNS_UART_CR_OFFSET); 1133 1134 /* restore interrupt state */ 1135 writel(imr, port->membase + CDNS_UART_IER_OFFSET); 1136 1137 if (locked) 1138 spin_unlock_irqrestore(&port->lock, flags); 1139} 1140 1141/** 1142 * cdns_uart_console_setup - Initialize the uart to default config 1143 * @co: Console handle 1144 * @options: Initial settings of uart 1145 * 1146 * Return: 0 on success, negative errno otherwise. 1147 */ 1148static int __init cdns_uart_console_setup(struct console *co, char *options) 1149{ 1150 struct uart_port *port = &cdns_uart_port[co->index]; 1151 int baud = 9600; 1152 int bits = 8; 1153 int parity = 'n'; 1154 int flow = 'n'; 1155 1156 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS) 1157 return -EINVAL; 1158 1159 if (!port->membase) { 1160 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n", 1161 co->index); 1162 return -ENODEV; 1163 } 1164 1165 if (options) 1166 uart_parse_options(options, &baud, &parity, &bits, &flow); 1167 1168 return uart_set_options(port, co, baud, parity, bits, flow); 1169} 1170 1171static struct uart_driver cdns_uart_uart_driver; 1172 1173static struct console cdns_uart_console = { 1174 .name = CDNS_UART_TTY_NAME, 1175 .write = cdns_uart_console_write, 1176 .device = uart_console_device, 1177 .setup = cdns_uart_console_setup, 1178 .flags = CON_PRINTBUFFER, 1179 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ 1180 .data = &cdns_uart_uart_driver, 1181}; 1182 1183/** 1184 * cdns_uart_console_init - Initialization call 1185 * 1186 * Return: 0 on success, negative errno otherwise 1187 */ 1188static int __init cdns_uart_console_init(void) 1189{ 1190 register_console(&cdns_uart_console); 1191 return 0; 1192} 1193 1194console_initcall(cdns_uart_console_init); 1195 1196#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ 1197 1198static struct uart_driver cdns_uart_uart_driver = { 1199 .owner = THIS_MODULE, 1200 .driver_name = CDNS_UART_NAME, 1201 .dev_name = CDNS_UART_TTY_NAME, 1202 .major = CDNS_UART_MAJOR, 1203 .minor = CDNS_UART_MINOR, 1204 .nr = CDNS_UART_NR_PORTS, 1205#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE 1206 .cons = &cdns_uart_console, 1207#endif 1208}; 1209 1210#ifdef CONFIG_PM_SLEEP 1211/** 1212 * cdns_uart_suspend - suspend event 1213 * @device: Pointer to the device structure 1214 * 1215 * Return: 0 1216 */ 1217static int cdns_uart_suspend(struct device *device) 1218{ 1219 struct uart_port *port = dev_get_drvdata(device); 1220 struct tty_struct *tty; 1221 struct device *tty_dev; 1222 int may_wake = 0; 1223 1224 /* Get the tty which could be NULL so don't assume it's valid */ 1225 tty = tty_port_tty_get(&port->state->port); 1226 if (tty) { 1227 tty_dev = tty->dev; 1228 may_wake = device_may_wakeup(tty_dev); 1229 tty_kref_put(tty); 1230 } 1231 1232 /* 1233 * Call the API provided in serial_core.c file which handles 1234 * the suspend. 1235 */ 1236 uart_suspend_port(&cdns_uart_uart_driver, port); 1237 if (console_suspend_enabled && !may_wake) { 1238 struct cdns_uart *cdns_uart = port->private_data; 1239 1240 clk_disable(cdns_uart->uartclk); 1241 clk_disable(cdns_uart->pclk); 1242 } else { 1243 unsigned long flags = 0; 1244 1245 spin_lock_irqsave(&port->lock, flags); 1246 /* Empty the receive FIFO 1st before making changes */ 1247 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & 1248 CDNS_UART_SR_RXEMPTY)) 1249 readl(port->membase + CDNS_UART_FIFO_OFFSET); 1250 /* set RX trigger level to 1 */ 1251 writel(1, port->membase + CDNS_UART_RXWM_OFFSET); 1252 /* disable RX timeout interrups */ 1253 writel(CDNS_UART_IXR_TOUT, 1254 port->membase + CDNS_UART_IDR_OFFSET); 1255 spin_unlock_irqrestore(&port->lock, flags); 1256 } 1257 1258 return 0; 1259} 1260 1261/** 1262 * cdns_uart_resume - Resume after a previous suspend 1263 * @device: Pointer to the device structure 1264 * 1265 * Return: 0 1266 */ 1267static int cdns_uart_resume(struct device *device) 1268{ 1269 struct uart_port *port = dev_get_drvdata(device); 1270 unsigned long flags = 0; 1271 u32 ctrl_reg; 1272 struct tty_struct *tty; 1273 struct device *tty_dev; 1274 int may_wake = 0; 1275 1276 /* Get the tty which could be NULL so don't assume it's valid */ 1277 tty = tty_port_tty_get(&port->state->port); 1278 if (tty) { 1279 tty_dev = tty->dev; 1280 may_wake = device_may_wakeup(tty_dev); 1281 tty_kref_put(tty); 1282 } 1283 1284 if (console_suspend_enabled && !may_wake) { 1285 struct cdns_uart *cdns_uart = port->private_data; 1286 1287 clk_enable(cdns_uart->pclk); 1288 clk_enable(cdns_uart->uartclk); 1289 1290 spin_lock_irqsave(&port->lock, flags); 1291 1292 /* Set TX/RX Reset */ 1293 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); 1294 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; 1295 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); 1296 while (readl(port->membase + CDNS_UART_CR_OFFSET) & 1297 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) 1298 cpu_relax(); 1299 1300 /* restore rx timeout value */ 1301 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); 1302 /* Enable Tx/Rx */ 1303 ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); 1304 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); 1305 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 1306 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); 1307 1308 spin_unlock_irqrestore(&port->lock, flags); 1309 } else { 1310 spin_lock_irqsave(&port->lock, flags); 1311 /* restore original rx trigger level */ 1312 writel(rx_trigger_level, 1313 port->membase + CDNS_UART_RXWM_OFFSET); 1314 /* enable RX timeout interrupt */ 1315 writel(CDNS_UART_IXR_TOUT, 1316 port->membase + CDNS_UART_IER_OFFSET); 1317 spin_unlock_irqrestore(&port->lock, flags); 1318 } 1319 1320 return uart_resume_port(&cdns_uart_uart_driver, port); 1321} 1322#endif /* ! CONFIG_PM_SLEEP */ 1323 1324static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend, 1325 cdns_uart_resume); 1326 1327/** 1328 * cdns_uart_probe - Platform driver probe 1329 * @pdev: Pointer to the platform device structure 1330 * 1331 * Return: 0 on success, negative errno otherwise 1332 */ 1333static int cdns_uart_probe(struct platform_device *pdev) 1334{ 1335 int rc, id, irq; 1336 struct uart_port *port; 1337 struct resource *res; 1338 struct cdns_uart *cdns_uart_data; 1339 1340 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data), 1341 GFP_KERNEL); 1342 if (!cdns_uart_data) 1343 return -ENOMEM; 1344 1345 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk"); 1346 if (IS_ERR(cdns_uart_data->pclk)) { 1347 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk"); 1348 if (!IS_ERR(cdns_uart_data->pclk)) 1349 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n"); 1350 } 1351 if (IS_ERR(cdns_uart_data->pclk)) { 1352 dev_err(&pdev->dev, "pclk clock not found.\n"); 1353 return PTR_ERR(cdns_uart_data->pclk); 1354 } 1355 1356 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk"); 1357 if (IS_ERR(cdns_uart_data->uartclk)) { 1358 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk"); 1359 if (!IS_ERR(cdns_uart_data->uartclk)) 1360 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); 1361 } 1362 if (IS_ERR(cdns_uart_data->uartclk)) { 1363 dev_err(&pdev->dev, "uart_clk clock not found.\n"); 1364 return PTR_ERR(cdns_uart_data->uartclk); 1365 } 1366 1367 rc = clk_prepare_enable(cdns_uart_data->pclk); 1368 if (rc) { 1369 dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); 1370 return rc; 1371 } 1372 rc = clk_prepare_enable(cdns_uart_data->uartclk); 1373 if (rc) { 1374 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 1375 goto err_out_clk_dis_pclk; 1376 } 1377 1378 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1379 if (!res) { 1380 rc = -ENODEV; 1381 goto err_out_clk_disable; 1382 } 1383 1384 irq = platform_get_irq(pdev, 0); 1385 if (irq <= 0) { 1386 rc = -ENXIO; 1387 goto err_out_clk_disable; 1388 } 1389 1390#ifdef CONFIG_COMMON_CLK 1391 cdns_uart_data->clk_rate_change_nb.notifier_call = 1392 cdns_uart_clk_notifier_cb; 1393 if (clk_notifier_register(cdns_uart_data->uartclk, 1394 &cdns_uart_data->clk_rate_change_nb)) 1395 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1396#endif 1397 /* Look for a serialN alias */ 1398 id = of_alias_get_id(pdev->dev.of_node, "serial"); 1399 if (id < 0) 1400 id = 0; 1401 1402 /* Initialize the port structure */ 1403 port = cdns_uart_get_port(id); 1404 1405 if (!port) { 1406 dev_err(&pdev->dev, "Cannot get uart_port structure\n"); 1407 rc = -ENODEV; 1408 goto err_out_notif_unreg; 1409 } else { 1410 /* Register the port. 1411 * This function also registers this device with the tty layer 1412 * and triggers invocation of the config_port() entry point. 1413 */ 1414 port->mapbase = res->start; 1415 port->irq = irq; 1416 port->dev = &pdev->dev; 1417 port->uartclk = clk_get_rate(cdns_uart_data->uartclk); 1418 port->private_data = cdns_uart_data; 1419 cdns_uart_data->port = port; 1420 platform_set_drvdata(pdev, port); 1421 rc = uart_add_one_port(&cdns_uart_uart_driver, port); 1422 if (rc) { 1423 dev_err(&pdev->dev, 1424 "uart_add_one_port() failed; err=%i\n", rc); 1425 goto err_out_notif_unreg; 1426 } 1427 return 0; 1428 } 1429 1430err_out_notif_unreg: 1431#ifdef CONFIG_COMMON_CLK 1432 clk_notifier_unregister(cdns_uart_data->uartclk, 1433 &cdns_uart_data->clk_rate_change_nb); 1434#endif 1435err_out_clk_disable: 1436 clk_disable_unprepare(cdns_uart_data->uartclk); 1437err_out_clk_dis_pclk: 1438 clk_disable_unprepare(cdns_uart_data->pclk); 1439 1440 return rc; 1441} 1442 1443/** 1444 * cdns_uart_remove - called when the platform driver is unregistered 1445 * @pdev: Pointer to the platform device structure 1446 * 1447 * Return: 0 on success, negative errno otherwise 1448 */ 1449static int cdns_uart_remove(struct platform_device *pdev) 1450{ 1451 struct uart_port *port = platform_get_drvdata(pdev); 1452 struct cdns_uart *cdns_uart_data = port->private_data; 1453 int rc; 1454 1455 /* Remove the cdns_uart port from the serial core */ 1456#ifdef CONFIG_COMMON_CLK 1457 clk_notifier_unregister(cdns_uart_data->uartclk, 1458 &cdns_uart_data->clk_rate_change_nb); 1459#endif 1460 rc = uart_remove_one_port(&cdns_uart_uart_driver, port); 1461 port->mapbase = 0; 1462 clk_disable_unprepare(cdns_uart_data->uartclk); 1463 clk_disable_unprepare(cdns_uart_data->pclk); 1464 return rc; 1465} 1466 1467/* Match table for of_platform binding */ 1468static const struct of_device_id cdns_uart_of_match[] = { 1469 { .compatible = "xlnx,xuartps", }, 1470 { .compatible = "cdns,uart-r1p8", }, 1471 {} 1472}; 1473MODULE_DEVICE_TABLE(of, cdns_uart_of_match); 1474 1475static struct platform_driver cdns_uart_platform_driver = { 1476 .probe = cdns_uart_probe, 1477 .remove = cdns_uart_remove, 1478 .driver = { 1479 .name = CDNS_UART_NAME, 1480 .of_match_table = cdns_uart_of_match, 1481 .pm = &cdns_uart_dev_pm_ops, 1482 }, 1483}; 1484 1485static int __init cdns_uart_init(void) 1486{ 1487 int retval = 0; 1488 1489 /* Register the cdns_uart driver with the serial core */ 1490 retval = uart_register_driver(&cdns_uart_uart_driver); 1491 if (retval) 1492 return retval; 1493 1494 /* Register the platform driver */ 1495 retval = platform_driver_register(&cdns_uart_platform_driver); 1496 if (retval) 1497 uart_unregister_driver(&cdns_uart_uart_driver); 1498 1499 return retval; 1500} 1501 1502static void __exit cdns_uart_exit(void) 1503{ 1504 /* Unregister the platform driver */ 1505 platform_driver_unregister(&cdns_uart_platform_driver); 1506 1507 /* Unregister the cdns_uart driver */ 1508 uart_unregister_driver(&cdns_uart_uart_driver); 1509} 1510 1511module_init(cdns_uart_init); 1512module_exit(cdns_uart_exit); 1513 1514MODULE_DESCRIPTION("Driver for Cadence UART"); 1515MODULE_AUTHOR("Xilinx Inc."); 1516MODULE_LICENSE("GPL"); 1517