1/************************************************************************ 2 * Copyright 2003 Digi International (www.digi.com) 3 * 4 * Copyright (C) 2004 IBM Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 14 * PURPOSE. See the GNU General Public License for more details. 15 * 16 * Contact Information: 17 * Scott H Kilau <Scott_Kilau@digi.com> 18 * Wendy Xiong <wendyx@us.ibm.com> 19 * 20 ***********************************************************************/ 21#include <linux/delay.h> /* For udelay */ 22#include <linux/serial_reg.h> /* For the various UART offsets */ 23#include <linux/tty.h> 24#include <linux/pci.h> 25#include <asm/io.h> 26 27#include "jsm.h" /* Driver main header file */ 28 29static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }; 30 31/* 32 * This function allows calls to ensure that all outstanding 33 * PCI writes have been completed, by doing a PCI read against 34 * a non-destructive, read-only location on the Neo card. 35 * 36 * In this case, we are reading the DVID (Read-only Device Identification) 37 * value of the Neo card. 38 */ 39static inline void neo_pci_posting_flush(struct jsm_board *bd) 40{ 41 readb(bd->re_map_membase + 0x8D); 42} 43 44static void neo_set_cts_flow_control(struct jsm_channel *ch) 45{ 46 u8 ier, efr; 47 ier = readb(&ch->ch_neo_uart->ier); 48 efr = readb(&ch->ch_neo_uart->efr); 49 50 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); 51 52 /* Turn on auto CTS flow control */ 53 ier |= (UART_17158_IER_CTSDSR); 54 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR); 55 56 /* Turn off auto Xon flow control */ 57 efr &= ~(UART_17158_EFR_IXON); 58 59 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 60 writeb(0, &ch->ch_neo_uart->efr); 61 62 /* Turn on UART enhanced bits */ 63 writeb(efr, &ch->ch_neo_uart->efr); 64 65 /* Turn on table D, with 8 char hi/low watermarks */ 66 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 67 68 /* Feed the UART our trigger levels */ 69 writeb(8, &ch->ch_neo_uart->tfifo); 70 ch->ch_t_tlevel = 8; 71 72 writeb(ier, &ch->ch_neo_uart->ier); 73} 74 75static void neo_set_rts_flow_control(struct jsm_channel *ch) 76{ 77 u8 ier, efr; 78 ier = readb(&ch->ch_neo_uart->ier); 79 efr = readb(&ch->ch_neo_uart->efr); 80 81 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n"); 82 83 /* Turn on auto RTS flow control */ 84 ier |= (UART_17158_IER_RTSDTR); 85 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR); 86 87 /* Turn off auto Xoff flow control */ 88 ier &= ~(UART_17158_IER_XOFF); 89 efr &= ~(UART_17158_EFR_IXOFF); 90 91 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 92 writeb(0, &ch->ch_neo_uart->efr); 93 94 /* Turn on UART enhanced bits */ 95 writeb(efr, &ch->ch_neo_uart->efr); 96 97 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 98 ch->ch_r_watermark = 4; 99 100 writeb(56, &ch->ch_neo_uart->rfifo); 101 ch->ch_r_tlevel = 56; 102 103 writeb(ier, &ch->ch_neo_uart->ier); 104 105 /* 106 * From the Neo UART spec sheet: 107 * The auto RTS/DTR function must be started by asserting 108 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after 109 * it is enabled. 110 */ 111 ch->ch_mostat |= (UART_MCR_RTS); 112} 113 114 115static void neo_set_ixon_flow_control(struct jsm_channel *ch) 116{ 117 u8 ier, efr; 118 ier = readb(&ch->ch_neo_uart->ier); 119 efr = readb(&ch->ch_neo_uart->efr); 120 121 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n"); 122 123 /* Turn off auto CTS flow control */ 124 ier &= ~(UART_17158_IER_CTSDSR); 125 efr &= ~(UART_17158_EFR_CTSDSR); 126 127 /* Turn on auto Xon flow control */ 128 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON); 129 130 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 131 writeb(0, &ch->ch_neo_uart->efr); 132 133 /* Turn on UART enhanced bits */ 134 writeb(efr, &ch->ch_neo_uart->efr); 135 136 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 137 ch->ch_r_watermark = 4; 138 139 writeb(32, &ch->ch_neo_uart->rfifo); 140 ch->ch_r_tlevel = 32; 141 142 /* Tell UART what start/stop chars it should be looking for */ 143 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 144 writeb(0, &ch->ch_neo_uart->xonchar2); 145 146 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 147 writeb(0, &ch->ch_neo_uart->xoffchar2); 148 149 writeb(ier, &ch->ch_neo_uart->ier); 150} 151 152static void neo_set_ixoff_flow_control(struct jsm_channel *ch) 153{ 154 u8 ier, efr; 155 ier = readb(&ch->ch_neo_uart->ier); 156 efr = readb(&ch->ch_neo_uart->efr); 157 158 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n"); 159 160 /* Turn off auto RTS flow control */ 161 ier &= ~(UART_17158_IER_RTSDTR); 162 efr &= ~(UART_17158_EFR_RTSDTR); 163 164 /* Turn on auto Xoff flow control */ 165 ier |= (UART_17158_IER_XOFF); 166 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 167 168 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 169 writeb(0, &ch->ch_neo_uart->efr); 170 171 /* Turn on UART enhanced bits */ 172 writeb(efr, &ch->ch_neo_uart->efr); 173 174 /* Turn on table D, with 8 char hi/low watermarks */ 175 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 176 177 writeb(8, &ch->ch_neo_uart->tfifo); 178 ch->ch_t_tlevel = 8; 179 180 /* Tell UART what start/stop chars it should be looking for */ 181 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 182 writeb(0, &ch->ch_neo_uart->xonchar2); 183 184 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 185 writeb(0, &ch->ch_neo_uart->xoffchar2); 186 187 writeb(ier, &ch->ch_neo_uart->ier); 188} 189 190static void neo_set_no_input_flow_control(struct jsm_channel *ch) 191{ 192 u8 ier, efr; 193 ier = readb(&ch->ch_neo_uart->ier); 194 efr = readb(&ch->ch_neo_uart->efr); 195 196 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n"); 197 198 /* Turn off auto RTS flow control */ 199 ier &= ~(UART_17158_IER_RTSDTR); 200 efr &= ~(UART_17158_EFR_RTSDTR); 201 202 /* Turn off auto Xoff flow control */ 203 ier &= ~(UART_17158_IER_XOFF); 204 if (ch->ch_c_iflag & IXON) 205 efr &= ~(UART_17158_EFR_IXOFF); 206 else 207 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 208 209 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 210 writeb(0, &ch->ch_neo_uart->efr); 211 212 /* Turn on UART enhanced bits */ 213 writeb(efr, &ch->ch_neo_uart->efr); 214 215 /* Turn on table D, with 8 char hi/low watermarks */ 216 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 217 218 ch->ch_r_watermark = 0; 219 220 writeb(16, &ch->ch_neo_uart->tfifo); 221 ch->ch_t_tlevel = 16; 222 223 writeb(16, &ch->ch_neo_uart->rfifo); 224 ch->ch_r_tlevel = 16; 225 226 writeb(ier, &ch->ch_neo_uart->ier); 227} 228 229static void neo_set_no_output_flow_control(struct jsm_channel *ch) 230{ 231 u8 ier, efr; 232 ier = readb(&ch->ch_neo_uart->ier); 233 efr = readb(&ch->ch_neo_uart->efr); 234 235 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n"); 236 237 /* Turn off auto CTS flow control */ 238 ier &= ~(UART_17158_IER_CTSDSR); 239 efr &= ~(UART_17158_EFR_CTSDSR); 240 241 /* Turn off auto Xon flow control */ 242 if (ch->ch_c_iflag & IXOFF) 243 efr &= ~(UART_17158_EFR_IXON); 244 else 245 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON); 246 247 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 248 writeb(0, &ch->ch_neo_uart->efr); 249 250 /* Turn on UART enhanced bits */ 251 writeb(efr, &ch->ch_neo_uart->efr); 252 253 /* Turn on table D, with 8 char hi/low watermarks */ 254 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 255 256 ch->ch_r_watermark = 0; 257 258 writeb(16, &ch->ch_neo_uart->tfifo); 259 ch->ch_t_tlevel = 16; 260 261 writeb(16, &ch->ch_neo_uart->rfifo); 262 ch->ch_r_tlevel = 16; 263 264 writeb(ier, &ch->ch_neo_uart->ier); 265} 266 267static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch) 268{ 269 270 /* if hardware flow control is set, then skip this whole thing */ 271 if (ch->ch_c_cflag & CRTSCTS) 272 return; 273 274 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n"); 275 276 /* Tell UART what start/stop chars it should be looking for */ 277 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 278 writeb(0, &ch->ch_neo_uart->xonchar2); 279 280 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 281 writeb(0, &ch->ch_neo_uart->xoffchar2); 282} 283 284static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch) 285{ 286 int qleft = 0; 287 u8 linestatus = 0; 288 u8 error_mask = 0; 289 int n = 0; 290 int total = 0; 291 u16 head; 292 u16 tail; 293 294 if (!ch) 295 return; 296 297 /* cache head and tail of queue */ 298 head = ch->ch_r_head & RQUEUEMASK; 299 tail = ch->ch_r_tail & RQUEUEMASK; 300 301 /* Get our cached LSR */ 302 linestatus = ch->ch_cached_lsr; 303 ch->ch_cached_lsr = 0; 304 305 /* Store how much space we have left in the queue */ 306 if ((qleft = tail - head - 1) < 0) 307 qleft += RQUEUEMASK + 1; 308 309 /* 310 * If the UART is not in FIFO mode, force the FIFO copy to 311 * NOT be run, by setting total to 0. 312 * 313 * On the other hand, if the UART IS in FIFO mode, then ask 314 * the UART to give us an approximation of data it has RX'ed. 315 */ 316 if (!(ch->ch_flags & CH_FIFO_ENABLED)) 317 total = 0; 318 else { 319 total = readb(&ch->ch_neo_uart->rfifo); 320 321 /* 322 * EXAR chip bug - RX FIFO COUNT - Fudge factor. 323 * 324 * This resolves a problem/bug with the Exar chip that sometimes 325 * returns a bogus value in the rfifo register. 326 * The count can be any where from 0-3 bytes "off". 327 * Bizarre, but true. 328 */ 329 total -= 3; 330 } 331 332 /* 333 * Finally, bound the copy to make sure we don't overflow 334 * our own queue... 335 * The byte by byte copy loop below this loop this will 336 * deal with the queue overflow possibility. 337 */ 338 total = min(total, qleft); 339 340 while (total > 0) { 341 /* 342 * Grab the linestatus register, we need to check 343 * to see if there are any errors in the FIFO. 344 */ 345 linestatus = readb(&ch->ch_neo_uart->lsr); 346 347 /* 348 * Break out if there is a FIFO error somewhere. 349 * This will allow us to go byte by byte down below, 350 * finding the exact location of the error. 351 */ 352 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 353 break; 354 355 /* Make sure we don't go over the end of our queue */ 356 n = min(((u32) total), (RQUEUESIZE - (u32) head)); 357 358 /* 359 * Cut down n even further if needed, this is to fix 360 * a problem with memcpy_fromio() with the Neo on the 361 * IBM pSeries platform. 362 * 15 bytes max appears to be the magic number. 363 */ 364 n = min((u32) n, (u32) 12); 365 366 /* 367 * Since we are grabbing the linestatus register, which 368 * will reset some bits after our read, we need to ensure 369 * we don't miss our TX FIFO emptys. 370 */ 371 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) 372 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 373 374 linestatus = 0; 375 376 /* Copy data from uart to the queue */ 377 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n); 378 /* 379 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed 380 * that all the data currently in the FIFO is free of 381 * breaks and parity/frame/orun errors. 382 */ 383 memset(ch->ch_equeue + head, 0, n); 384 385 /* Add to and flip head if needed */ 386 head = (head + n) & RQUEUEMASK; 387 total -= n; 388 qleft -= n; 389 ch->ch_rxcount += n; 390 } 391 392 /* 393 * Create a mask to determine whether we should 394 * insert the character (if any) into our queue. 395 */ 396 if (ch->ch_c_iflag & IGNBRK) 397 error_mask |= UART_LSR_BI; 398 399 /* 400 * Now cleanup any leftover bytes still in the UART. 401 * Also deal with any possible queue overflow here as well. 402 */ 403 while (1) { 404 405 /* 406 * Its possible we have a linestatus from the loop above 407 * this, so we "OR" on any extra bits. 408 */ 409 linestatus |= readb(&ch->ch_neo_uart->lsr); 410 411 /* 412 * If the chip tells us there is no more data pending to 413 * be read, we can then leave. 414 * But before we do, cache the linestatus, just in case. 415 */ 416 if (!(linestatus & UART_LSR_DR)) { 417 ch->ch_cached_lsr = linestatus; 418 break; 419 } 420 421 /* No need to store this bit */ 422 linestatus &= ~UART_LSR_DR; 423 424 /* 425 * Since we are grabbing the linestatus register, which 426 * will reset some bits after our read, we need to ensure 427 * we don't miss our TX FIFO emptys. 428 */ 429 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) { 430 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR); 431 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 432 } 433 434 /* 435 * Discard character if we are ignoring the error mask. 436 */ 437 if (linestatus & error_mask) { 438 u8 discard; 439 linestatus = 0; 440 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1); 441 continue; 442 } 443 444 /* 445 * If our queue is full, we have no choice but to drop some data. 446 * The assumption is that HWFLOW or SWFLOW should have stopped 447 * things way way before we got to this point. 448 * 449 * I decided that I wanted to ditch the oldest data first, 450 * I hope thats okay with everyone? Yes? Good. 451 */ 452 while (qleft < 1) { 453 jsm_dbg(READ, &ch->ch_bd->pci_dev, 454 "Queue full, dropping DATA:%x LSR:%x\n", 455 ch->ch_rqueue[tail], ch->ch_equeue[tail]); 456 457 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK; 458 ch->ch_err_overrun++; 459 qleft++; 460 } 461 462 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1); 463 ch->ch_equeue[head] = (u8) linestatus; 464 465 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n", 466 ch->ch_rqueue[head], ch->ch_equeue[head]); 467 468 /* Ditch any remaining linestatus value. */ 469 linestatus = 0; 470 471 /* Add to and flip head if needed */ 472 head = (head + 1) & RQUEUEMASK; 473 474 qleft--; 475 ch->ch_rxcount++; 476 } 477 478 /* 479 * Write new final heads to channel structure. 480 */ 481 ch->ch_r_head = head & RQUEUEMASK; 482 ch->ch_e_head = head & EQUEUEMASK; 483 jsm_input(ch); 484} 485 486static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch) 487{ 488 u16 head; 489 u16 tail; 490 int n; 491 int s; 492 int qlen; 493 u32 len_written = 0; 494 struct circ_buf *circ; 495 496 if (!ch) 497 return; 498 499 circ = &ch->uart_port.state->xmit; 500 501 /* No data to write to the UART */ 502 if (uart_circ_empty(circ)) 503 return; 504 505 /* If port is "stopped", don't send any data to the UART */ 506 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) 507 return; 508 /* 509 * If FIFOs are disabled. Send data directly to txrx register 510 */ 511 if (!(ch->ch_flags & CH_FIFO_ENABLED)) { 512 u8 lsrbits = readb(&ch->ch_neo_uart->lsr); 513 514 ch->ch_cached_lsr |= lsrbits; 515 if (ch->ch_cached_lsr & UART_LSR_THRE) { 516 ch->ch_cached_lsr &= ~(UART_LSR_THRE); 517 518 writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx); 519 jsm_dbg(WRITE, &ch->ch_bd->pci_dev, 520 "Tx data: %x\n", circ->buf[circ->tail]); 521 circ->tail = (circ->tail + 1) & (UART_XMIT_SIZE - 1); 522 ch->ch_txcount++; 523 } 524 return; 525 } 526 527 /* 528 * We have to do it this way, because of the EXAR TXFIFO count bug. 529 */ 530 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) 531 return; 532 533 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel; 534 535 /* cache head and tail of queue */ 536 head = circ->head & (UART_XMIT_SIZE - 1); 537 tail = circ->tail & (UART_XMIT_SIZE - 1); 538 qlen = uart_circ_chars_pending(circ); 539 540 /* Find minimum of the FIFO space, versus queue length */ 541 n = min(n, qlen); 542 543 while (n > 0) { 544 545 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail; 546 s = min(s, n); 547 548 if (s <= 0) 549 break; 550 551 memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s); 552 /* Add and flip queue if needed */ 553 tail = (tail + s) & (UART_XMIT_SIZE - 1); 554 n -= s; 555 ch->ch_txcount += s; 556 len_written += s; 557 } 558 559 /* Update the final tail */ 560 circ->tail = tail & (UART_XMIT_SIZE - 1); 561 562 if (len_written >= ch->ch_t_tlevel) 563 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 564 565 if (uart_circ_empty(circ)) 566 uart_write_wakeup(&ch->uart_port); 567} 568 569static void neo_parse_modem(struct jsm_channel *ch, u8 signals) 570{ 571 u8 msignals = signals; 572 573 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, 574 "neo_parse_modem: port: %d msignals: %x\n", 575 ch->ch_portnum, msignals); 576 577 /* Scrub off lower bits. They signify delta's, which I don't care about */ 578 /* Keep DDCD and DDSR though */ 579 msignals &= 0xf8; 580 581 if (msignals & UART_MSR_DDCD) 582 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); 583 if (msignals & UART_MSR_DDSR) 584 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS); 585 if (msignals & UART_MSR_DCD) 586 ch->ch_mistat |= UART_MSR_DCD; 587 else 588 ch->ch_mistat &= ~UART_MSR_DCD; 589 590 if (msignals & UART_MSR_DSR) 591 ch->ch_mistat |= UART_MSR_DSR; 592 else 593 ch->ch_mistat &= ~UART_MSR_DSR; 594 595 if (msignals & UART_MSR_RI) 596 ch->ch_mistat |= UART_MSR_RI; 597 else 598 ch->ch_mistat &= ~UART_MSR_RI; 599 600 if (msignals & UART_MSR_CTS) 601 ch->ch_mistat |= UART_MSR_CTS; 602 else 603 ch->ch_mistat &= ~UART_MSR_CTS; 604 605 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, 606 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n", 607 ch->ch_portnum, 608 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), 609 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), 610 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), 611 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), 612 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), 613 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); 614} 615 616/* Make the UART raise any of the output signals we want up */ 617static void neo_assert_modem_signals(struct jsm_channel *ch) 618{ 619 if (!ch) 620 return; 621 622 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 623 624 /* flush write operation */ 625 neo_pci_posting_flush(ch->ch_bd); 626} 627 628/* 629 * Flush the WRITE FIFO on the Neo. 630 * 631 * NOTE: Channel lock MUST be held before calling this function! 632 */ 633static void neo_flush_uart_write(struct jsm_channel *ch) 634{ 635 u8 tmp = 0; 636 int i = 0; 637 638 if (!ch) 639 return; 640 641 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 642 643 for (i = 0; i < 10; i++) { 644 645 /* Check to see if the UART feels it completely flushed the FIFO. */ 646 tmp = readb(&ch->ch_neo_uart->isr_fcr); 647 if (tmp & UART_FCR_CLEAR_XMIT) { 648 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 649 "Still flushing TX UART... i: %d\n", i); 650 udelay(10); 651 } 652 else 653 break; 654 } 655 656 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 657} 658 659 660/* 661 * Flush the READ FIFO on the Neo. 662 * 663 * NOTE: Channel lock MUST be held before calling this function! 664 */ 665static void neo_flush_uart_read(struct jsm_channel *ch) 666{ 667 u8 tmp = 0; 668 int i = 0; 669 670 if (!ch) 671 return; 672 673 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr); 674 675 for (i = 0; i < 10; i++) { 676 677 /* Check to see if the UART feels it completely flushed the FIFO. */ 678 tmp = readb(&ch->ch_neo_uart->isr_fcr); 679 if (tmp & 2) { 680 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 681 "Still flushing RX UART... i: %d\n", i); 682 udelay(10); 683 } 684 else 685 break; 686 } 687} 688 689/* 690 * No locks are assumed to be held when calling this function. 691 */ 692static void neo_clear_break(struct jsm_channel *ch) 693{ 694 unsigned long lock_flags; 695 696 spin_lock_irqsave(&ch->ch_lock, lock_flags); 697 698 /* Turn break off, and unset some variables */ 699 if (ch->ch_flags & CH_BREAK_SENDING) { 700 u8 temp = readb(&ch->ch_neo_uart->lcr); 701 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr); 702 703 ch->ch_flags &= ~(CH_BREAK_SENDING); 704 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 705 "clear break Finishing UART_LCR_SBC! finished: %lx\n", 706 jiffies); 707 708 /* flush write operation */ 709 neo_pci_posting_flush(ch->ch_bd); 710 } 711 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 712} 713 714/* 715 * Parse the ISR register. 716 */ 717static inline void neo_parse_isr(struct jsm_board *brd, u32 port) 718{ 719 struct jsm_channel *ch; 720 u8 isr; 721 u8 cause; 722 unsigned long lock_flags; 723 724 if (!brd) 725 return; 726 727 if (port >= brd->maxports) 728 return; 729 730 ch = brd->channels[port]; 731 if (!ch) 732 return; 733 734 /* Here we try to figure out what caused the interrupt to happen */ 735 while (1) { 736 737 isr = readb(&ch->ch_neo_uart->isr_fcr); 738 739 /* Bail if no pending interrupt */ 740 if (isr & UART_IIR_NO_INT) 741 break; 742 743 /* 744 * Yank off the upper 2 bits, which just show that the FIFO's are enabled. 745 */ 746 isr &= ~(UART_17158_IIR_FIFO_ENABLED); 747 748 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n", 749 __FILE__, __LINE__, isr); 750 751 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) { 752 /* Read data from uart -> queue */ 753 neo_copy_data_from_uart_to_queue(ch); 754 755 /* Call our tty layer to enforce queue flow control if needed. */ 756 spin_lock_irqsave(&ch->ch_lock, lock_flags); 757 jsm_check_queue_flow_control(ch); 758 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 759 } 760 761 if (isr & UART_IIR_THRI) { 762 /* Transfer data (if any) from Write Queue -> UART. */ 763 spin_lock_irqsave(&ch->ch_lock, lock_flags); 764 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 765 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 766 neo_copy_data_from_queue_to_uart(ch); 767 } 768 769 if (isr & UART_17158_IIR_XONXOFF) { 770 cause = readb(&ch->ch_neo_uart->xoffchar1); 771 772 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 773 "Port %d. Got ISR_XONXOFF: cause:%x\n", 774 port, cause); 775 776 /* 777 * Since the UART detected either an XON or 778 * XOFF match, we need to figure out which 779 * one it was, so we can suspend or resume data flow. 780 */ 781 spin_lock_irqsave(&ch->ch_lock, lock_flags); 782 if (cause == UART_17158_XON_DETECT) { 783 /* Is output stopped right now, if so, resume it */ 784 if (brd->channels[port]->ch_flags & CH_STOP) { 785 ch->ch_flags &= ~(CH_STOP); 786 } 787 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 788 "Port %d. XON detected in incoming data\n", 789 port); 790 } 791 else if (cause == UART_17158_XOFF_DETECT) { 792 if (!(brd->channels[port]->ch_flags & CH_STOP)) { 793 ch->ch_flags |= CH_STOP; 794 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 795 "Setting CH_STOP\n"); 796 } 797 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 798 "Port: %d. XOFF detected in incoming data\n", 799 port); 800 } 801 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 802 } 803 804 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) { 805 /* 806 * If we get here, this means the hardware is doing auto flow control. 807 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt. 808 */ 809 cause = readb(&ch->ch_neo_uart->mcr); 810 811 /* Which pin is doing auto flow? RTS or DTR? */ 812 spin_lock_irqsave(&ch->ch_lock, lock_flags); 813 if ((cause & 0x4) == 0) { 814 if (cause & UART_MCR_RTS) 815 ch->ch_mostat |= UART_MCR_RTS; 816 else 817 ch->ch_mostat &= ~(UART_MCR_RTS); 818 } else { 819 if (cause & UART_MCR_DTR) 820 ch->ch_mostat |= UART_MCR_DTR; 821 else 822 ch->ch_mostat &= ~(UART_MCR_DTR); 823 } 824 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 825 } 826 827 /* Parse any modem signal changes */ 828 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 829 "MOD_STAT: sending to parse_modem_sigs\n"); 830 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 831 } 832} 833 834static inline void neo_parse_lsr(struct jsm_board *brd, u32 port) 835{ 836 struct jsm_channel *ch; 837 int linestatus; 838 unsigned long lock_flags; 839 840 if (!brd) 841 return; 842 843 if (port >= brd->maxports) 844 return; 845 846 ch = brd->channels[port]; 847 if (!ch) 848 return; 849 850 linestatus = readb(&ch->ch_neo_uart->lsr); 851 852 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n", 853 __FILE__, __LINE__, port, linestatus); 854 855 ch->ch_cached_lsr |= linestatus; 856 857 if (ch->ch_cached_lsr & UART_LSR_DR) { 858 /* Read data from uart -> queue */ 859 neo_copy_data_from_uart_to_queue(ch); 860 spin_lock_irqsave(&ch->ch_lock, lock_flags); 861 jsm_check_queue_flow_control(ch); 862 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 863 } 864 865 /* 866 * This is a special flag. It indicates that at least 1 867 * RX error (parity, framing, or break) has happened. 868 * Mark this in our struct, which will tell me that I have 869 *to do the special RX+LSR read for this FIFO load. 870 */ 871 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 872 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 873 "%s:%d Port: %d Got an RX error, need to parse LSR\n", 874 __FILE__, __LINE__, port); 875 876 /* 877 * The next 3 tests should *NOT* happen, as the above test 878 * should encapsulate all 3... At least, thats what Exar says. 879 */ 880 881 if (linestatus & UART_LSR_PE) { 882 ch->ch_err_parity++; 883 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n", 884 __FILE__, __LINE__, port); 885 } 886 887 if (linestatus & UART_LSR_FE) { 888 ch->ch_err_frame++; 889 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n", 890 __FILE__, __LINE__, port); 891 } 892 893 if (linestatus & UART_LSR_BI) { 894 ch->ch_err_break++; 895 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 896 "%s:%d Port: %d. BRK INTR!\n", 897 __FILE__, __LINE__, port); 898 } 899 900 if (linestatus & UART_LSR_OE) { 901 /* 902 * Rx Oruns. Exar says that an orun will NOT corrupt 903 * the FIFO. It will just replace the holding register 904 * with this new data byte. So basically just ignore this. 905 * Probably we should eventually have an orun stat in our driver... 906 */ 907 ch->ch_err_overrun++; 908 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 909 "%s:%d Port: %d. Rx Overrun!\n", 910 __FILE__, __LINE__, port); 911 } 912 913 if (linestatus & UART_LSR_THRE) { 914 spin_lock_irqsave(&ch->ch_lock, lock_flags); 915 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 916 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 917 918 /* Transfer data (if any) from Write Queue -> UART. */ 919 neo_copy_data_from_queue_to_uart(ch); 920 } 921 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) { 922 spin_lock_irqsave(&ch->ch_lock, lock_flags); 923 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 924 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 925 926 /* Transfer data (if any) from Write Queue -> UART. */ 927 neo_copy_data_from_queue_to_uart(ch); 928 } 929} 930 931/* 932 * neo_param() 933 * Send any/all changes to the line to the UART. 934 */ 935static void neo_param(struct jsm_channel *ch) 936{ 937 u8 lcr = 0; 938 u8 uart_lcr, ier; 939 u32 baud; 940 int quot; 941 struct jsm_board *bd; 942 943 bd = ch->ch_bd; 944 if (!bd) 945 return; 946 947 /* 948 * If baud rate is zero, flush queues, and set mval to drop DTR. 949 */ 950 if ((ch->ch_c_cflag & (CBAUD)) == 0) { 951 ch->ch_r_head = ch->ch_r_tail = 0; 952 ch->ch_e_head = ch->ch_e_tail = 0; 953 954 neo_flush_uart_write(ch); 955 neo_flush_uart_read(ch); 956 957 ch->ch_flags |= (CH_BAUD0); 958 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); 959 neo_assert_modem_signals(ch); 960 return; 961 962 } else { 963 int i; 964 unsigned int cflag; 965 static struct { 966 unsigned int rate; 967 unsigned int cflag; 968 } baud_rates[] = { 969 { 921600, B921600 }, 970 { 460800, B460800 }, 971 { 230400, B230400 }, 972 { 115200, B115200 }, 973 { 57600, B57600 }, 974 { 38400, B38400 }, 975 { 19200, B19200 }, 976 { 9600, B9600 }, 977 { 4800, B4800 }, 978 { 2400, B2400 }, 979 { 1200, B1200 }, 980 { 600, B600 }, 981 { 300, B300 }, 982 { 200, B200 }, 983 { 150, B150 }, 984 { 134, B134 }, 985 { 110, B110 }, 986 { 75, B75 }, 987 { 50, B50 }, 988 }; 989 990 cflag = C_BAUD(ch->uart_port.state->port.tty); 991 baud = 9600; 992 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) { 993 if (baud_rates[i].cflag == cflag) { 994 baud = baud_rates[i].rate; 995 break; 996 } 997 } 998 999 if (ch->ch_flags & CH_BAUD0) 1000 ch->ch_flags &= ~(CH_BAUD0); 1001 } 1002 1003 if (ch->ch_c_cflag & PARENB) 1004 lcr |= UART_LCR_PARITY; 1005 1006 if (!(ch->ch_c_cflag & PARODD)) 1007 lcr |= UART_LCR_EPAR; 1008 1009 /* 1010 * Not all platforms support mark/space parity, 1011 * so this will hide behind an ifdef. 1012 */ 1013#ifdef CMSPAR 1014 if (ch->ch_c_cflag & CMSPAR) 1015 lcr |= UART_LCR_SPAR; 1016#endif 1017 1018 if (ch->ch_c_cflag & CSTOPB) 1019 lcr |= UART_LCR_STOP; 1020 1021 switch (ch->ch_c_cflag & CSIZE) { 1022 case CS5: 1023 lcr |= UART_LCR_WLEN5; 1024 break; 1025 case CS6: 1026 lcr |= UART_LCR_WLEN6; 1027 break; 1028 case CS7: 1029 lcr |= UART_LCR_WLEN7; 1030 break; 1031 case CS8: 1032 default: 1033 lcr |= UART_LCR_WLEN8; 1034 break; 1035 } 1036 1037 ier = readb(&ch->ch_neo_uart->ier); 1038 uart_lcr = readb(&ch->ch_neo_uart->lcr); 1039 1040 quot = ch->ch_bd->bd_dividend / baud; 1041 1042 if (quot != 0) { 1043 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr); 1044 writeb((quot & 0xff), &ch->ch_neo_uart->txrx); 1045 writeb((quot >> 8), &ch->ch_neo_uart->ier); 1046 writeb(lcr, &ch->ch_neo_uart->lcr); 1047 } 1048 1049 if (uart_lcr != lcr) 1050 writeb(lcr, &ch->ch_neo_uart->lcr); 1051 1052 if (ch->ch_c_cflag & CREAD) 1053 ier |= (UART_IER_RDI | UART_IER_RLSI); 1054 1055 ier |= (UART_IER_THRI | UART_IER_MSI); 1056 1057 writeb(ier, &ch->ch_neo_uart->ier); 1058 1059 /* Set new start/stop chars */ 1060 neo_set_new_start_stop_chars(ch); 1061 1062 if (ch->ch_c_cflag & CRTSCTS) 1063 neo_set_cts_flow_control(ch); 1064 else if (ch->ch_c_iflag & IXON) { 1065 /* If start/stop is set to disable, then we should disable flow control */ 1066 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) 1067 neo_set_no_output_flow_control(ch); 1068 else 1069 neo_set_ixon_flow_control(ch); 1070 } 1071 else 1072 neo_set_no_output_flow_control(ch); 1073 1074 if (ch->ch_c_cflag & CRTSCTS) 1075 neo_set_rts_flow_control(ch); 1076 else if (ch->ch_c_iflag & IXOFF) { 1077 /* If start/stop is set to disable, then we should disable flow control */ 1078 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) 1079 neo_set_no_input_flow_control(ch); 1080 else 1081 neo_set_ixoff_flow_control(ch); 1082 } 1083 else 1084 neo_set_no_input_flow_control(ch); 1085 /* 1086 * Adjust the RX FIFO Trigger level if baud is less than 9600. 1087 * Not exactly elegant, but this is needed because of the Exar chip's 1088 * delay on firing off the RX FIFO interrupt on slower baud rates. 1089 */ 1090 if (baud < 9600) { 1091 writeb(1, &ch->ch_neo_uart->rfifo); 1092 ch->ch_r_tlevel = 1; 1093 } 1094 1095 neo_assert_modem_signals(ch); 1096 1097 /* Get current status of the modem signals now */ 1098 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 1099 return; 1100} 1101 1102/* 1103 * jsm_neo_intr() 1104 * 1105 * Neo specific interrupt handler. 1106 */ 1107static irqreturn_t neo_intr(int irq, void *voidbrd) 1108{ 1109 struct jsm_board *brd = voidbrd; 1110 struct jsm_channel *ch; 1111 int port = 0; 1112 int type = 0; 1113 int current_port; 1114 u32 tmp; 1115 u32 uart_poll; 1116 unsigned long lock_flags; 1117 unsigned long lock_flags2; 1118 int outofloop_count = 0; 1119 1120 /* Lock out the slow poller from running on this board. */ 1121 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags); 1122 1123 /* 1124 * Read in "extended" IRQ information from the 32bit Neo register. 1125 * Bits 0-7: What port triggered the interrupt. 1126 * Bits 8-31: Each 3bits indicate what type of interrupt occurred. 1127 */ 1128 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET); 1129 1130 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n", 1131 __FILE__, __LINE__, uart_poll); 1132 1133 if (!uart_poll) { 1134 jsm_dbg(INTR, &brd->pci_dev, 1135 "Kernel interrupted to me, but no pending interrupts...\n"); 1136 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 1137 return IRQ_NONE; 1138 } 1139 1140 /* At this point, we have at least SOMETHING to service, dig further... */ 1141 1142 current_port = 0; 1143 1144 /* Loop on each port */ 1145 while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){ 1146 1147 tmp = uart_poll; 1148 outofloop_count++; 1149 1150 /* Check current port to see if it has interrupt pending */ 1151 if ((tmp & jsm_offset_table[current_port]) != 0) { 1152 port = current_port; 1153 type = tmp >> (8 + (port * 3)); 1154 type &= 0x7; 1155 } else { 1156 current_port++; 1157 continue; 1158 } 1159 1160 jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n", 1161 __FILE__, __LINE__, port, type); 1162 1163 /* Remove this port + type from uart_poll */ 1164 uart_poll &= ~(jsm_offset_table[port]); 1165 1166 if (!type) { 1167 /* If no type, just ignore it, and move onto next port */ 1168 jsm_dbg(INTR, &brd->pci_dev, 1169 "Interrupt with no type! port: %d\n", port); 1170 continue; 1171 } 1172 1173 /* Switch on type of interrupt we have */ 1174 switch (type) { 1175 1176 case UART_17158_RXRDY_TIMEOUT: 1177 /* 1178 * RXRDY Time-out is cleared by reading data in the 1179 * RX FIFO until it falls below the trigger level. 1180 */ 1181 1182 /* Verify the port is in range. */ 1183 if (port >= brd->nasync) 1184 continue; 1185 1186 ch = brd->channels[port]; 1187 neo_copy_data_from_uart_to_queue(ch); 1188 1189 /* Call our tty layer to enforce queue flow control if needed. */ 1190 spin_lock_irqsave(&ch->ch_lock, lock_flags2); 1191 jsm_check_queue_flow_control(ch); 1192 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2); 1193 1194 continue; 1195 1196 case UART_17158_RX_LINE_STATUS: 1197 /* 1198 * RXRDY and RX LINE Status (logic OR of LSR[4:1]) 1199 */ 1200 neo_parse_lsr(brd, port); 1201 continue; 1202 1203 case UART_17158_TXRDY: 1204 /* 1205 * TXRDY interrupt clears after reading ISR register for the UART channel. 1206 */ 1207 1208 /* 1209 * Yes, this is odd... 1210 * Why would I check EVERY possibility of type of 1211 * interrupt, when we know its TXRDY??? 1212 * Becuz for some reason, even tho we got triggered for TXRDY, 1213 * it seems to be occasionally wrong. Instead of TX, which 1214 * it should be, I was getting things like RXDY too. Weird. 1215 */ 1216 neo_parse_isr(brd, port); 1217 continue; 1218 1219 case UART_17158_MSR: 1220 /* 1221 * MSR or flow control was seen. 1222 */ 1223 neo_parse_isr(brd, port); 1224 continue; 1225 1226 default: 1227 /* 1228 * The UART triggered us with a bogus interrupt type. 1229 * It appears the Exar chip, when REALLY bogged down, will throw 1230 * these once and awhile. 1231 * Its harmless, just ignore it and move on. 1232 */ 1233 jsm_dbg(INTR, &brd->pci_dev, 1234 "%s:%d Unknown Interrupt type: %x\n", 1235 __FILE__, __LINE__, type); 1236 continue; 1237 } 1238 } 1239 1240 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 1241 1242 jsm_dbg(INTR, &brd->pci_dev, "finish\n"); 1243 return IRQ_HANDLED; 1244} 1245 1246/* 1247 * Neo specific way of turning off the receiver. 1248 * Used as a way to enforce queue flow control when in 1249 * hardware flow control mode. 1250 */ 1251static void neo_disable_receiver(struct jsm_channel *ch) 1252{ 1253 u8 tmp = readb(&ch->ch_neo_uart->ier); 1254 tmp &= ~(UART_IER_RDI); 1255 writeb(tmp, &ch->ch_neo_uart->ier); 1256 1257 /* flush write operation */ 1258 neo_pci_posting_flush(ch->ch_bd); 1259} 1260 1261 1262/* 1263 * Neo specific way of turning on the receiver. 1264 * Used as a way to un-enforce queue flow control when in 1265 * hardware flow control mode. 1266 */ 1267static void neo_enable_receiver(struct jsm_channel *ch) 1268{ 1269 u8 tmp = readb(&ch->ch_neo_uart->ier); 1270 tmp |= (UART_IER_RDI); 1271 writeb(tmp, &ch->ch_neo_uart->ier); 1272 1273 /* flush write operation */ 1274 neo_pci_posting_flush(ch->ch_bd); 1275} 1276 1277static void neo_send_start_character(struct jsm_channel *ch) 1278{ 1279 if (!ch) 1280 return; 1281 1282 if (ch->ch_startc != __DISABLED_CHAR) { 1283 ch->ch_xon_sends++; 1284 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx); 1285 1286 /* flush write operation */ 1287 neo_pci_posting_flush(ch->ch_bd); 1288 } 1289} 1290 1291static void neo_send_stop_character(struct jsm_channel *ch) 1292{ 1293 if (!ch) 1294 return; 1295 1296 if (ch->ch_stopc != __DISABLED_CHAR) { 1297 ch->ch_xoff_sends++; 1298 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx); 1299 1300 /* flush write operation */ 1301 neo_pci_posting_flush(ch->ch_bd); 1302 } 1303} 1304 1305/* 1306 * neo_uart_init 1307 */ 1308static void neo_uart_init(struct jsm_channel *ch) 1309{ 1310 writeb(0, &ch->ch_neo_uart->ier); 1311 writeb(0, &ch->ch_neo_uart->efr); 1312 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr); 1313 1314 /* Clear out UART and FIFO */ 1315 readb(&ch->ch_neo_uart->txrx); 1316 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 1317 readb(&ch->ch_neo_uart->lsr); 1318 readb(&ch->ch_neo_uart->msr); 1319 1320 ch->ch_flags |= CH_FIFO_ENABLED; 1321 1322 /* Assert any signals we want up */ 1323 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 1324} 1325 1326/* 1327 * Make the UART completely turn off. 1328 */ 1329static void neo_uart_off(struct jsm_channel *ch) 1330{ 1331 /* Turn off UART enhanced bits */ 1332 writeb(0, &ch->ch_neo_uart->efr); 1333 1334 /* Stop all interrupts from occurring. */ 1335 writeb(0, &ch->ch_neo_uart->ier); 1336} 1337 1338static u32 neo_get_uart_bytes_left(struct jsm_channel *ch) 1339{ 1340 u8 left = 0; 1341 u8 lsr = readb(&ch->ch_neo_uart->lsr); 1342 1343 /* We must cache the LSR as some of the bits get reset once read... */ 1344 ch->ch_cached_lsr |= lsr; 1345 1346 /* Determine whether the Transmitter is empty or not */ 1347 if (!(lsr & UART_LSR_TEMT)) 1348 left = 1; 1349 else { 1350 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1351 left = 0; 1352 } 1353 1354 return left; 1355} 1356 1357/* Channel lock MUST be held by the calling function! */ 1358static void neo_send_break(struct jsm_channel *ch) 1359{ 1360 /* 1361 * Set the time we should stop sending the break. 1362 * If we are already sending a break, toss away the existing 1363 * time to stop, and use this new value instead. 1364 */ 1365 1366 /* Tell the UART to start sending the break */ 1367 if (!(ch->ch_flags & CH_BREAK_SENDING)) { 1368 u8 temp = readb(&ch->ch_neo_uart->lcr); 1369 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr); 1370 ch->ch_flags |= (CH_BREAK_SENDING); 1371 1372 /* flush write operation */ 1373 neo_pci_posting_flush(ch->ch_bd); 1374 } 1375} 1376 1377/* 1378 * neo_send_immediate_char. 1379 * 1380 * Sends a specific character as soon as possible to the UART, 1381 * jumping over any bytes that might be in the write queue. 1382 * 1383 * The channel lock MUST be held by the calling function. 1384 */ 1385static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c) 1386{ 1387 if (!ch) 1388 return; 1389 1390 writeb(c, &ch->ch_neo_uart->txrx); 1391 1392 /* flush write operation */ 1393 neo_pci_posting_flush(ch->ch_bd); 1394} 1395 1396struct board_ops jsm_neo_ops = { 1397 .intr = neo_intr, 1398 .uart_init = neo_uart_init, 1399 .uart_off = neo_uart_off, 1400 .param = neo_param, 1401 .assert_modem_signals = neo_assert_modem_signals, 1402 .flush_uart_write = neo_flush_uart_write, 1403 .flush_uart_read = neo_flush_uart_read, 1404 .disable_receiver = neo_disable_receiver, 1405 .enable_receiver = neo_enable_receiver, 1406 .send_break = neo_send_break, 1407 .clear_break = neo_clear_break, 1408 .send_start_character = neo_send_start_character, 1409 .send_stop_character = neo_send_stop_character, 1410 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart, 1411 .get_uart_bytes_left = neo_get_uart_bytes_left, 1412 .send_immediate_char = neo_send_immediate_char 1413}; 1414