1/* 2 * DTC controller, taken from T128 driver by... 3 * Copyright 1993, Drew Eckhardt 4 * Visionary Computing 5 * (Unix and Linux consulting and custom programming) 6 * drew@colorado.edu 7 * +1 (303) 440-4894 8 */ 9 10#ifndef DTC3280_H 11#define DTC3280_H 12 13#define DTCDEBUG 0 14#define DTCDEBUG_INIT 0x1 15#define DTCDEBUG_TRANSFER 0x2 16 17#ifndef CMD_PER_LUN 18#define CMD_PER_LUN 2 19#endif 20 21#ifndef CAN_QUEUE 22#define CAN_QUEUE 32 23#endif 24 25#define NCR5380_implementation_fields \ 26 void __iomem *base 27 28#define NCR5380_local_declare() \ 29 void __iomem *base 30 31#define NCR5380_setup(instance) \ 32 base = ((struct NCR5380_hostdata *)(instance)->hostdata)->base 33 34#define DTC_address(reg) (base + DTC_5380_OFFSET + reg) 35 36#define dbNCR5380_read(reg) \ 37 (rval=readb(DTC_address(reg)), \ 38 (((unsigned char) printk("DTC : read register %d at addr %p is: %02x\n"\ 39 , (reg), DTC_address(reg), rval)), rval ) ) 40 41#define dbNCR5380_write(reg, value) do { \ 42 printk("DTC : write %02x to register %d at address %p\n", \ 43 (value), (reg), DTC_address(reg)); \ 44 writeb(value, DTC_address(reg));} while(0) 45 46 47#if !(DTCDEBUG & DTCDEBUG_TRANSFER) 48#define NCR5380_read(reg) (readb(DTC_address(reg))) 49#define NCR5380_write(reg, value) (writeb(value, DTC_address(reg))) 50#else 51#define NCR5380_read(reg) (readb(DTC_address(reg))) 52#define xNCR5380_read(reg) \ 53 (((unsigned char) printk("DTC : read register %d at address %p\n"\ 54 , (reg), DTC_address(reg))), readb(DTC_address(reg))) 55 56#define NCR5380_write(reg, value) do { \ 57 printk("DTC : write %02x to register %d at address %p\n", \ 58 (value), (reg), DTC_address(reg)); \ 59 writeb(value, DTC_address(reg));} while(0) 60#endif 61 62#define NCR5380_intr dtc_intr 63#define NCR5380_queue_command dtc_queue_command 64#define NCR5380_abort dtc_abort 65#define NCR5380_bus_reset dtc_bus_reset 66#define NCR5380_info dtc_info 67#define NCR5380_show_info dtc_show_info 68#define NCR5380_write_info dtc_write_info 69 70/* 15 12 11 10 71 1001 1100 0000 0000 */ 72 73#define DTC_IRQS 0x9c00 74 75 76#endif /* DTC3280_H */ 77