1/* 2 * Generic GPIO driver for logic cells found in the Nomadik SoC 3 * 4 * Copyright (C) 2008,2009 STMicroelectronics 5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> 6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> 7 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/init.h> 16#include <linux/device.h> 17#include <linux/platform_device.h> 18#include <linux/io.h> 19#include <linux/clk.h> 20#include <linux/err.h> 21#include <linux/gpio.h> 22#include <linux/spinlock.h> 23#include <linux/interrupt.h> 24#include <linux/slab.h> 25#include <linux/of_device.h> 26#include <linux/of_address.h> 27#include <linux/pinctrl/machine.h> 28#include <linux/pinctrl/pinctrl.h> 29#include <linux/pinctrl/pinmux.h> 30#include <linux/pinctrl/pinconf.h> 31/* Since we request GPIOs from ourself */ 32#include <linux/pinctrl/consumer.h> 33#include "pinctrl-nomadik.h" 34#include "../core.h" 35#include "../pinctrl-utils.h" 36 37/* 38 * The GPIO module in the Nomadik family of Systems-on-Chip is an 39 * AMBA device, managing 32 pins and alternate functions. The logic block 40 * is currently used in the Nomadik and ux500. 41 * 42 * Symbols in this file are called "nmk_gpio" for "nomadik gpio" 43 */ 44 45/* 46 * pin configurations are represented by 32-bit integers: 47 * 48 * bit 0.. 8 - Pin Number (512 Pins Maximum) 49 * bit 9..10 - Alternate Function Selection 50 * bit 11..12 - Pull up/down state 51 * bit 13 - Sleep mode behaviour 52 * bit 14 - Direction 53 * bit 15 - Value (if output) 54 * bit 16..18 - SLPM pull up/down state 55 * bit 19..20 - SLPM direction 56 * bit 21..22 - SLPM Value (if output) 57 * bit 23..25 - PDIS value (if input) 58 * bit 26 - Gpio mode 59 * bit 27 - Sleep mode 60 * 61 * to facilitate the definition, the following macros are provided 62 * 63 * PIN_CFG_DEFAULT - default config (0): 64 * pull up/down = disabled 65 * sleep mode = input/wakeup 66 * direction = input 67 * value = low 68 * SLPM direction = same as normal 69 * SLPM pull = same as normal 70 * SLPM value = same as normal 71 * 72 * PIN_CFG - default config with alternate function 73 */ 74 75typedef unsigned long pin_cfg_t; 76 77#define PIN_NUM_MASK 0x1ff 78#define PIN_NUM(x) ((x) & PIN_NUM_MASK) 79 80#define PIN_ALT_SHIFT 9 81#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) 82#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) 83#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) 84#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) 85#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) 86#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) 87 88#define PIN_PULL_SHIFT 11 89#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) 90#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) 91#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) 92#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) 93#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) 94 95#define PIN_SLPM_SHIFT 13 96#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) 97#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) 98#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) 99#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) 100/* These two replace the above in DB8500v2+ */ 101#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) 102#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) 103#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE 104 105#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ 106#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ 107 108#define PIN_DIR_SHIFT 14 109#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) 110#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) 111#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) 112#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) 113 114#define PIN_VAL_SHIFT 15 115#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) 116#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) 117#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) 118#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) 119 120#define PIN_SLPM_PULL_SHIFT 16 121#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) 122#define PIN_SLPM_PULL(x) \ 123 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) 124#define PIN_SLPM_PULL_NONE \ 125 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) 126#define PIN_SLPM_PULL_UP \ 127 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) 128#define PIN_SLPM_PULL_DOWN \ 129 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) 130 131#define PIN_SLPM_DIR_SHIFT 19 132#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) 133#define PIN_SLPM_DIR(x) \ 134 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) 135#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) 136#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) 137 138#define PIN_SLPM_VAL_SHIFT 21 139#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) 140#define PIN_SLPM_VAL(x) \ 141 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) 142#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) 143#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) 144 145#define PIN_SLPM_PDIS_SHIFT 23 146#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) 147#define PIN_SLPM_PDIS(x) \ 148 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) 149#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) 150#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) 151#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) 152 153#define PIN_LOWEMI_SHIFT 25 154#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) 155#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) 156#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) 157#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) 158 159#define PIN_GPIOMODE_SHIFT 26 160#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) 161#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) 162#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) 163#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) 164 165#define PIN_SLEEPMODE_SHIFT 27 166#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) 167#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) 168#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) 169#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) 170 171 172/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ 173#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) 174#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) 175#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) 176#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) 177#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) 178 179#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) 180#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) 181#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) 182#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) 183#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) 184 185#define PIN_CFG_DEFAULT (0) 186 187#define PIN_CFG(num, alt) \ 188 (PIN_CFG_DEFAULT |\ 189 (PIN_NUM(num) | PIN_##alt)) 190 191#define PIN_CFG_INPUT(num, alt, pull) \ 192 (PIN_CFG_DEFAULT |\ 193 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) 194 195#define PIN_CFG_OUTPUT(num, alt, val) \ 196 (PIN_CFG_DEFAULT |\ 197 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) 198 199/* 200 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving 201 * the "gpio" namespace for generic and cross-machine functions 202 */ 203 204#define GPIO_BLOCK_SHIFT 5 205#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) 206#define NMK_MAX_BANKS DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP) 207 208/* Register in the logic block */ 209#define NMK_GPIO_DAT 0x00 210#define NMK_GPIO_DATS 0x04 211#define NMK_GPIO_DATC 0x08 212#define NMK_GPIO_PDIS 0x0c 213#define NMK_GPIO_DIR 0x10 214#define NMK_GPIO_DIRS 0x14 215#define NMK_GPIO_DIRC 0x18 216#define NMK_GPIO_SLPC 0x1c 217#define NMK_GPIO_AFSLA 0x20 218#define NMK_GPIO_AFSLB 0x24 219#define NMK_GPIO_LOWEMI 0x28 220 221#define NMK_GPIO_RIMSC 0x40 222#define NMK_GPIO_FIMSC 0x44 223#define NMK_GPIO_IS 0x48 224#define NMK_GPIO_IC 0x4c 225#define NMK_GPIO_RWIMSC 0x50 226#define NMK_GPIO_FWIMSC 0x54 227#define NMK_GPIO_WKS 0x58 228/* These appear in DB8540 and later ASICs */ 229#define NMK_GPIO_EDGELEVEL 0x5C 230#define NMK_GPIO_LEVEL 0x60 231 232 233/* Pull up/down values */ 234enum nmk_gpio_pull { 235 NMK_GPIO_PULL_NONE, 236 NMK_GPIO_PULL_UP, 237 NMK_GPIO_PULL_DOWN, 238}; 239 240/* Sleep mode */ 241enum nmk_gpio_slpm { 242 NMK_GPIO_SLPM_INPUT, 243 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, 244 NMK_GPIO_SLPM_NOCHANGE, 245 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, 246}; 247 248struct nmk_gpio_chip { 249 struct gpio_chip chip; 250 struct irq_chip irqchip; 251 void __iomem *addr; 252 struct clk *clk; 253 unsigned int bank; 254 unsigned int parent_irq; 255 int latent_parent_irq; 256 u32 (*get_latent_status)(unsigned int bank); 257 void (*set_ioforce)(bool enable); 258 spinlock_t lock; 259 bool sleepmode; 260 /* Keep track of configured edges */ 261 u32 edge_rising; 262 u32 edge_falling; 263 u32 real_wake; 264 u32 rwimsc; 265 u32 fwimsc; 266 u32 rimsc; 267 u32 fimsc; 268 u32 pull_up; 269 u32 lowemi; 270}; 271 272/** 273 * struct nmk_pinctrl - state container for the Nomadik pin controller 274 * @dev: containing device pointer 275 * @pctl: corresponding pin controller device 276 * @soc: SoC data for this specific chip 277 * @prcm_base: PRCM register range virtual base 278 */ 279struct nmk_pinctrl { 280 struct device *dev; 281 struct pinctrl_dev *pctl; 282 const struct nmk_pinctrl_soc_data *soc; 283 void __iomem *prcm_base; 284}; 285 286static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS]; 287 288static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); 289 290#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) 291 292static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, 293 unsigned offset, int gpio_mode) 294{ 295 u32 bit = 1 << offset; 296 u32 afunc, bfunc; 297 298 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; 299 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; 300 if (gpio_mode & NMK_GPIO_ALT_A) 301 afunc |= bit; 302 if (gpio_mode & NMK_GPIO_ALT_B) 303 bfunc |= bit; 304 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); 305 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); 306} 307 308static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, 309 unsigned offset, enum nmk_gpio_slpm mode) 310{ 311 u32 bit = 1 << offset; 312 u32 slpm; 313 314 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); 315 if (mode == NMK_GPIO_SLPM_NOCHANGE) 316 slpm |= bit; 317 else 318 slpm &= ~bit; 319 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); 320} 321 322static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, 323 unsigned offset, enum nmk_gpio_pull pull) 324{ 325 u32 bit = 1 << offset; 326 u32 pdis; 327 328 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); 329 if (pull == NMK_GPIO_PULL_NONE) { 330 pdis |= bit; 331 nmk_chip->pull_up &= ~bit; 332 } else { 333 pdis &= ~bit; 334 } 335 336 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); 337 338 if (pull == NMK_GPIO_PULL_UP) { 339 nmk_chip->pull_up |= bit; 340 writel(bit, nmk_chip->addr + NMK_GPIO_DATS); 341 } else if (pull == NMK_GPIO_PULL_DOWN) { 342 nmk_chip->pull_up &= ~bit; 343 writel(bit, nmk_chip->addr + NMK_GPIO_DATC); 344 } 345} 346 347static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, 348 unsigned offset, bool lowemi) 349{ 350 u32 bit = BIT(offset); 351 bool enabled = nmk_chip->lowemi & bit; 352 353 if (lowemi == enabled) 354 return; 355 356 if (lowemi) 357 nmk_chip->lowemi |= bit; 358 else 359 nmk_chip->lowemi &= ~bit; 360 361 writel_relaxed(nmk_chip->lowemi, 362 nmk_chip->addr + NMK_GPIO_LOWEMI); 363} 364 365static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, 366 unsigned offset) 367{ 368 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); 369} 370 371static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, 372 unsigned offset, int val) 373{ 374 if (val) 375 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); 376 else 377 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); 378} 379 380static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, 381 unsigned offset, int val) 382{ 383 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); 384 __nmk_gpio_set_output(nmk_chip, offset, val); 385} 386 387static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, 388 unsigned offset, int gpio_mode, 389 bool glitch) 390{ 391 u32 rwimsc = nmk_chip->rwimsc; 392 u32 fwimsc = nmk_chip->fwimsc; 393 394 if (glitch && nmk_chip->set_ioforce) { 395 u32 bit = BIT(offset); 396 397 /* Prevent spurious wakeups */ 398 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); 399 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); 400 401 nmk_chip->set_ioforce(true); 402 } 403 404 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); 405 406 if (glitch && nmk_chip->set_ioforce) { 407 nmk_chip->set_ioforce(false); 408 409 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); 410 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); 411 } 412} 413 414static void 415nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) 416{ 417 u32 falling = nmk_chip->fimsc & BIT(offset); 418 u32 rising = nmk_chip->rimsc & BIT(offset); 419 int gpio = nmk_chip->chip.base + offset; 420 int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset); 421 struct irq_data *d = irq_get_irq_data(irq); 422 423 if (!rising && !falling) 424 return; 425 426 if (!d || !irqd_irq_disabled(d)) 427 return; 428 429 if (rising) { 430 nmk_chip->rimsc &= ~BIT(offset); 431 writel_relaxed(nmk_chip->rimsc, 432 nmk_chip->addr + NMK_GPIO_RIMSC); 433 } 434 435 if (falling) { 436 nmk_chip->fimsc &= ~BIT(offset); 437 writel_relaxed(nmk_chip->fimsc, 438 nmk_chip->addr + NMK_GPIO_FIMSC); 439 } 440 441 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); 442} 443 444static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) 445{ 446 u32 val; 447 448 val = readl(reg); 449 val = ((val & ~mask) | (value & mask)); 450 writel(val, reg); 451} 452 453static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, 454 unsigned offset, unsigned alt_num) 455{ 456 int i; 457 u16 reg; 458 u8 bit; 459 u8 alt_index; 460 const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 461 const u16 *gpiocr_regs; 462 463 if (!npct->prcm_base) 464 return; 465 466 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { 467 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", 468 alt_num); 469 return; 470 } 471 472 for (i = 0 ; i < npct->soc->npins_altcx ; i++) { 473 if (npct->soc->altcx_pins[i].pin == offset) 474 break; 475 } 476 if (i == npct->soc->npins_altcx) { 477 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", 478 offset); 479 return; 480 } 481 482 pin_desc = npct->soc->altcx_pins + i; 483 gpiocr_regs = npct->soc->prcm_gpiocr_registers; 484 485 /* 486 * If alt_num is NULL, just clear current ALTCx selection 487 * to make sure we come back to a pure ALTC selection 488 */ 489 if (!alt_num) { 490 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 491 if (pin_desc->altcx[i].used == true) { 492 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 493 bit = pin_desc->altcx[i].control_bit; 494 if (readl(npct->prcm_base + reg) & BIT(bit)) { 495 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 496 dev_dbg(npct->dev, 497 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 498 offset, i+1); 499 } 500 } 501 } 502 return; 503 } 504 505 alt_index = alt_num - 1; 506 if (pin_desc->altcx[alt_index].used == false) { 507 dev_warn(npct->dev, 508 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", 509 offset, alt_num); 510 return; 511 } 512 513 /* 514 * Check if any other ALTCx functions are activated on this pin 515 * and disable it first. 516 */ 517 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 518 if (i == alt_index) 519 continue; 520 if (pin_desc->altcx[i].used == true) { 521 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 522 bit = pin_desc->altcx[i].control_bit; 523 if (readl(npct->prcm_base + reg) & BIT(bit)) { 524 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 525 dev_dbg(npct->dev, 526 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 527 offset, i+1); 528 } 529 } 530 } 531 532 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; 533 bit = pin_desc->altcx[alt_index].control_bit; 534 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", 535 offset, alt_index+1); 536 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); 537} 538 539/* 540 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 541 * - Save SLPM registers 542 * - Set SLPM=0 for the IOs you want to switch and others to 1 543 * - Configure the GPIO registers for the IOs that are being switched 544 * - Set IOFORCE=1 545 * - Modify the AFLSA/B registers for the IOs that are being switched 546 * - Set IOFORCE=0 547 * - Restore SLPM registers 548 * - Any spurious wake up event during switch sequence to be ignored and 549 * cleared 550 */ 551static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) 552{ 553 int i; 554 555 for (i = 0; i < NUM_BANKS; i++) { 556 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 557 unsigned int temp = slpm[i]; 558 559 if (!chip) 560 break; 561 562 clk_enable(chip->clk); 563 564 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); 565 writel(temp, chip->addr + NMK_GPIO_SLPC); 566 } 567} 568 569static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) 570{ 571 int i; 572 573 for (i = 0; i < NUM_BANKS; i++) { 574 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 575 576 if (!chip) 577 break; 578 579 writel(slpm[i], chip->addr + NMK_GPIO_SLPC); 580 581 clk_disable(chip->clk); 582 } 583} 584 585static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) 586{ 587 int i; 588 u16 reg; 589 u8 bit; 590 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 591 const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 592 const u16 *gpiocr_regs; 593 594 if (!npct->prcm_base) 595 return NMK_GPIO_ALT_C; 596 597 for (i = 0; i < npct->soc->npins_altcx; i++) { 598 if (npct->soc->altcx_pins[i].pin == gpio) 599 break; 600 } 601 if (i == npct->soc->npins_altcx) 602 return NMK_GPIO_ALT_C; 603 604 pin_desc = npct->soc->altcx_pins + i; 605 gpiocr_regs = npct->soc->prcm_gpiocr_registers; 606 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { 607 if (pin_desc->altcx[i].used == true) { 608 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 609 bit = pin_desc->altcx[i].control_bit; 610 if (readl(npct->prcm_base + reg) & BIT(bit)) 611 return NMK_GPIO_ALT_C+i+1; 612 } 613 } 614 return NMK_GPIO_ALT_C; 615} 616 617int nmk_gpio_get_mode(int gpio) 618{ 619 struct nmk_gpio_chip *nmk_chip; 620 u32 afunc, bfunc, bit; 621 622 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; 623 if (!nmk_chip) 624 return -EINVAL; 625 626 bit = 1 << (gpio % NMK_GPIO_PER_CHIP); 627 628 clk_enable(nmk_chip->clk); 629 630 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; 631 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; 632 633 clk_disable(nmk_chip->clk); 634 635 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); 636} 637EXPORT_SYMBOL(nmk_gpio_get_mode); 638 639 640/* IRQ functions */ 641static inline int nmk_gpio_get_bitmask(int gpio) 642{ 643 return 1 << (gpio % NMK_GPIO_PER_CHIP); 644} 645 646static void nmk_gpio_irq_ack(struct irq_data *d) 647{ 648 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 649 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 650 651 clk_enable(nmk_chip->clk); 652 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); 653 clk_disable(nmk_chip->clk); 654} 655 656enum nmk_gpio_irq_type { 657 NORMAL, 658 WAKE, 659}; 660 661static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, 662 int gpio, enum nmk_gpio_irq_type which, 663 bool enable) 664{ 665 u32 bitmask = nmk_gpio_get_bitmask(gpio); 666 u32 *rimscval; 667 u32 *fimscval; 668 u32 rimscreg; 669 u32 fimscreg; 670 671 if (which == NORMAL) { 672 rimscreg = NMK_GPIO_RIMSC; 673 fimscreg = NMK_GPIO_FIMSC; 674 rimscval = &nmk_chip->rimsc; 675 fimscval = &nmk_chip->fimsc; 676 } else { 677 rimscreg = NMK_GPIO_RWIMSC; 678 fimscreg = NMK_GPIO_FWIMSC; 679 rimscval = &nmk_chip->rwimsc; 680 fimscval = &nmk_chip->fwimsc; 681 } 682 683 /* we must individually set/clear the two edges */ 684 if (nmk_chip->edge_rising & bitmask) { 685 if (enable) 686 *rimscval |= bitmask; 687 else 688 *rimscval &= ~bitmask; 689 writel(*rimscval, nmk_chip->addr + rimscreg); 690 } 691 if (nmk_chip->edge_falling & bitmask) { 692 if (enable) 693 *fimscval |= bitmask; 694 else 695 *fimscval &= ~bitmask; 696 writel(*fimscval, nmk_chip->addr + fimscreg); 697 } 698} 699 700static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, 701 int gpio, bool on) 702{ 703 /* 704 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is 705 * disabled, since setting SLPM to 1 increases power consumption, and 706 * wakeup is anyhow controlled by the RIMSC and FIMSC registers. 707 */ 708 if (nmk_chip->sleepmode && on) { 709 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, 710 NMK_GPIO_SLPM_WAKEUP_ENABLE); 711 } 712 713 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); 714} 715 716static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) 717{ 718 struct nmk_gpio_chip *nmk_chip; 719 unsigned long flags; 720 u32 bitmask; 721 722 nmk_chip = irq_data_get_irq_chip_data(d); 723 bitmask = nmk_gpio_get_bitmask(d->hwirq); 724 if (!nmk_chip) 725 return -EINVAL; 726 727 clk_enable(nmk_chip->clk); 728 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 729 spin_lock(&nmk_chip->lock); 730 731 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); 732 733 if (!(nmk_chip->real_wake & bitmask)) 734 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); 735 736 spin_unlock(&nmk_chip->lock); 737 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 738 clk_disable(nmk_chip->clk); 739 740 return 0; 741} 742 743static void nmk_gpio_irq_mask(struct irq_data *d) 744{ 745 nmk_gpio_irq_maskunmask(d, false); 746} 747 748static void nmk_gpio_irq_unmask(struct irq_data *d) 749{ 750 nmk_gpio_irq_maskunmask(d, true); 751} 752 753static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 754{ 755 struct nmk_gpio_chip *nmk_chip; 756 unsigned long flags; 757 u32 bitmask; 758 759 nmk_chip = irq_data_get_irq_chip_data(d); 760 if (!nmk_chip) 761 return -EINVAL; 762 bitmask = nmk_gpio_get_bitmask(d->hwirq); 763 764 clk_enable(nmk_chip->clk); 765 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 766 spin_lock(&nmk_chip->lock); 767 768 if (irqd_irq_disabled(d)) 769 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); 770 771 if (on) 772 nmk_chip->real_wake |= bitmask; 773 else 774 nmk_chip->real_wake &= ~bitmask; 775 776 spin_unlock(&nmk_chip->lock); 777 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 778 clk_disable(nmk_chip->clk); 779 780 return 0; 781} 782 783static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) 784{ 785 bool enabled = !irqd_irq_disabled(d); 786 bool wake = irqd_is_wakeup_set(d); 787 struct nmk_gpio_chip *nmk_chip; 788 unsigned long flags; 789 u32 bitmask; 790 791 nmk_chip = irq_data_get_irq_chip_data(d); 792 bitmask = nmk_gpio_get_bitmask(d->hwirq); 793 if (!nmk_chip) 794 return -EINVAL; 795 if (type & IRQ_TYPE_LEVEL_HIGH) 796 return -EINVAL; 797 if (type & IRQ_TYPE_LEVEL_LOW) 798 return -EINVAL; 799 800 clk_enable(nmk_chip->clk); 801 spin_lock_irqsave(&nmk_chip->lock, flags); 802 803 if (enabled) 804 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); 805 806 if (enabled || wake) 807 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); 808 809 nmk_chip->edge_rising &= ~bitmask; 810 if (type & IRQ_TYPE_EDGE_RISING) 811 nmk_chip->edge_rising |= bitmask; 812 813 nmk_chip->edge_falling &= ~bitmask; 814 if (type & IRQ_TYPE_EDGE_FALLING) 815 nmk_chip->edge_falling |= bitmask; 816 817 if (enabled) 818 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); 819 820 if (enabled || wake) 821 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); 822 823 spin_unlock_irqrestore(&nmk_chip->lock, flags); 824 clk_disable(nmk_chip->clk); 825 826 return 0; 827} 828 829static unsigned int nmk_gpio_irq_startup(struct irq_data *d) 830{ 831 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 832 833 clk_enable(nmk_chip->clk); 834 nmk_gpio_irq_unmask(d); 835 return 0; 836} 837 838static void nmk_gpio_irq_shutdown(struct irq_data *d) 839{ 840 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 841 842 nmk_gpio_irq_mask(d); 843 clk_disable(nmk_chip->clk); 844} 845 846static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status) 847{ 848 struct irq_chip *host_chip = irq_desc_get_chip(desc); 849 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 850 851 chained_irq_enter(host_chip, desc); 852 853 while (status) { 854 int bit = __ffs(status); 855 856 generic_handle_irq(irq_find_mapping(chip->irqdomain, bit)); 857 status &= ~BIT(bit); 858 } 859 860 chained_irq_exit(host_chip, desc); 861} 862 863static void nmk_gpio_irq_handler(struct irq_desc *desc) 864{ 865 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 866 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 867 u32 status; 868 869 clk_enable(nmk_chip->clk); 870 status = readl(nmk_chip->addr + NMK_GPIO_IS); 871 clk_disable(nmk_chip->clk); 872 873 __nmk_gpio_irq_handler(desc, status); 874} 875 876static void nmk_gpio_latent_irq_handler(struct irq_desc *desc) 877{ 878 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 879 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 880 u32 status = nmk_chip->get_latent_status(nmk_chip->bank); 881 882 __nmk_gpio_irq_handler(desc, status); 883} 884 885/* I/O Functions */ 886 887static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) 888{ 889 struct nmk_gpio_chip *nmk_chip = 890 container_of(chip, struct nmk_gpio_chip, chip); 891 892 clk_enable(nmk_chip->clk); 893 894 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); 895 896 clk_disable(nmk_chip->clk); 897 898 return 0; 899} 900 901static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) 902{ 903 struct nmk_gpio_chip *nmk_chip = 904 container_of(chip, struct nmk_gpio_chip, chip); 905 u32 bit = 1 << offset; 906 int value; 907 908 clk_enable(nmk_chip->clk); 909 910 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; 911 912 clk_disable(nmk_chip->clk); 913 914 return value; 915} 916 917static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, 918 int val) 919{ 920 struct nmk_gpio_chip *nmk_chip = 921 container_of(chip, struct nmk_gpio_chip, chip); 922 923 clk_enable(nmk_chip->clk); 924 925 __nmk_gpio_set_output(nmk_chip, offset, val); 926 927 clk_disable(nmk_chip->clk); 928} 929 930static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, 931 int val) 932{ 933 struct nmk_gpio_chip *nmk_chip = 934 container_of(chip, struct nmk_gpio_chip, chip); 935 936 clk_enable(nmk_chip->clk); 937 938 __nmk_gpio_make_output(nmk_chip, offset, val); 939 940 clk_disable(nmk_chip->clk); 941 942 return 0; 943} 944 945#ifdef CONFIG_DEBUG_FS 946 947#include <linux/seq_file.h> 948 949static void nmk_gpio_dbg_show_one(struct seq_file *s, 950 struct pinctrl_dev *pctldev, struct gpio_chip *chip, 951 unsigned offset, unsigned gpio) 952{ 953 const char *label = gpiochip_is_requested(chip, offset); 954 struct nmk_gpio_chip *nmk_chip = 955 container_of(chip, struct nmk_gpio_chip, chip); 956 int mode; 957 bool is_out; 958 bool data_out; 959 bool pull; 960 u32 bit = 1 << offset; 961 const char *modes[] = { 962 [NMK_GPIO_ALT_GPIO] = "gpio", 963 [NMK_GPIO_ALT_A] = "altA", 964 [NMK_GPIO_ALT_B] = "altB", 965 [NMK_GPIO_ALT_C] = "altC", 966 [NMK_GPIO_ALT_C+1] = "altC1", 967 [NMK_GPIO_ALT_C+2] = "altC2", 968 [NMK_GPIO_ALT_C+3] = "altC3", 969 [NMK_GPIO_ALT_C+4] = "altC4", 970 }; 971 const char *pulls[] = { 972 "none ", 973 "pull down", 974 "pull up ", 975 }; 976 977 clk_enable(nmk_chip->clk); 978 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); 979 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); 980 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & bit); 981 mode = nmk_gpio_get_mode(gpio); 982 if ((mode == NMK_GPIO_ALT_C) && pctldev) 983 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); 984 985 if (is_out) { 986 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", 987 gpio, 988 label ?: "(none)", 989 data_out ? "hi" : "lo", 990 (mode < 0) ? "unknown" : modes[mode]); 991 } else { 992 int irq = gpio_to_irq(gpio); 993 struct irq_desc *desc = irq_to_desc(irq); 994 int pullidx = 0; 995 int val; 996 997 if (pull) 998 pullidx = data_out ? 2 : 1; 999 1000 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", 1001 gpio, 1002 label ?: "(none)", 1003 pulls[pullidx], 1004 (mode < 0) ? "unknown" : modes[mode]); 1005 1006 val = nmk_gpio_get_input(chip, offset); 1007 seq_printf(s, " VAL %d", val); 1008 1009 /* 1010 * This races with request_irq(), set_irq_type(), 1011 * and set_irq_wake() ... but those are "rare". 1012 */ 1013 if (irq > 0 && desc && desc->action) { 1014 char *trigger; 1015 u32 bitmask = nmk_gpio_get_bitmask(gpio); 1016 1017 if (nmk_chip->edge_rising & bitmask) 1018 trigger = "edge-rising"; 1019 else if (nmk_chip->edge_falling & bitmask) 1020 trigger = "edge-falling"; 1021 else 1022 trigger = "edge-undefined"; 1023 1024 seq_printf(s, " irq-%d %s%s", 1025 irq, trigger, 1026 irqd_is_wakeup_set(&desc->irq_data) 1027 ? " wakeup" : ""); 1028 } 1029 } 1030 clk_disable(nmk_chip->clk); 1031} 1032 1033static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1034{ 1035 unsigned i; 1036 unsigned gpio = chip->base; 1037 1038 for (i = 0; i < chip->ngpio; i++, gpio++) { 1039 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); 1040 seq_printf(s, "\n"); 1041 } 1042} 1043 1044#else 1045static inline void nmk_gpio_dbg_show_one(struct seq_file *s, 1046 struct pinctrl_dev *pctldev, 1047 struct gpio_chip *chip, 1048 unsigned offset, unsigned gpio) 1049{ 1050} 1051#define nmk_gpio_dbg_show NULL 1052#endif 1053 1054void nmk_gpio_clocks_enable(void) 1055{ 1056 int i; 1057 1058 for (i = 0; i < NUM_BANKS; i++) { 1059 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 1060 1061 if (!chip) 1062 continue; 1063 1064 clk_enable(chip->clk); 1065 } 1066} 1067 1068void nmk_gpio_clocks_disable(void) 1069{ 1070 int i; 1071 1072 for (i = 0; i < NUM_BANKS; i++) { 1073 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 1074 1075 if (!chip) 1076 continue; 1077 1078 clk_disable(chip->clk); 1079 } 1080} 1081 1082/* 1083 * Called from the suspend/resume path to only keep the real wakeup interrupts 1084 * (those that have had set_irq_wake() called on them) as wakeup interrupts, 1085 * and not the rest of the interrupts which we needed to have as wakeups for 1086 * cpuidle. 1087 * 1088 * PM ops are not used since this needs to be done at the end, after all the 1089 * other drivers are done with their suspend callbacks. 1090 */ 1091void nmk_gpio_wakeups_suspend(void) 1092{ 1093 int i; 1094 1095 for (i = 0; i < NUM_BANKS; i++) { 1096 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 1097 1098 if (!chip) 1099 break; 1100 1101 clk_enable(chip->clk); 1102 1103 writel(chip->rwimsc & chip->real_wake, 1104 chip->addr + NMK_GPIO_RWIMSC); 1105 writel(chip->fwimsc & chip->real_wake, 1106 chip->addr + NMK_GPIO_FWIMSC); 1107 1108 clk_disable(chip->clk); 1109 } 1110} 1111 1112void nmk_gpio_wakeups_resume(void) 1113{ 1114 int i; 1115 1116 for (i = 0; i < NUM_BANKS; i++) { 1117 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 1118 1119 if (!chip) 1120 break; 1121 1122 clk_enable(chip->clk); 1123 1124 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); 1125 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); 1126 1127 clk_disable(chip->clk); 1128 } 1129} 1130 1131/* 1132 * Read the pull up/pull down status. 1133 * A bit set in 'pull_up' means that pull up 1134 * is selected if pull is enabled in PDIS register. 1135 * Note: only pull up/down set via this driver can 1136 * be detected due to HW limitations. 1137 */ 1138void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) 1139{ 1140 if (gpio_bank < NUM_BANKS) { 1141 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; 1142 1143 if (!chip) 1144 return; 1145 1146 *pull_up = chip->pull_up; 1147 } 1148} 1149 1150/* 1151 * We will allocate memory for the state container using devm* allocators 1152 * binding to the first device reaching this point, it doesn't matter if 1153 * it is the pin controller or GPIO driver. However we need to use the right 1154 * platform device when looking up resources so pay attention to pdev. 1155 */ 1156static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np, 1157 struct platform_device *pdev) 1158{ 1159 struct nmk_gpio_chip *nmk_chip; 1160 struct platform_device *gpio_pdev; 1161 struct gpio_chip *chip; 1162 struct resource *res; 1163 struct clk *clk; 1164 void __iomem *base; 1165 u32 id; 1166 1167 gpio_pdev = of_find_device_by_node(np); 1168 if (!gpio_pdev) { 1169 pr_err("populate \"%s\": device not found\n", np->name); 1170 return ERR_PTR(-ENODEV); 1171 } 1172 if (of_property_read_u32(np, "gpio-bank", &id)) { 1173 dev_err(&pdev->dev, "populate: gpio-bank property not found\n"); 1174 return ERR_PTR(-EINVAL); 1175 } 1176 1177 /* Already populated? */ 1178 nmk_chip = nmk_gpio_chips[id]; 1179 if (nmk_chip) 1180 return nmk_chip; 1181 1182 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL); 1183 if (!nmk_chip) 1184 return ERR_PTR(-ENOMEM); 1185 1186 nmk_chip->bank = id; 1187 chip = &nmk_chip->chip; 1188 chip->base = id * NMK_GPIO_PER_CHIP; 1189 chip->ngpio = NMK_GPIO_PER_CHIP; 1190 chip->label = dev_name(&gpio_pdev->dev); 1191 chip->dev = &gpio_pdev->dev; 1192 1193 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0); 1194 base = devm_ioremap_resource(&pdev->dev, res); 1195 if (IS_ERR(base)) 1196 return base; 1197 nmk_chip->addr = base; 1198 1199 clk = clk_get(&gpio_pdev->dev, NULL); 1200 if (IS_ERR(clk)) 1201 return (void *) clk; 1202 clk_prepare(clk); 1203 nmk_chip->clk = clk; 1204 1205 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); 1206 nmk_gpio_chips[id] = nmk_chip; 1207 return nmk_chip; 1208} 1209 1210static int nmk_gpio_probe(struct platform_device *dev) 1211{ 1212 struct device_node *np = dev->dev.of_node; 1213 struct nmk_gpio_chip *nmk_chip; 1214 struct gpio_chip *chip; 1215 struct irq_chip *irqchip; 1216 int latent_irq; 1217 bool supports_sleepmode; 1218 int irq; 1219 int ret; 1220 1221 nmk_chip = nmk_gpio_populate_chip(np, dev); 1222 if (IS_ERR(nmk_chip)) { 1223 dev_err(&dev->dev, "could not populate nmk chip struct\n"); 1224 return PTR_ERR(nmk_chip); 1225 } 1226 1227 if (of_get_property(np, "st,supports-sleepmode", NULL)) 1228 supports_sleepmode = true; 1229 else 1230 supports_sleepmode = false; 1231 1232 /* Correct platform device ID */ 1233 dev->id = nmk_chip->bank; 1234 1235 irq = platform_get_irq(dev, 0); 1236 if (irq < 0) 1237 return irq; 1238 1239 /* It's OK for this IRQ not to be present */ 1240 latent_irq = platform_get_irq(dev, 1); 1241 1242 /* 1243 * The virt address in nmk_chip->addr is in the nomadik register space, 1244 * so we can simply convert the resource address, without remapping 1245 */ 1246 nmk_chip->parent_irq = irq; 1247 nmk_chip->latent_parent_irq = latent_irq; 1248 nmk_chip->sleepmode = supports_sleepmode; 1249 spin_lock_init(&nmk_chip->lock); 1250 1251 chip = &nmk_chip->chip; 1252 chip->request = gpiochip_generic_request; 1253 chip->free = gpiochip_generic_free; 1254 chip->direction_input = nmk_gpio_make_input; 1255 chip->get = nmk_gpio_get_input; 1256 chip->direction_output = nmk_gpio_make_output; 1257 chip->set = nmk_gpio_set_output; 1258 chip->dbg_show = nmk_gpio_dbg_show; 1259 chip->can_sleep = false; 1260 chip->owner = THIS_MODULE; 1261 1262 irqchip = &nmk_chip->irqchip; 1263 irqchip->irq_ack = nmk_gpio_irq_ack; 1264 irqchip->irq_mask = nmk_gpio_irq_mask; 1265 irqchip->irq_unmask = nmk_gpio_irq_unmask; 1266 irqchip->irq_set_type = nmk_gpio_irq_set_type; 1267 irqchip->irq_set_wake = nmk_gpio_irq_set_wake; 1268 irqchip->irq_startup = nmk_gpio_irq_startup; 1269 irqchip->irq_shutdown = nmk_gpio_irq_shutdown; 1270 irqchip->flags = IRQCHIP_MASK_ON_SUSPEND; 1271 irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u", 1272 dev->id, 1273 chip->base, 1274 chip->base + chip->ngpio - 1); 1275 1276 clk_enable(nmk_chip->clk); 1277 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); 1278 clk_disable(nmk_chip->clk); 1279 chip->of_node = np; 1280 1281 ret = gpiochip_add(chip); 1282 if (ret) 1283 return ret; 1284 1285 platform_set_drvdata(dev, nmk_chip); 1286 1287 /* 1288 * Let the generic code handle this edge IRQ, the the chained 1289 * handler will perform the actual work of handling the parent 1290 * interrupt. 1291 */ 1292 ret = gpiochip_irqchip_add(chip, 1293 irqchip, 1294 0, 1295 handle_edge_irq, 1296 IRQ_TYPE_EDGE_FALLING); 1297 if (ret) { 1298 dev_err(&dev->dev, "could not add irqchip\n"); 1299 gpiochip_remove(&nmk_chip->chip); 1300 return -ENODEV; 1301 } 1302 /* Then register the chain on the parent IRQ */ 1303 gpiochip_set_chained_irqchip(chip, 1304 irqchip, 1305 nmk_chip->parent_irq, 1306 nmk_gpio_irq_handler); 1307 if (nmk_chip->latent_parent_irq > 0) 1308 gpiochip_set_chained_irqchip(chip, 1309 irqchip, 1310 nmk_chip->latent_parent_irq, 1311 nmk_gpio_latent_irq_handler); 1312 1313 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); 1314 1315 return 0; 1316} 1317 1318static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) 1319{ 1320 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1321 1322 return npct->soc->ngroups; 1323} 1324 1325static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, 1326 unsigned selector) 1327{ 1328 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1329 1330 return npct->soc->groups[selector].name; 1331} 1332 1333static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 1334 const unsigned **pins, 1335 unsigned *num_pins) 1336{ 1337 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1338 1339 *pins = npct->soc->groups[selector].pins; 1340 *num_pins = npct->soc->groups[selector].npins; 1341 return 0; 1342} 1343 1344static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin) 1345{ 1346 int i; 1347 struct nmk_gpio_chip *nmk_gpio; 1348 1349 for(i = 0; i < NMK_MAX_BANKS; i++) { 1350 nmk_gpio = nmk_gpio_chips[i]; 1351 if (!nmk_gpio) 1352 continue; 1353 if (pin >= nmk_gpio->chip.base && 1354 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio) 1355 return nmk_gpio; 1356 } 1357 return NULL; 1358} 1359 1360static struct gpio_chip *find_gc_from_pin(unsigned pin) 1361{ 1362 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin); 1363 1364 if (nmk_gpio) 1365 return &nmk_gpio->chip; 1366 return NULL; 1367} 1368 1369static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1370 unsigned offset) 1371{ 1372 struct gpio_chip *chip = find_gc_from_pin(offset); 1373 1374 if (!chip) { 1375 seq_printf(s, "invalid pin offset"); 1376 return; 1377 } 1378 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 1379} 1380 1381static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, 1382 unsigned *num_maps, const char *group, 1383 const char *function) 1384{ 1385 if (*num_maps == *reserved_maps) 1386 return -ENOSPC; 1387 1388 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 1389 (*map)[*num_maps].data.mux.group = group; 1390 (*map)[*num_maps].data.mux.function = function; 1391 (*num_maps)++; 1392 1393 return 0; 1394} 1395 1396static int nmk_dt_add_map_configs(struct pinctrl_map **map, 1397 unsigned *reserved_maps, 1398 unsigned *num_maps, const char *group, 1399 unsigned long *configs, unsigned num_configs) 1400{ 1401 unsigned long *dup_configs; 1402 1403 if (*num_maps == *reserved_maps) 1404 return -ENOSPC; 1405 1406 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 1407 GFP_KERNEL); 1408 if (!dup_configs) 1409 return -ENOMEM; 1410 1411 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; 1412 1413 (*map)[*num_maps].data.configs.group_or_pin = group; 1414 (*map)[*num_maps].data.configs.configs = dup_configs; 1415 (*map)[*num_maps].data.configs.num_configs = num_configs; 1416 (*num_maps)++; 1417 1418 return 0; 1419} 1420 1421#define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } 1422#define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ 1423 .size = ARRAY_SIZE(y), } 1424 1425static const unsigned long nmk_pin_input_modes[] = { 1426 PIN_INPUT_NOPULL, 1427 PIN_INPUT_PULLUP, 1428 PIN_INPUT_PULLDOWN, 1429}; 1430 1431static const unsigned long nmk_pin_output_modes[] = { 1432 PIN_OUTPUT_LOW, 1433 PIN_OUTPUT_HIGH, 1434 PIN_DIR_OUTPUT, 1435}; 1436 1437static const unsigned long nmk_pin_sleep_modes[] = { 1438 PIN_SLEEPMODE_DISABLED, 1439 PIN_SLEEPMODE_ENABLED, 1440}; 1441 1442static const unsigned long nmk_pin_sleep_input_modes[] = { 1443 PIN_SLPM_INPUT_NOPULL, 1444 PIN_SLPM_INPUT_PULLUP, 1445 PIN_SLPM_INPUT_PULLDOWN, 1446 PIN_SLPM_DIR_INPUT, 1447}; 1448 1449static const unsigned long nmk_pin_sleep_output_modes[] = { 1450 PIN_SLPM_OUTPUT_LOW, 1451 PIN_SLPM_OUTPUT_HIGH, 1452 PIN_SLPM_DIR_OUTPUT, 1453}; 1454 1455static const unsigned long nmk_pin_sleep_wakeup_modes[] = { 1456 PIN_SLPM_WAKEUP_DISABLE, 1457 PIN_SLPM_WAKEUP_ENABLE, 1458}; 1459 1460static const unsigned long nmk_pin_gpio_modes[] = { 1461 PIN_GPIOMODE_DISABLED, 1462 PIN_GPIOMODE_ENABLED, 1463}; 1464 1465static const unsigned long nmk_pin_sleep_pdis_modes[] = { 1466 PIN_SLPM_PDIS_DISABLED, 1467 PIN_SLPM_PDIS_ENABLED, 1468}; 1469 1470struct nmk_cfg_param { 1471 const char *property; 1472 unsigned long config; 1473 const unsigned long *choice; 1474 int size; 1475}; 1476 1477static const struct nmk_cfg_param nmk_cfg_params[] = { 1478 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), 1479 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), 1480 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), 1481 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), 1482 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), 1483 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), 1484 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), 1485 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), 1486}; 1487 1488static int nmk_dt_pin_config(int index, int val, unsigned long *config) 1489{ 1490 int ret = 0; 1491 1492 if (nmk_cfg_params[index].choice == NULL) 1493 *config = nmk_cfg_params[index].config; 1494 else { 1495 /* test if out of range */ 1496 if (val < nmk_cfg_params[index].size) { 1497 *config = nmk_cfg_params[index].config | 1498 nmk_cfg_params[index].choice[val]; 1499 } 1500 } 1501 return ret; 1502} 1503 1504static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) 1505{ 1506 int i, pin_number; 1507 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1508 1509 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) 1510 for (i = 0; i < npct->soc->npins; i++) 1511 if (npct->soc->pins[i].number == pin_number) 1512 return npct->soc->pins[i].name; 1513 return NULL; 1514} 1515 1516static bool nmk_pinctrl_dt_get_config(struct device_node *np, 1517 unsigned long *configs) 1518{ 1519 bool has_config = 0; 1520 unsigned long cfg = 0; 1521 int i, val, ret; 1522 1523 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { 1524 ret = of_property_read_u32(np, 1525 nmk_cfg_params[i].property, &val); 1526 if (ret != -EINVAL) { 1527 if (nmk_dt_pin_config(i, val, &cfg) == 0) { 1528 *configs |= cfg; 1529 has_config = 1; 1530 } 1531 } 1532 } 1533 1534 return has_config; 1535} 1536 1537static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 1538 struct device_node *np, 1539 struct pinctrl_map **map, 1540 unsigned *reserved_maps, 1541 unsigned *num_maps) 1542{ 1543 int ret; 1544 const char *function = NULL; 1545 unsigned long configs = 0; 1546 bool has_config = 0; 1547 struct property *prop; 1548 struct device_node *np_config; 1549 1550 ret = of_property_read_string(np, "function", &function); 1551 if (ret >= 0) { 1552 const char *group; 1553 1554 ret = of_property_count_strings(np, "groups"); 1555 if (ret < 0) 1556 goto exit; 1557 1558 ret = pinctrl_utils_reserve_map(pctldev, map, 1559 reserved_maps, 1560 num_maps, ret); 1561 if (ret < 0) 1562 goto exit; 1563 1564 of_property_for_each_string(np, "groups", prop, group) { 1565 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, 1566 group, function); 1567 if (ret < 0) 1568 goto exit; 1569 } 1570 } 1571 1572 has_config = nmk_pinctrl_dt_get_config(np, &configs); 1573 np_config = of_parse_phandle(np, "ste,config", 0); 1574 if (np_config) 1575 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); 1576 if (has_config) { 1577 const char *gpio_name; 1578 const char *pin; 1579 1580 ret = of_property_count_strings(np, "pins"); 1581 if (ret < 0) 1582 goto exit; 1583 ret = pinctrl_utils_reserve_map(pctldev, map, 1584 reserved_maps, 1585 num_maps, ret); 1586 if (ret < 0) 1587 goto exit; 1588 1589 of_property_for_each_string(np, "pins", prop, pin) { 1590 gpio_name = nmk_find_pin_name(pctldev, pin); 1591 1592 ret = nmk_dt_add_map_configs(map, reserved_maps, 1593 num_maps, 1594 gpio_name, &configs, 1); 1595 if (ret < 0) 1596 goto exit; 1597 } 1598 } 1599 1600exit: 1601 return ret; 1602} 1603 1604static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 1605 struct device_node *np_config, 1606 struct pinctrl_map **map, unsigned *num_maps) 1607{ 1608 unsigned reserved_maps; 1609 struct device_node *np; 1610 int ret; 1611 1612 reserved_maps = 0; 1613 *map = NULL; 1614 *num_maps = 0; 1615 1616 for_each_child_of_node(np_config, np) { 1617 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, 1618 &reserved_maps, num_maps); 1619 if (ret < 0) { 1620 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); 1621 return ret; 1622 } 1623 } 1624 1625 return 0; 1626} 1627 1628static const struct pinctrl_ops nmk_pinctrl_ops = { 1629 .get_groups_count = nmk_get_groups_cnt, 1630 .get_group_name = nmk_get_group_name, 1631 .get_group_pins = nmk_get_group_pins, 1632 .pin_dbg_show = nmk_pin_dbg_show, 1633 .dt_node_to_map = nmk_pinctrl_dt_node_to_map, 1634 .dt_free_map = pinctrl_utils_dt_free_map, 1635}; 1636 1637static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 1638{ 1639 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1640 1641 return npct->soc->nfunctions; 1642} 1643 1644static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, 1645 unsigned function) 1646{ 1647 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1648 1649 return npct->soc->functions[function].name; 1650} 1651 1652static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 1653 unsigned function, 1654 const char * const **groups, 1655 unsigned * const num_groups) 1656{ 1657 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1658 1659 *groups = npct->soc->functions[function].groups; 1660 *num_groups = npct->soc->functions[function].ngroups; 1661 1662 return 0; 1663} 1664 1665static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function, 1666 unsigned group) 1667{ 1668 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1669 const struct nmk_pingroup *g; 1670 static unsigned int slpm[NUM_BANKS]; 1671 unsigned long flags = 0; 1672 bool glitch; 1673 int ret = -EINVAL; 1674 int i; 1675 1676 g = &npct->soc->groups[group]; 1677 1678 if (g->altsetting < 0) 1679 return -EINVAL; 1680 1681 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); 1682 1683 /* 1684 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, 1685 * we may pass through an undesired state. In this case we take 1686 * some extra care. 1687 * 1688 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 1689 * - Save SLPM registers (since we have a shadow register in the 1690 * nmk_chip we're using that as backup) 1691 * - Set SLPM=0 for the IOs you want to switch and others to 1 1692 * - Configure the GPIO registers for the IOs that are being switched 1693 * - Set IOFORCE=1 1694 * - Modify the AFLSA/B registers for the IOs that are being switched 1695 * - Set IOFORCE=0 1696 * - Restore SLPM registers 1697 * - Any spurious wake up event during switch sequence to be ignored 1698 * and cleared 1699 * 1700 * We REALLY need to save ALL slpm registers, because the external 1701 * IOFORCE will switch *all* ports to their sleepmode setting to as 1702 * to avoid glitches. (Not just one port!) 1703 */ 1704 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); 1705 1706 if (glitch) { 1707 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 1708 1709 /* Initially don't put any pins to sleep when switching */ 1710 memset(slpm, 0xff, sizeof(slpm)); 1711 1712 /* 1713 * Then mask the pins that need to be sleeping now when we're 1714 * switching to the ALT C function. 1715 */ 1716 for (i = 0; i < g->npins; i++) 1717 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); 1718 nmk_gpio_glitch_slpm_init(slpm); 1719 } 1720 1721 for (i = 0; i < g->npins; i++) { 1722 struct nmk_gpio_chip *nmk_chip; 1723 unsigned bit; 1724 1725 nmk_chip = find_nmk_gpio_from_pin(g->pins[i]); 1726 if (!nmk_chip) { 1727 dev_err(npct->dev, 1728 "invalid pin offset %d in group %s at index %d\n", 1729 g->pins[i], g->name, i); 1730 goto out_glitch; 1731 } 1732 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); 1733 1734 clk_enable(nmk_chip->clk); 1735 bit = g->pins[i] % NMK_GPIO_PER_CHIP; 1736 /* 1737 * If the pin is switching to altfunc, and there was an 1738 * interrupt installed on it which has been lazy disabled, 1739 * actually mask the interrupt to prevent spurious interrupts 1740 * that would occur while the pin is under control of the 1741 * peripheral. Only SKE does this. 1742 */ 1743 nmk_gpio_disable_lazy_irq(nmk_chip, bit); 1744 1745 __nmk_gpio_set_mode_safe(nmk_chip, bit, 1746 (g->altsetting & NMK_GPIO_ALT_C), glitch); 1747 clk_disable(nmk_chip->clk); 1748 1749 /* 1750 * Call PRCM GPIOCR config function in case ALTC 1751 * has been selected: 1752 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers 1753 * must be set. 1754 * - If selection is pure ALTC and previous selection was ALTCx, 1755 * then some bits in PRCM GPIOCR registers must be cleared. 1756 */ 1757 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) 1758 nmk_prcm_altcx_set_mode(npct, g->pins[i], 1759 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); 1760 } 1761 1762 /* When all pins are successfully reconfigured we get here */ 1763 ret = 0; 1764 1765out_glitch: 1766 if (glitch) { 1767 nmk_gpio_glitch_slpm_restore(slpm); 1768 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 1769 } 1770 1771 return ret; 1772} 1773 1774static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, 1775 struct pinctrl_gpio_range *range, 1776 unsigned offset) 1777{ 1778 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1779 struct nmk_gpio_chip *nmk_chip; 1780 struct gpio_chip *chip; 1781 unsigned bit; 1782 1783 if (!range) { 1784 dev_err(npct->dev, "invalid range\n"); 1785 return -EINVAL; 1786 } 1787 if (!range->gc) { 1788 dev_err(npct->dev, "missing GPIO chip in range\n"); 1789 return -EINVAL; 1790 } 1791 chip = range->gc; 1792 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 1793 1794 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 1795 1796 clk_enable(nmk_chip->clk); 1797 bit = offset % NMK_GPIO_PER_CHIP; 1798 /* There is no glitch when converting any pin to GPIO */ 1799 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 1800 clk_disable(nmk_chip->clk); 1801 1802 return 0; 1803} 1804 1805static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, 1806 struct pinctrl_gpio_range *range, 1807 unsigned offset) 1808{ 1809 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1810 1811 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 1812 /* Set the pin to some default state, GPIO is usually default */ 1813} 1814 1815static const struct pinmux_ops nmk_pinmux_ops = { 1816 .get_functions_count = nmk_pmx_get_funcs_cnt, 1817 .get_function_name = nmk_pmx_get_func_name, 1818 .get_function_groups = nmk_pmx_get_func_groups, 1819 .set_mux = nmk_pmx_set, 1820 .gpio_request_enable = nmk_gpio_request_enable, 1821 .gpio_disable_free = nmk_gpio_disable_free, 1822 .strict = true, 1823}; 1824 1825static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 1826 unsigned long *config) 1827{ 1828 /* Not implemented */ 1829 return -EINVAL; 1830} 1831 1832static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 1833 unsigned long *configs, unsigned num_configs) 1834{ 1835 static const char *pullnames[] = { 1836 [NMK_GPIO_PULL_NONE] = "none", 1837 [NMK_GPIO_PULL_UP] = "up", 1838 [NMK_GPIO_PULL_DOWN] = "down", 1839 [3] /* illegal */ = "??" 1840 }; 1841 static const char *slpmnames[] = { 1842 [NMK_GPIO_SLPM_INPUT] = "input/wakeup", 1843 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", 1844 }; 1845 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1846 struct nmk_gpio_chip *nmk_chip; 1847 unsigned bit; 1848 pin_cfg_t cfg; 1849 int pull, slpm, output, val, i; 1850 bool lowemi, gpiomode, sleep; 1851 1852 nmk_chip = find_nmk_gpio_from_pin(pin); 1853 if (!nmk_chip) { 1854 dev_err(npct->dev, 1855 "invalid pin offset %d\n", pin); 1856 return -EINVAL; 1857 } 1858 1859 for (i = 0; i < num_configs; i++) { 1860 /* 1861 * The pin config contains pin number and altfunction fields, 1862 * here we just ignore that part. It's being handled by the 1863 * framework and pinmux callback respectively. 1864 */ 1865 cfg = (pin_cfg_t) configs[i]; 1866 pull = PIN_PULL(cfg); 1867 slpm = PIN_SLPM(cfg); 1868 output = PIN_DIR(cfg); 1869 val = PIN_VAL(cfg); 1870 lowemi = PIN_LOWEMI(cfg); 1871 gpiomode = PIN_GPIOMODE(cfg); 1872 sleep = PIN_SLEEPMODE(cfg); 1873 1874 if (sleep) { 1875 int slpm_pull = PIN_SLPM_PULL(cfg); 1876 int slpm_output = PIN_SLPM_DIR(cfg); 1877 int slpm_val = PIN_SLPM_VAL(cfg); 1878 1879 /* All pins go into GPIO mode at sleep */ 1880 gpiomode = true; 1881 1882 /* 1883 * The SLPM_* values are normal values + 1 to allow zero 1884 * to mean "same as normal". 1885 */ 1886 if (slpm_pull) 1887 pull = slpm_pull - 1; 1888 if (slpm_output) 1889 output = slpm_output - 1; 1890 if (slpm_val) 1891 val = slpm_val - 1; 1892 1893 dev_dbg(nmk_chip->chip.dev, 1894 "pin %d: sleep pull %s, dir %s, val %s\n", 1895 pin, 1896 slpm_pull ? pullnames[pull] : "same", 1897 slpm_output ? (output ? "output" : "input") 1898 : "same", 1899 slpm_val ? (val ? "high" : "low") : "same"); 1900 } 1901 1902 dev_dbg(nmk_chip->chip.dev, 1903 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", 1904 pin, cfg, pullnames[pull], slpmnames[slpm], 1905 output ? "output " : "input", 1906 output ? (val ? "high" : "low") : "", 1907 lowemi ? "on" : "off"); 1908 1909 clk_enable(nmk_chip->clk); 1910 bit = pin % NMK_GPIO_PER_CHIP; 1911 if (gpiomode) 1912 /* No glitch when going to GPIO mode */ 1913 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 1914 if (output) 1915 __nmk_gpio_make_output(nmk_chip, bit, val); 1916 else { 1917 __nmk_gpio_make_input(nmk_chip, bit); 1918 __nmk_gpio_set_pull(nmk_chip, bit, pull); 1919 } 1920 /* TODO: isn't this only applicable on output pins? */ 1921 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); 1922 1923 __nmk_gpio_set_slpm(nmk_chip, bit, slpm); 1924 clk_disable(nmk_chip->clk); 1925 } /* for each config */ 1926 1927 return 0; 1928} 1929 1930static const struct pinconf_ops nmk_pinconf_ops = { 1931 .pin_config_get = nmk_pin_config_get, 1932 .pin_config_set = nmk_pin_config_set, 1933}; 1934 1935static struct pinctrl_desc nmk_pinctrl_desc = { 1936 .name = "pinctrl-nomadik", 1937 .pctlops = &nmk_pinctrl_ops, 1938 .pmxops = &nmk_pinmux_ops, 1939 .confops = &nmk_pinconf_ops, 1940 .owner = THIS_MODULE, 1941}; 1942 1943static const struct of_device_id nmk_pinctrl_match[] = { 1944 { 1945 .compatible = "stericsson,stn8815-pinctrl", 1946 .data = (void *)PINCTRL_NMK_STN8815, 1947 }, 1948 { 1949 .compatible = "stericsson,db8500-pinctrl", 1950 .data = (void *)PINCTRL_NMK_DB8500, 1951 }, 1952 { 1953 .compatible = "stericsson,db8540-pinctrl", 1954 .data = (void *)PINCTRL_NMK_DB8540, 1955 }, 1956 {}, 1957}; 1958 1959#ifdef CONFIG_PM_SLEEP 1960static int nmk_pinctrl_suspend(struct device *dev) 1961{ 1962 struct nmk_pinctrl *npct; 1963 1964 npct = dev_get_drvdata(dev); 1965 if (!npct) 1966 return -EINVAL; 1967 1968 return pinctrl_force_sleep(npct->pctl); 1969} 1970 1971static int nmk_pinctrl_resume(struct device *dev) 1972{ 1973 struct nmk_pinctrl *npct; 1974 1975 npct = dev_get_drvdata(dev); 1976 if (!npct) 1977 return -EINVAL; 1978 1979 return pinctrl_force_default(npct->pctl); 1980} 1981#endif 1982 1983static int nmk_pinctrl_probe(struct platform_device *pdev) 1984{ 1985 const struct of_device_id *match; 1986 struct device_node *np = pdev->dev.of_node; 1987 struct device_node *prcm_np; 1988 struct nmk_pinctrl *npct; 1989 unsigned int version = 0; 1990 int i; 1991 1992 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); 1993 if (!npct) 1994 return -ENOMEM; 1995 1996 match = of_match_device(nmk_pinctrl_match, &pdev->dev); 1997 if (!match) 1998 return -ENODEV; 1999 version = (unsigned int) match->data; 2000 2001 /* Poke in other ASIC variants here */ 2002 if (version == PINCTRL_NMK_STN8815) 2003 nmk_pinctrl_stn8815_init(&npct->soc); 2004 if (version == PINCTRL_NMK_DB8500) 2005 nmk_pinctrl_db8500_init(&npct->soc); 2006 if (version == PINCTRL_NMK_DB8540) 2007 nmk_pinctrl_db8540_init(&npct->soc); 2008 2009 /* 2010 * Since we depend on the GPIO chips to provide clock and register base 2011 * for the pin control operations, make sure that we have these 2012 * populated before we continue. Follow the phandles to instantiate 2013 * them. The GPIO portion of the actual hardware may be probed before 2014 * or after this point: it shouldn't matter as the APIs are orthogonal. 2015 */ 2016 for (i = 0; i < NMK_MAX_BANKS; i++) { 2017 struct device_node *gpio_np; 2018 struct nmk_gpio_chip *nmk_chip; 2019 2020 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i); 2021 if (gpio_np) { 2022 dev_info(&pdev->dev, 2023 "populate NMK GPIO %d \"%s\"\n", 2024 i, gpio_np->name); 2025 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev); 2026 if (IS_ERR(nmk_chip)) 2027 dev_err(&pdev->dev, 2028 "could not populate nmk chip struct " 2029 "- continue anyway\n"); 2030 of_node_put(gpio_np); 2031 } 2032 } 2033 2034 prcm_np = of_parse_phandle(np, "prcm", 0); 2035 if (prcm_np) 2036 npct->prcm_base = of_iomap(prcm_np, 0); 2037 if (!npct->prcm_base) { 2038 if (version == PINCTRL_NMK_STN8815) { 2039 dev_info(&pdev->dev, 2040 "No PRCM base, " 2041 "assuming no ALT-Cx control is available\n"); 2042 } else { 2043 dev_err(&pdev->dev, "missing PRCM base address\n"); 2044 return -EINVAL; 2045 } 2046 } 2047 2048 nmk_pinctrl_desc.pins = npct->soc->pins; 2049 nmk_pinctrl_desc.npins = npct->soc->npins; 2050 npct->dev = &pdev->dev; 2051 2052 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); 2053 if (IS_ERR(npct->pctl)) { 2054 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); 2055 return PTR_ERR(npct->pctl); 2056 } 2057 2058 platform_set_drvdata(pdev, npct); 2059 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); 2060 2061 return 0; 2062} 2063 2064static const struct of_device_id nmk_gpio_match[] = { 2065 { .compatible = "st,nomadik-gpio", }, 2066 {} 2067}; 2068 2069static struct platform_driver nmk_gpio_driver = { 2070 .driver = { 2071 .name = "gpio", 2072 .of_match_table = nmk_gpio_match, 2073 }, 2074 .probe = nmk_gpio_probe, 2075}; 2076 2077static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, 2078 nmk_pinctrl_suspend, 2079 nmk_pinctrl_resume); 2080 2081static struct platform_driver nmk_pinctrl_driver = { 2082 .driver = { 2083 .name = "pinctrl-nomadik", 2084 .of_match_table = nmk_pinctrl_match, 2085 .pm = &nmk_pinctrl_pm_ops, 2086 }, 2087 .probe = nmk_pinctrl_probe, 2088}; 2089 2090static int __init nmk_gpio_init(void) 2091{ 2092 return platform_driver_register(&nmk_gpio_driver); 2093} 2094subsys_initcall(nmk_gpio_init); 2095 2096static int __init nmk_pinctrl_init(void) 2097{ 2098 return platform_driver_register(&nmk_pinctrl_driver); 2099} 2100core_initcall(nmk_pinctrl_init); 2101 2102MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); 2103MODULE_DESCRIPTION("Nomadik GPIO Driver"); 2104MODULE_LICENSE("GPL"); 2105