1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <asm-generic/pci-bridge.h>
19 #include "pci.h"
20
21 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
22 #define CARDBUS_RESERVE_BUSNR 3
23
24 static struct resource busn_resource = {
25 .name = "PCI busn",
26 .start = 0,
27 .end = 255,
28 .flags = IORESOURCE_BUS,
29 };
30
31 /* Ugh. Need to stop exporting this to modules. */
32 LIST_HEAD(pci_root_buses);
33 EXPORT_SYMBOL(pci_root_buses);
34
35 static LIST_HEAD(pci_domain_busn_res_list);
36
37 struct pci_domain_busn_res {
38 struct list_head list;
39 struct resource res;
40 int domain_nr;
41 };
42
get_pci_domain_busn_res(int domain_nr)43 static struct resource *get_pci_domain_busn_res(int domain_nr)
44 {
45 struct pci_domain_busn_res *r;
46
47 list_for_each_entry(r, &pci_domain_busn_res_list, list)
48 if (r->domain_nr == domain_nr)
49 return &r->res;
50
51 r = kzalloc(sizeof(*r), GFP_KERNEL);
52 if (!r)
53 return NULL;
54
55 r->domain_nr = domain_nr;
56 r->res.start = 0;
57 r->res.end = 0xff;
58 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
59
60 list_add_tail(&r->list, &pci_domain_busn_res_list);
61
62 return &r->res;
63 }
64
find_anything(struct device * dev,void * data)65 static int find_anything(struct device *dev, void *data)
66 {
67 return 1;
68 }
69
70 /*
71 * Some device drivers need know if pci is initiated.
72 * Basically, we think pci is not initiated when there
73 * is no device to be found on the pci_bus_type.
74 */
no_pci_devices(void)75 int no_pci_devices(void)
76 {
77 struct device *dev;
78 int no_devices;
79
80 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
81 no_devices = (dev == NULL);
82 put_device(dev);
83 return no_devices;
84 }
85 EXPORT_SYMBOL(no_pci_devices);
86
87 /*
88 * PCI Bus Class
89 */
release_pcibus_dev(struct device * dev)90 static void release_pcibus_dev(struct device *dev)
91 {
92 struct pci_bus *pci_bus = to_pci_bus(dev);
93
94 put_device(pci_bus->bridge);
95 pci_bus_remove_resources(pci_bus);
96 pci_release_bus_of_node(pci_bus);
97 kfree(pci_bus);
98 }
99
100 static struct class pcibus_class = {
101 .name = "pci_bus",
102 .dev_release = &release_pcibus_dev,
103 .dev_groups = pcibus_groups,
104 };
105
pcibus_class_init(void)106 static int __init pcibus_class_init(void)
107 {
108 return class_register(&pcibus_class);
109 }
110 postcore_initcall(pcibus_class_init);
111
pci_size(u64 base,u64 maxbase,u64 mask)112 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
113 {
114 u64 size = mask & maxbase; /* Find the significant bits */
115 if (!size)
116 return 0;
117
118 /* Get the lowest of them to find the decode size, and
119 from that the extent. */
120 size = (size & ~(size-1)) - 1;
121
122 /* base == maxbase can be valid only if the BAR has
123 already been programmed with all 1s. */
124 if (base == maxbase && ((base | size) & mask) != mask)
125 return 0;
126
127 return size;
128 }
129
decode_bar(struct pci_dev * dev,u32 bar)130 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
131 {
132 u32 mem_type;
133 unsigned long flags;
134
135 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
136 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
137 flags |= IORESOURCE_IO;
138 return flags;
139 }
140
141 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
142 flags |= IORESOURCE_MEM;
143 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
144 flags |= IORESOURCE_PREFETCH;
145
146 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
147 switch (mem_type) {
148 case PCI_BASE_ADDRESS_MEM_TYPE_32:
149 break;
150 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
151 /* 1M mem BAR treated as 32-bit BAR */
152 break;
153 case PCI_BASE_ADDRESS_MEM_TYPE_64:
154 flags |= IORESOURCE_MEM_64;
155 break;
156 default:
157 /* mem unknown type treated as 32-bit BAR */
158 break;
159 }
160 return flags;
161 }
162
163 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
164
165 /**
166 * pci_read_base - read a PCI BAR
167 * @dev: the PCI device
168 * @type: type of the BAR
169 * @res: resource buffer to be filled in
170 * @pos: BAR position in the config space
171 *
172 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
173 */
__pci_read_base(struct pci_dev * dev,enum pci_bar_type type,struct resource * res,unsigned int pos)174 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
175 struct resource *res, unsigned int pos)
176 {
177 u32 l, sz, mask;
178 u64 l64, sz64, mask64;
179 u16 orig_cmd;
180 struct pci_bus_region region, inverted_region;
181
182 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
183
184 /* No printks while decoding is disabled! */
185 if (!dev->mmio_always_on) {
186 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
187 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
188 pci_write_config_word(dev, PCI_COMMAND,
189 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
190 }
191 }
192
193 res->name = pci_name(dev);
194
195 pci_read_config_dword(dev, pos, &l);
196 pci_write_config_dword(dev, pos, l | mask);
197 pci_read_config_dword(dev, pos, &sz);
198 pci_write_config_dword(dev, pos, l);
199
200 /*
201 * All bits set in sz means the device isn't working properly.
202 * If the BAR isn't implemented, all bits must be 0. If it's a
203 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
204 * 1 must be clear.
205 */
206 if (sz == 0xffffffff)
207 sz = 0;
208
209 /*
210 * I don't know how l can have all bits set. Copied from old code.
211 * Maybe it fixes a bug on some ancient platform.
212 */
213 if (l == 0xffffffff)
214 l = 0;
215
216 if (type == pci_bar_unknown) {
217 res->flags = decode_bar(dev, l);
218 res->flags |= IORESOURCE_SIZEALIGN;
219 if (res->flags & IORESOURCE_IO) {
220 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
221 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
222 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
223 } else {
224 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
225 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
226 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
227 }
228 } else {
229 res->flags |= (l & IORESOURCE_ROM_ENABLE);
230 l64 = l & PCI_ROM_ADDRESS_MASK;
231 sz64 = sz & PCI_ROM_ADDRESS_MASK;
232 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
233 }
234
235 if (res->flags & IORESOURCE_MEM_64) {
236 pci_read_config_dword(dev, pos + 4, &l);
237 pci_write_config_dword(dev, pos + 4, ~0);
238 pci_read_config_dword(dev, pos + 4, &sz);
239 pci_write_config_dword(dev, pos + 4, l);
240
241 l64 |= ((u64)l << 32);
242 sz64 |= ((u64)sz << 32);
243 mask64 |= ((u64)~0 << 32);
244 }
245
246 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
247 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
248
249 if (!sz64)
250 goto fail;
251
252 sz64 = pci_size(l64, sz64, mask64);
253 if (!sz64) {
254 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
255 pos);
256 goto fail;
257 }
258
259 if (res->flags & IORESOURCE_MEM_64) {
260 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
261 && sz64 > 0x100000000ULL) {
262 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
263 res->start = 0;
264 res->end = 0;
265 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
266 pos, (unsigned long long)sz64);
267 goto out;
268 }
269
270 if ((sizeof(pci_bus_addr_t) < 8) && l) {
271 /* Above 32-bit boundary; try to reallocate */
272 res->flags |= IORESOURCE_UNSET;
273 res->start = 0;
274 res->end = sz64;
275 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
276 pos, (unsigned long long)l64);
277 goto out;
278 }
279 }
280
281 region.start = l64;
282 region.end = l64 + sz64;
283
284 pcibios_bus_to_resource(dev->bus, res, ®ion);
285 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
286
287 /*
288 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
289 * the corresponding resource address (the physical address used by
290 * the CPU. Converting that resource address back to a bus address
291 * should yield the original BAR value:
292 *
293 * resource_to_bus(bus_to_resource(A)) == A
294 *
295 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
296 * be claimed by the device.
297 */
298 if (inverted_region.start != region.start) {
299 res->flags |= IORESOURCE_UNSET;
300 res->start = 0;
301 res->end = region.end - region.start;
302 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
303 pos, (unsigned long long)region.start);
304 }
305
306 goto out;
307
308
309 fail:
310 res->flags = 0;
311 out:
312 if (res->flags)
313 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
314
315 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
316 }
317
pci_read_bases(struct pci_dev * dev,unsigned int howmany,int rom)318 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
319 {
320 unsigned int pos, reg;
321
322 if (dev->non_compliant_bars)
323 return;
324
325 for (pos = 0; pos < howmany; pos++) {
326 struct resource *res = &dev->resource[pos];
327 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
328 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
329 }
330
331 if (rom) {
332 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
333 dev->rom_base_reg = rom;
334 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
335 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
336 __pci_read_base(dev, pci_bar_mem32, res, rom);
337 }
338 }
339
pci_read_bridge_io(struct pci_bus * child)340 static void pci_read_bridge_io(struct pci_bus *child)
341 {
342 struct pci_dev *dev = child->self;
343 u8 io_base_lo, io_limit_lo;
344 unsigned long io_mask, io_granularity, base, limit;
345 struct pci_bus_region region;
346 struct resource *res;
347
348 io_mask = PCI_IO_RANGE_MASK;
349 io_granularity = 0x1000;
350 if (dev->io_window_1k) {
351 /* Support 1K I/O space granularity */
352 io_mask = PCI_IO_1K_RANGE_MASK;
353 io_granularity = 0x400;
354 }
355
356 res = child->resource[0];
357 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
358 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
359 base = (io_base_lo & io_mask) << 8;
360 limit = (io_limit_lo & io_mask) << 8;
361
362 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
363 u16 io_base_hi, io_limit_hi;
364
365 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
366 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
367 base |= ((unsigned long) io_base_hi << 16);
368 limit |= ((unsigned long) io_limit_hi << 16);
369 }
370
371 if (base <= limit) {
372 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
373 region.start = base;
374 region.end = limit + io_granularity - 1;
375 pcibios_bus_to_resource(dev->bus, res, ®ion);
376 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
377 }
378 }
379
pci_read_bridge_mmio(struct pci_bus * child)380 static void pci_read_bridge_mmio(struct pci_bus *child)
381 {
382 struct pci_dev *dev = child->self;
383 u16 mem_base_lo, mem_limit_lo;
384 unsigned long base, limit;
385 struct pci_bus_region region;
386 struct resource *res;
387
388 res = child->resource[1];
389 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
390 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
391 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
392 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
393 if (base <= limit) {
394 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
395 region.start = base;
396 region.end = limit + 0xfffff;
397 pcibios_bus_to_resource(dev->bus, res, ®ion);
398 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
399 }
400 }
401
pci_read_bridge_mmio_pref(struct pci_bus * child)402 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
403 {
404 struct pci_dev *dev = child->self;
405 u16 mem_base_lo, mem_limit_lo;
406 u64 base64, limit64;
407 pci_bus_addr_t base, limit;
408 struct pci_bus_region region;
409 struct resource *res;
410
411 res = child->resource[2];
412 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
413 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
414 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
415 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
416
417 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
418 u32 mem_base_hi, mem_limit_hi;
419
420 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
421 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
422
423 /*
424 * Some bridges set the base > limit by default, and some
425 * (broken) BIOSes do not initialize them. If we find
426 * this, just assume they are not being used.
427 */
428 if (mem_base_hi <= mem_limit_hi) {
429 base64 |= (u64) mem_base_hi << 32;
430 limit64 |= (u64) mem_limit_hi << 32;
431 }
432 }
433
434 base = (pci_bus_addr_t) base64;
435 limit = (pci_bus_addr_t) limit64;
436
437 if (base != base64) {
438 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
439 (unsigned long long) base64);
440 return;
441 }
442
443 if (base <= limit) {
444 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
445 IORESOURCE_MEM | IORESOURCE_PREFETCH;
446 if (res->flags & PCI_PREF_RANGE_TYPE_64)
447 res->flags |= IORESOURCE_MEM_64;
448 region.start = base;
449 region.end = limit + 0xfffff;
450 pcibios_bus_to_resource(dev->bus, res, ®ion);
451 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
452 }
453 }
454
pci_read_bridge_bases(struct pci_bus * child)455 void pci_read_bridge_bases(struct pci_bus *child)
456 {
457 struct pci_dev *dev = child->self;
458 struct resource *res;
459 int i;
460
461 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
462 return;
463
464 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
465 &child->busn_res,
466 dev->transparent ? " (subtractive decode)" : "");
467
468 pci_bus_remove_resources(child);
469 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
470 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
471
472 pci_read_bridge_io(child);
473 pci_read_bridge_mmio(child);
474 pci_read_bridge_mmio_pref(child);
475
476 if (dev->transparent) {
477 pci_bus_for_each_resource(child->parent, res, i) {
478 if (res && res->flags) {
479 pci_bus_add_resource(child, res,
480 PCI_SUBTRACTIVE_DECODE);
481 dev_printk(KERN_DEBUG, &dev->dev,
482 " bridge window %pR (subtractive decode)\n",
483 res);
484 }
485 }
486 }
487 }
488
pci_alloc_bus(struct pci_bus * parent)489 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
490 {
491 struct pci_bus *b;
492
493 b = kzalloc(sizeof(*b), GFP_KERNEL);
494 if (!b)
495 return NULL;
496
497 INIT_LIST_HEAD(&b->node);
498 INIT_LIST_HEAD(&b->children);
499 INIT_LIST_HEAD(&b->devices);
500 INIT_LIST_HEAD(&b->slots);
501 INIT_LIST_HEAD(&b->resources);
502 b->max_bus_speed = PCI_SPEED_UNKNOWN;
503 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
504 #ifdef CONFIG_PCI_DOMAINS_GENERIC
505 if (parent)
506 b->domain_nr = parent->domain_nr;
507 #endif
508 return b;
509 }
510
pci_release_host_bridge_dev(struct device * dev)511 static void pci_release_host_bridge_dev(struct device *dev)
512 {
513 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
514
515 if (bridge->release_fn)
516 bridge->release_fn(bridge);
517
518 pci_free_resource_list(&bridge->windows);
519
520 kfree(bridge);
521 }
522
pci_alloc_host_bridge(struct pci_bus * b)523 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
524 {
525 struct pci_host_bridge *bridge;
526
527 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
528 if (!bridge)
529 return NULL;
530
531 INIT_LIST_HEAD(&bridge->windows);
532 bridge->bus = b;
533 return bridge;
534 }
535
536 static const unsigned char pcix_bus_speed[] = {
537 PCI_SPEED_UNKNOWN, /* 0 */
538 PCI_SPEED_66MHz_PCIX, /* 1 */
539 PCI_SPEED_100MHz_PCIX, /* 2 */
540 PCI_SPEED_133MHz_PCIX, /* 3 */
541 PCI_SPEED_UNKNOWN, /* 4 */
542 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
543 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
544 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
545 PCI_SPEED_UNKNOWN, /* 8 */
546 PCI_SPEED_66MHz_PCIX_266, /* 9 */
547 PCI_SPEED_100MHz_PCIX_266, /* A */
548 PCI_SPEED_133MHz_PCIX_266, /* B */
549 PCI_SPEED_UNKNOWN, /* C */
550 PCI_SPEED_66MHz_PCIX_533, /* D */
551 PCI_SPEED_100MHz_PCIX_533, /* E */
552 PCI_SPEED_133MHz_PCIX_533 /* F */
553 };
554
555 const unsigned char pcie_link_speed[] = {
556 PCI_SPEED_UNKNOWN, /* 0 */
557 PCIE_SPEED_2_5GT, /* 1 */
558 PCIE_SPEED_5_0GT, /* 2 */
559 PCIE_SPEED_8_0GT, /* 3 */
560 PCI_SPEED_UNKNOWN, /* 4 */
561 PCI_SPEED_UNKNOWN, /* 5 */
562 PCI_SPEED_UNKNOWN, /* 6 */
563 PCI_SPEED_UNKNOWN, /* 7 */
564 PCI_SPEED_UNKNOWN, /* 8 */
565 PCI_SPEED_UNKNOWN, /* 9 */
566 PCI_SPEED_UNKNOWN, /* A */
567 PCI_SPEED_UNKNOWN, /* B */
568 PCI_SPEED_UNKNOWN, /* C */
569 PCI_SPEED_UNKNOWN, /* D */
570 PCI_SPEED_UNKNOWN, /* E */
571 PCI_SPEED_UNKNOWN /* F */
572 };
573
pcie_update_link_speed(struct pci_bus * bus,u16 linksta)574 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
575 {
576 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
577 }
578 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
579
580 static unsigned char agp_speeds[] = {
581 AGP_UNKNOWN,
582 AGP_1X,
583 AGP_2X,
584 AGP_4X,
585 AGP_8X
586 };
587
agp_speed(int agp3,int agpstat)588 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
589 {
590 int index = 0;
591
592 if (agpstat & 4)
593 index = 3;
594 else if (agpstat & 2)
595 index = 2;
596 else if (agpstat & 1)
597 index = 1;
598 else
599 goto out;
600
601 if (agp3) {
602 index += 2;
603 if (index == 5)
604 index = 0;
605 }
606
607 out:
608 return agp_speeds[index];
609 }
610
pci_set_bus_speed(struct pci_bus * bus)611 static void pci_set_bus_speed(struct pci_bus *bus)
612 {
613 struct pci_dev *bridge = bus->self;
614 int pos;
615
616 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
617 if (!pos)
618 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
619 if (pos) {
620 u32 agpstat, agpcmd;
621
622 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
623 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
624
625 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
626 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
627 }
628
629 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
630 if (pos) {
631 u16 status;
632 enum pci_bus_speed max;
633
634 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
635 &status);
636
637 if (status & PCI_X_SSTATUS_533MHZ) {
638 max = PCI_SPEED_133MHz_PCIX_533;
639 } else if (status & PCI_X_SSTATUS_266MHZ) {
640 max = PCI_SPEED_133MHz_PCIX_266;
641 } else if (status & PCI_X_SSTATUS_133MHZ) {
642 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
643 max = PCI_SPEED_133MHz_PCIX_ECC;
644 else
645 max = PCI_SPEED_133MHz_PCIX;
646 } else {
647 max = PCI_SPEED_66MHz_PCIX;
648 }
649
650 bus->max_bus_speed = max;
651 bus->cur_bus_speed = pcix_bus_speed[
652 (status & PCI_X_SSTATUS_FREQ) >> 6];
653
654 return;
655 }
656
657 if (pci_is_pcie(bridge)) {
658 u32 linkcap;
659 u16 linksta;
660
661 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
662 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
663
664 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
665 pcie_update_link_speed(bus, linksta);
666 }
667 }
668
pci_host_bridge_msi_domain(struct pci_bus * bus)669 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
670 {
671 struct irq_domain *d;
672
673 /*
674 * Any firmware interface that can resolve the msi_domain
675 * should be called from here.
676 */
677 d = pci_host_bridge_of_msi_domain(bus);
678
679 return d;
680 }
681
pci_set_bus_msi_domain(struct pci_bus * bus)682 static void pci_set_bus_msi_domain(struct pci_bus *bus)
683 {
684 struct irq_domain *d;
685 struct pci_bus *b;
686
687 /*
688 * The bus can be a root bus, a subordinate bus, or a virtual bus
689 * created by an SR-IOV device. Walk up to the first bridge device
690 * found or derive the domain from the host bridge.
691 */
692 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
693 if (b->self)
694 d = dev_get_msi_domain(&b->self->dev);
695 }
696
697 if (!d)
698 d = pci_host_bridge_msi_domain(b);
699
700 dev_set_msi_domain(&bus->dev, d);
701 }
702
pci_alloc_child_bus(struct pci_bus * parent,struct pci_dev * bridge,int busnr)703 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
704 struct pci_dev *bridge, int busnr)
705 {
706 struct pci_bus *child;
707 int i;
708 int ret;
709
710 /*
711 * Allocate a new bus, and inherit stuff from the parent..
712 */
713 child = pci_alloc_bus(parent);
714 if (!child)
715 return NULL;
716
717 child->parent = parent;
718 child->ops = parent->ops;
719 child->msi = parent->msi;
720 child->sysdata = parent->sysdata;
721 child->bus_flags = parent->bus_flags;
722
723 /* initialize some portions of the bus device, but don't register it
724 * now as the parent is not properly set up yet.
725 */
726 child->dev.class = &pcibus_class;
727 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
728
729 /*
730 * Set up the primary, secondary and subordinate
731 * bus numbers.
732 */
733 child->number = child->busn_res.start = busnr;
734 child->primary = parent->busn_res.start;
735 child->busn_res.end = 0xff;
736
737 if (!bridge) {
738 child->dev.parent = parent->bridge;
739 goto add_dev;
740 }
741
742 child->self = bridge;
743 child->bridge = get_device(&bridge->dev);
744 child->dev.parent = child->bridge;
745 pci_set_bus_of_node(child);
746 pci_set_bus_speed(child);
747
748 /* Set up default resource pointers and names.. */
749 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
750 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
751 child->resource[i]->name = child->name;
752 }
753 bridge->subordinate = child;
754
755 add_dev:
756 pci_set_bus_msi_domain(child);
757 ret = device_register(&child->dev);
758 WARN_ON(ret < 0);
759
760 pcibios_add_bus(child);
761
762 /* Create legacy_io and legacy_mem files for this bus */
763 pci_create_legacy_files(child);
764
765 return child;
766 }
767
pci_add_new_bus(struct pci_bus * parent,struct pci_dev * dev,int busnr)768 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
769 int busnr)
770 {
771 struct pci_bus *child;
772
773 child = pci_alloc_child_bus(parent, dev, busnr);
774 if (child) {
775 down_write(&pci_bus_sem);
776 list_add_tail(&child->node, &parent->children);
777 up_write(&pci_bus_sem);
778 }
779 return child;
780 }
781 EXPORT_SYMBOL(pci_add_new_bus);
782
pci_enable_crs(struct pci_dev * pdev)783 static void pci_enable_crs(struct pci_dev *pdev)
784 {
785 u16 root_cap = 0;
786
787 /* Enable CRS Software Visibility if supported */
788 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
789 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
790 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
791 PCI_EXP_RTCTL_CRSSVE);
792 }
793
794 /*
795 * If it's a bridge, configure it and scan the bus behind it.
796 * For CardBus bridges, we don't scan behind as the devices will
797 * be handled by the bridge driver itself.
798 *
799 * We need to process bridges in two passes -- first we scan those
800 * already configured by the BIOS and after we are done with all of
801 * them, we proceed to assigning numbers to the remaining buses in
802 * order to avoid overlaps between old and new bus numbers.
803 */
pci_scan_bridge(struct pci_bus * bus,struct pci_dev * dev,int max,int pass)804 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
805 {
806 struct pci_bus *child;
807 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
808 u32 buses, i, j = 0;
809 u16 bctl;
810 u8 primary, secondary, subordinate;
811 int broken = 0;
812
813 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
814 primary = buses & 0xFF;
815 secondary = (buses >> 8) & 0xFF;
816 subordinate = (buses >> 16) & 0xFF;
817
818 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
819 secondary, subordinate, pass);
820
821 if (!primary && (primary != bus->number) && secondary && subordinate) {
822 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
823 primary = bus->number;
824 }
825
826 /* Check if setup is sensible at all */
827 if (!pass &&
828 (primary != bus->number || secondary <= bus->number ||
829 secondary > subordinate)) {
830 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
831 secondary, subordinate);
832 broken = 1;
833 }
834
835 /* Disable MasterAbortMode during probing to avoid reporting
836 of bus errors (in some architectures) */
837 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
838 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
839 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
840
841 pci_enable_crs(dev);
842
843 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
844 !is_cardbus && !broken) {
845 unsigned int cmax;
846 /*
847 * Bus already configured by firmware, process it in the first
848 * pass and just note the configuration.
849 */
850 if (pass)
851 goto out;
852
853 /*
854 * The bus might already exist for two reasons: Either we are
855 * rescanning the bus or the bus is reachable through more than
856 * one bridge. The second case can happen with the i450NX
857 * chipset.
858 */
859 child = pci_find_bus(pci_domain_nr(bus), secondary);
860 if (!child) {
861 child = pci_add_new_bus(bus, dev, secondary);
862 if (!child)
863 goto out;
864 child->primary = primary;
865 pci_bus_insert_busn_res(child, secondary, subordinate);
866 child->bridge_ctl = bctl;
867 }
868
869 cmax = pci_scan_child_bus(child);
870 if (cmax > subordinate)
871 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
872 subordinate, cmax);
873 /* subordinate should equal child->busn_res.end */
874 if (subordinate > max)
875 max = subordinate;
876 } else {
877 /*
878 * We need to assign a number to this bus which we always
879 * do in the second pass.
880 */
881 if (!pass) {
882 if (pcibios_assign_all_busses() || broken || is_cardbus)
883 /* Temporarily disable forwarding of the
884 configuration cycles on all bridges in
885 this bus segment to avoid possible
886 conflicts in the second pass between two
887 bridges programmed with overlapping
888 bus ranges. */
889 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
890 buses & ~0xffffff);
891 goto out;
892 }
893
894 /* Clear errors */
895 pci_write_config_word(dev, PCI_STATUS, 0xffff);
896
897 /* Prevent assigning a bus number that already exists.
898 * This can happen when a bridge is hot-plugged, so in
899 * this case we only re-scan this bus. */
900 child = pci_find_bus(pci_domain_nr(bus), max+1);
901 if (!child) {
902 child = pci_add_new_bus(bus, dev, max+1);
903 if (!child)
904 goto out;
905 pci_bus_insert_busn_res(child, max+1, 0xff);
906 }
907 max++;
908 buses = (buses & 0xff000000)
909 | ((unsigned int)(child->primary) << 0)
910 | ((unsigned int)(child->busn_res.start) << 8)
911 | ((unsigned int)(child->busn_res.end) << 16);
912
913 /*
914 * yenta.c forces a secondary latency timer of 176.
915 * Copy that behaviour here.
916 */
917 if (is_cardbus) {
918 buses &= ~0xff000000;
919 buses |= CARDBUS_LATENCY_TIMER << 24;
920 }
921
922 /*
923 * We need to blast all three values with a single write.
924 */
925 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
926
927 if (!is_cardbus) {
928 child->bridge_ctl = bctl;
929 max = pci_scan_child_bus(child);
930 } else {
931 /*
932 * For CardBus bridges, we leave 4 bus numbers
933 * as cards with a PCI-to-PCI bridge can be
934 * inserted later.
935 */
936 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
937 struct pci_bus *parent = bus;
938 if (pci_find_bus(pci_domain_nr(bus),
939 max+i+1))
940 break;
941 while (parent->parent) {
942 if ((!pcibios_assign_all_busses()) &&
943 (parent->busn_res.end > max) &&
944 (parent->busn_res.end <= max+i)) {
945 j = 1;
946 }
947 parent = parent->parent;
948 }
949 if (j) {
950 /*
951 * Often, there are two cardbus bridges
952 * -- try to leave one valid bus number
953 * for each one.
954 */
955 i /= 2;
956 break;
957 }
958 }
959 max += i;
960 }
961 /*
962 * Set the subordinate bus number to its real value.
963 */
964 pci_bus_update_busn_res_end(child, max);
965 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
966 }
967
968 sprintf(child->name,
969 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
970 pci_domain_nr(bus), child->number);
971
972 /* Has only triggered on CardBus, fixup is in yenta_socket */
973 while (bus->parent) {
974 if ((child->busn_res.end > bus->busn_res.end) ||
975 (child->number > bus->busn_res.end) ||
976 (child->number < bus->number) ||
977 (child->busn_res.end < bus->number)) {
978 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
979 &child->busn_res,
980 (bus->number > child->busn_res.end &&
981 bus->busn_res.end < child->number) ?
982 "wholly" : "partially",
983 bus->self->transparent ? " transparent" : "",
984 dev_name(&bus->dev),
985 &bus->busn_res);
986 }
987 bus = bus->parent;
988 }
989
990 out:
991 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
992
993 return max;
994 }
995 EXPORT_SYMBOL(pci_scan_bridge);
996
997 /*
998 * Read interrupt line and base address registers.
999 * The architecture-dependent code can tweak these, of course.
1000 */
pci_read_irq(struct pci_dev * dev)1001 static void pci_read_irq(struct pci_dev *dev)
1002 {
1003 unsigned char irq;
1004
1005 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1006 dev->pin = irq;
1007 if (irq)
1008 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1009 dev->irq = irq;
1010 }
1011
set_pcie_port_type(struct pci_dev * pdev)1012 void set_pcie_port_type(struct pci_dev *pdev)
1013 {
1014 int pos;
1015 u16 reg16;
1016 int type;
1017 struct pci_dev *parent;
1018
1019 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1020 if (!pos)
1021 return;
1022 pdev->pcie_cap = pos;
1023 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1024 pdev->pcie_flags_reg = reg16;
1025 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1026 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1027
1028 /*
1029 * A Root Port is always the upstream end of a Link. No PCIe
1030 * component has two Links. Two Links are connected by a Switch
1031 * that has a Port on each Link and internal logic to connect the
1032 * two Ports.
1033 */
1034 type = pci_pcie_type(pdev);
1035 if (type == PCI_EXP_TYPE_ROOT_PORT)
1036 pdev->has_secondary_link = 1;
1037 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1038 type == PCI_EXP_TYPE_DOWNSTREAM) {
1039 parent = pci_upstream_bridge(pdev);
1040
1041 /*
1042 * Usually there's an upstream device (Root Port or Switch
1043 * Downstream Port), but we can't assume one exists.
1044 */
1045 if (parent && !parent->has_secondary_link)
1046 pdev->has_secondary_link = 1;
1047 }
1048 }
1049
set_pcie_hotplug_bridge(struct pci_dev * pdev)1050 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1051 {
1052 u32 reg32;
1053
1054 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1055 if (reg32 & PCI_EXP_SLTCAP_HPC)
1056 pdev->is_hotplug_bridge = 1;
1057 }
1058
1059 /**
1060 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1061 * @dev: PCI device
1062 *
1063 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1064 * when forwarding a type1 configuration request the bridge must check that
1065 * the extended register address field is zero. The bridge is not permitted
1066 * to forward the transactions and must handle it as an Unsupported Request.
1067 * Some bridges do not follow this rule and simply drop the extended register
1068 * bits, resulting in the standard config space being aliased, every 256
1069 * bytes across the entire configuration space. Test for this condition by
1070 * comparing the first dword of each potential alias to the vendor/device ID.
1071 * Known offenders:
1072 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1073 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1074 */
pci_ext_cfg_is_aliased(struct pci_dev * dev)1075 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1076 {
1077 #ifdef CONFIG_PCI_QUIRKS
1078 int pos;
1079 u32 header, tmp;
1080
1081 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1082
1083 for (pos = PCI_CFG_SPACE_SIZE;
1084 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1085 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1086 || header != tmp)
1087 return false;
1088 }
1089
1090 return true;
1091 #else
1092 return false;
1093 #endif
1094 }
1095
1096 /**
1097 * pci_cfg_space_size - get the configuration space size of the PCI device.
1098 * @dev: PCI device
1099 *
1100 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1101 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1102 * access it. Maybe we don't have a way to generate extended config space
1103 * accesses, or the device is behind a reverse Express bridge. So we try
1104 * reading the dword at 0x100 which must either be 0 or a valid extended
1105 * capability header.
1106 */
pci_cfg_space_size_ext(struct pci_dev * dev)1107 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1108 {
1109 u32 status;
1110 int pos = PCI_CFG_SPACE_SIZE;
1111
1112 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1113 goto fail;
1114 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1115 goto fail;
1116
1117 return PCI_CFG_SPACE_EXP_SIZE;
1118
1119 fail:
1120 return PCI_CFG_SPACE_SIZE;
1121 }
1122
pci_cfg_space_size(struct pci_dev * dev)1123 int pci_cfg_space_size(struct pci_dev *dev)
1124 {
1125 int pos;
1126 u32 status;
1127 u16 class;
1128
1129 class = dev->class >> 8;
1130 if (class == PCI_CLASS_BRIDGE_HOST)
1131 return pci_cfg_space_size_ext(dev);
1132
1133 if (!pci_is_pcie(dev)) {
1134 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1135 if (!pos)
1136 goto fail;
1137
1138 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1139 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1140 goto fail;
1141 }
1142
1143 return pci_cfg_space_size_ext(dev);
1144
1145 fail:
1146 return PCI_CFG_SPACE_SIZE;
1147 }
1148
1149 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1150
pci_msi_setup_pci_dev(struct pci_dev * dev)1151 void pci_msi_setup_pci_dev(struct pci_dev *dev)
1152 {
1153 /*
1154 * Disable the MSI hardware to avoid screaming interrupts
1155 * during boot. This is the power on reset default so
1156 * usually this should be a noop.
1157 */
1158 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1159 if (dev->msi_cap)
1160 pci_msi_set_enable(dev, 0);
1161
1162 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1163 if (dev->msix_cap)
1164 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1165 }
1166
1167 /**
1168 * pci_setup_device - fill in class and map information of a device
1169 * @dev: the device structure to fill
1170 *
1171 * Initialize the device structure with information about the device's
1172 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1173 * Called at initialisation of the PCI subsystem and by CardBus services.
1174 * Returns 0 on success and negative if unknown type of device (not normal,
1175 * bridge or CardBus).
1176 */
pci_setup_device(struct pci_dev * dev)1177 int pci_setup_device(struct pci_dev *dev)
1178 {
1179 u32 class;
1180 u16 cmd;
1181 u8 hdr_type;
1182 int pos = 0;
1183 struct pci_bus_region region;
1184 struct resource *res;
1185
1186 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1187 return -EIO;
1188
1189 dev->sysdata = dev->bus->sysdata;
1190 dev->dev.parent = dev->bus->bridge;
1191 dev->dev.bus = &pci_bus_type;
1192 dev->hdr_type = hdr_type & 0x7f;
1193 dev->multifunction = !!(hdr_type & 0x80);
1194 dev->error_state = pci_channel_io_normal;
1195 set_pcie_port_type(dev);
1196
1197 pci_dev_assign_slot(dev);
1198 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1199 set this higher, assuming the system even supports it. */
1200 dev->dma_mask = 0xffffffff;
1201
1202 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1203 dev->bus->number, PCI_SLOT(dev->devfn),
1204 PCI_FUNC(dev->devfn));
1205
1206 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1207 dev->revision = class & 0xff;
1208 dev->class = class >> 8; /* upper 3 bytes */
1209
1210 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1211 dev->vendor, dev->device, dev->hdr_type, dev->class);
1212
1213 /* need to have dev->class ready */
1214 dev->cfg_size = pci_cfg_space_size(dev);
1215
1216 /* "Unknown power state" */
1217 dev->current_state = PCI_UNKNOWN;
1218
1219 pci_msi_setup_pci_dev(dev);
1220
1221 /* Early fixups, before probing the BARs */
1222 pci_fixup_device(pci_fixup_early, dev);
1223 /* device class may be changed after fixup */
1224 class = dev->class >> 8;
1225
1226 if (dev->non_compliant_bars) {
1227 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1228 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1229 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1230 cmd &= ~PCI_COMMAND_IO;
1231 cmd &= ~PCI_COMMAND_MEMORY;
1232 pci_write_config_word(dev, PCI_COMMAND, cmd);
1233 }
1234 }
1235
1236 switch (dev->hdr_type) { /* header type */
1237 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1238 if (class == PCI_CLASS_BRIDGE_PCI)
1239 goto bad;
1240 pci_read_irq(dev);
1241 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1242 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1243 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1244
1245 /*
1246 * Do the ugly legacy mode stuff here rather than broken chip
1247 * quirk code. Legacy mode ATA controllers have fixed
1248 * addresses. These are not always echoed in BAR0-3, and
1249 * BAR0-3 in a few cases contain junk!
1250 */
1251 if (class == PCI_CLASS_STORAGE_IDE) {
1252 u8 progif;
1253 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1254 if ((progif & 1) == 0) {
1255 region.start = 0x1F0;
1256 region.end = 0x1F7;
1257 res = &dev->resource[0];
1258 res->flags = LEGACY_IO_RESOURCE;
1259 pcibios_bus_to_resource(dev->bus, res, ®ion);
1260 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1261 res);
1262 region.start = 0x3F6;
1263 region.end = 0x3F6;
1264 res = &dev->resource[1];
1265 res->flags = LEGACY_IO_RESOURCE;
1266 pcibios_bus_to_resource(dev->bus, res, ®ion);
1267 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1268 res);
1269 }
1270 if ((progif & 4) == 0) {
1271 region.start = 0x170;
1272 region.end = 0x177;
1273 res = &dev->resource[2];
1274 res->flags = LEGACY_IO_RESOURCE;
1275 pcibios_bus_to_resource(dev->bus, res, ®ion);
1276 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1277 res);
1278 region.start = 0x376;
1279 region.end = 0x376;
1280 res = &dev->resource[3];
1281 res->flags = LEGACY_IO_RESOURCE;
1282 pcibios_bus_to_resource(dev->bus, res, ®ion);
1283 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1284 res);
1285 }
1286 }
1287 break;
1288
1289 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1290 if (class != PCI_CLASS_BRIDGE_PCI)
1291 goto bad;
1292 /* The PCI-to-PCI bridge spec requires that subtractive
1293 decoding (i.e. transparent) bridge must have programming
1294 interface code of 0x01. */
1295 pci_read_irq(dev);
1296 dev->transparent = ((dev->class & 0xff) == 1);
1297 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1298 set_pcie_hotplug_bridge(dev);
1299 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1300 if (pos) {
1301 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1302 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1303 }
1304 break;
1305
1306 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1307 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1308 goto bad;
1309 pci_read_irq(dev);
1310 pci_read_bases(dev, 1, 0);
1311 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1312 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1313 break;
1314
1315 default: /* unknown header */
1316 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1317 dev->hdr_type);
1318 return -EIO;
1319
1320 bad:
1321 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1322 dev->class, dev->hdr_type);
1323 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1324 }
1325
1326 /* We found a fine healthy device, go go go... */
1327 return 0;
1328 }
1329
pci_configure_mps(struct pci_dev * dev)1330 static void pci_configure_mps(struct pci_dev *dev)
1331 {
1332 struct pci_dev *bridge = pci_upstream_bridge(dev);
1333 int mps, p_mps, rc;
1334
1335 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1336 return;
1337
1338 mps = pcie_get_mps(dev);
1339 p_mps = pcie_get_mps(bridge);
1340
1341 if (mps == p_mps)
1342 return;
1343
1344 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1345 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1346 mps, pci_name(bridge), p_mps);
1347 return;
1348 }
1349
1350 /*
1351 * Fancier MPS configuration is done later by
1352 * pcie_bus_configure_settings()
1353 */
1354 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1355 return;
1356
1357 rc = pcie_set_mps(dev, p_mps);
1358 if (rc) {
1359 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1360 p_mps);
1361 return;
1362 }
1363
1364 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1365 p_mps, mps, 128 << dev->pcie_mpss);
1366 }
1367
1368 static struct hpp_type0 pci_default_type0 = {
1369 .revision = 1,
1370 .cache_line_size = 8,
1371 .latency_timer = 0x40,
1372 .enable_serr = 0,
1373 .enable_perr = 0,
1374 };
1375
program_hpp_type0(struct pci_dev * dev,struct hpp_type0 * hpp)1376 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1377 {
1378 u16 pci_cmd, pci_bctl;
1379
1380 if (!hpp)
1381 hpp = &pci_default_type0;
1382
1383 if (hpp->revision > 1) {
1384 dev_warn(&dev->dev,
1385 "PCI settings rev %d not supported; using defaults\n",
1386 hpp->revision);
1387 hpp = &pci_default_type0;
1388 }
1389
1390 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1391 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1392 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1393 if (hpp->enable_serr)
1394 pci_cmd |= PCI_COMMAND_SERR;
1395 if (hpp->enable_perr)
1396 pci_cmd |= PCI_COMMAND_PARITY;
1397 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1398
1399 /* Program bridge control value */
1400 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1401 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1402 hpp->latency_timer);
1403 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1404 if (hpp->enable_serr)
1405 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1406 if (hpp->enable_perr)
1407 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1408 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1409 }
1410 }
1411
program_hpp_type1(struct pci_dev * dev,struct hpp_type1 * hpp)1412 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1413 {
1414 if (hpp)
1415 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1416 }
1417
program_hpp_type2(struct pci_dev * dev,struct hpp_type2 * hpp)1418 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1419 {
1420 int pos;
1421 u32 reg32;
1422
1423 if (!hpp)
1424 return;
1425
1426 if (hpp->revision > 1) {
1427 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1428 hpp->revision);
1429 return;
1430 }
1431
1432 /*
1433 * Don't allow _HPX to change MPS or MRRS settings. We manage
1434 * those to make sure they're consistent with the rest of the
1435 * platform.
1436 */
1437 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1438 PCI_EXP_DEVCTL_READRQ;
1439 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1440 PCI_EXP_DEVCTL_READRQ);
1441
1442 /* Initialize Device Control Register */
1443 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1444 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1445
1446 /* Initialize Link Control Register */
1447 if (pcie_cap_has_lnkctl(dev))
1448 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1449 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1450
1451 /* Find Advanced Error Reporting Enhanced Capability */
1452 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1453 if (!pos)
1454 return;
1455
1456 /* Initialize Uncorrectable Error Mask Register */
1457 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1458 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1459 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1460
1461 /* Initialize Uncorrectable Error Severity Register */
1462 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1463 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1464 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1465
1466 /* Initialize Correctable Error Mask Register */
1467 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1468 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1469 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1470
1471 /* Initialize Advanced Error Capabilities and Control Register */
1472 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1473 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1474 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1475
1476 /*
1477 * FIXME: The following two registers are not supported yet.
1478 *
1479 * o Secondary Uncorrectable Error Severity Register
1480 * o Secondary Uncorrectable Error Mask Register
1481 */
1482 }
1483
pci_configure_device(struct pci_dev * dev)1484 static void pci_configure_device(struct pci_dev *dev)
1485 {
1486 struct hotplug_params hpp;
1487 int ret;
1488
1489 pci_configure_mps(dev);
1490
1491 memset(&hpp, 0, sizeof(hpp));
1492 ret = pci_get_hp_params(dev, &hpp);
1493 if (ret)
1494 return;
1495
1496 program_hpp_type2(dev, hpp.t2);
1497 program_hpp_type1(dev, hpp.t1);
1498 program_hpp_type0(dev, hpp.t0);
1499 }
1500
pci_release_capabilities(struct pci_dev * dev)1501 static void pci_release_capabilities(struct pci_dev *dev)
1502 {
1503 pci_vpd_release(dev);
1504 pci_iov_release(dev);
1505 pci_free_cap_save_buffers(dev);
1506 }
1507
1508 /**
1509 * pci_release_dev - free a pci device structure when all users of it are finished.
1510 * @dev: device that's been disconnected
1511 *
1512 * Will be called only by the device core when all users of this pci device are
1513 * done.
1514 */
pci_release_dev(struct device * dev)1515 static void pci_release_dev(struct device *dev)
1516 {
1517 struct pci_dev *pci_dev;
1518
1519 pci_dev = to_pci_dev(dev);
1520 pci_release_capabilities(pci_dev);
1521 pci_release_of_node(pci_dev);
1522 pcibios_release_device(pci_dev);
1523 pci_bus_put(pci_dev->bus);
1524 kfree(pci_dev->driver_override);
1525 kfree(pci_dev);
1526 }
1527
pci_alloc_dev(struct pci_bus * bus)1528 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1529 {
1530 struct pci_dev *dev;
1531
1532 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1533 if (!dev)
1534 return NULL;
1535
1536 INIT_LIST_HEAD(&dev->bus_list);
1537 dev->dev.type = &pci_dev_type;
1538 dev->bus = pci_bus_get(bus);
1539
1540 return dev;
1541 }
1542 EXPORT_SYMBOL(pci_alloc_dev);
1543
pci_bus_read_dev_vendor_id(struct pci_bus * bus,int devfn,u32 * l,int crs_timeout)1544 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1545 int crs_timeout)
1546 {
1547 int delay = 1;
1548
1549 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1550 return false;
1551
1552 /* some broken boards return 0 or ~0 if a slot is empty: */
1553 if (*l == 0xffffffff || *l == 0x00000000 ||
1554 *l == 0x0000ffff || *l == 0xffff0000)
1555 return false;
1556
1557 /*
1558 * Configuration Request Retry Status. Some root ports return the
1559 * actual device ID instead of the synthetic ID (0xFFFF) required
1560 * by the PCIe spec. Ignore the device ID and only check for
1561 * (vendor id == 1).
1562 */
1563 while ((*l & 0xffff) == 0x0001) {
1564 if (!crs_timeout)
1565 return false;
1566
1567 msleep(delay);
1568 delay *= 2;
1569 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1570 return false;
1571 /* Card hasn't responded in 60 seconds? Must be stuck. */
1572 if (delay > crs_timeout) {
1573 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1574 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1575 PCI_FUNC(devfn));
1576 return false;
1577 }
1578 }
1579
1580 return true;
1581 }
1582 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1583
1584 /*
1585 * Read the config data for a PCI device, sanity-check it
1586 * and fill in the dev structure...
1587 */
pci_scan_device(struct pci_bus * bus,int devfn)1588 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1589 {
1590 struct pci_dev *dev;
1591 u32 l;
1592
1593 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1594 return NULL;
1595
1596 dev = pci_alloc_dev(bus);
1597 if (!dev)
1598 return NULL;
1599
1600 dev->devfn = devfn;
1601 dev->vendor = l & 0xffff;
1602 dev->device = (l >> 16) & 0xffff;
1603
1604 pci_set_of_node(dev);
1605
1606 if (pci_setup_device(dev)) {
1607 pci_bus_put(dev->bus);
1608 kfree(dev);
1609 return NULL;
1610 }
1611
1612 return dev;
1613 }
1614
pci_init_capabilities(struct pci_dev * dev)1615 static void pci_init_capabilities(struct pci_dev *dev)
1616 {
1617 /* Enhanced Allocation */
1618 pci_ea_init(dev);
1619
1620 /* MSI/MSI-X list */
1621 pci_msi_init_pci_dev(dev);
1622
1623 /* Buffers for saving PCIe and PCI-X capabilities */
1624 pci_allocate_cap_save_buffers(dev);
1625
1626 /* Power Management */
1627 pci_pm_init(dev);
1628
1629 /* Vital Product Data */
1630 pci_vpd_pci22_init(dev);
1631
1632 /* Alternative Routing-ID Forwarding */
1633 pci_configure_ari(dev);
1634
1635 /* Single Root I/O Virtualization */
1636 pci_iov_init(dev);
1637
1638 /* Address Translation Services */
1639 pci_ats_init(dev);
1640
1641 /* Enable ACS P2P upstream forwarding */
1642 pci_enable_acs(dev);
1643
1644 pci_cleanup_aer_error_status_regs(dev);
1645 }
1646
1647 /*
1648 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1649 * devices. Firmware interfaces that can select the MSI domain on a
1650 * per-device basis should be called from here.
1651 */
pci_dev_msi_domain(struct pci_dev * dev)1652 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1653 {
1654 struct irq_domain *d;
1655
1656 /*
1657 * If a domain has been set through the pcibios_add_device
1658 * callback, then this is the one (platform code knows best).
1659 */
1660 d = dev_get_msi_domain(&dev->dev);
1661 if (d)
1662 return d;
1663
1664 /*
1665 * Let's see if we have a firmware interface able to provide
1666 * the domain.
1667 */
1668 d = pci_msi_get_device_domain(dev);
1669 if (d)
1670 return d;
1671
1672 return NULL;
1673 }
1674
pci_set_msi_domain(struct pci_dev * dev)1675 static void pci_set_msi_domain(struct pci_dev *dev)
1676 {
1677 struct irq_domain *d;
1678
1679 /*
1680 * If the platform or firmware interfaces cannot supply a
1681 * device-specific MSI domain, then inherit the default domain
1682 * from the host bridge itself.
1683 */
1684 d = pci_dev_msi_domain(dev);
1685 if (!d)
1686 d = dev_get_msi_domain(&dev->bus->dev);
1687
1688 dev_set_msi_domain(&dev->dev, d);
1689 }
1690
1691 /**
1692 * pci_dma_configure - Setup DMA configuration
1693 * @dev: ptr to pci_dev struct of the PCI device
1694 *
1695 * Function to update PCI devices's DMA configuration using the same
1696 * info from the OF node or ACPI node of host bridge's parent (if any).
1697 */
pci_dma_configure(struct pci_dev * dev)1698 static void pci_dma_configure(struct pci_dev *dev)
1699 {
1700 struct device *bridge = pci_get_host_bridge_device(dev);
1701
1702 if (IS_ENABLED(CONFIG_OF) &&
1703 bridge->parent && bridge->parent->of_node) {
1704 of_dma_configure(&dev->dev, bridge->parent->of_node);
1705 } else if (has_acpi_companion(bridge)) {
1706 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1707 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1708
1709 if (attr == DEV_DMA_NOT_SUPPORTED)
1710 dev_warn(&dev->dev, "DMA not supported.\n");
1711 else
1712 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1713 attr == DEV_DMA_COHERENT);
1714 }
1715
1716 pci_put_host_bridge_device(bridge);
1717 }
1718
pci_device_add(struct pci_dev * dev,struct pci_bus * bus)1719 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1720 {
1721 int ret;
1722
1723 pci_configure_device(dev);
1724
1725 device_initialize(&dev->dev);
1726 dev->dev.release = pci_release_dev;
1727
1728 set_dev_node(&dev->dev, pcibus_to_node(bus));
1729 dev->dev.dma_mask = &dev->dma_mask;
1730 dev->dev.dma_parms = &dev->dma_parms;
1731 dev->dev.coherent_dma_mask = 0xffffffffull;
1732 pci_dma_configure(dev);
1733
1734 pci_set_dma_max_seg_size(dev, 65536);
1735 pci_set_dma_seg_boundary(dev, 0xffffffff);
1736
1737 /* Fix up broken headers */
1738 pci_fixup_device(pci_fixup_header, dev);
1739
1740 /* moved out from quirk header fixup code */
1741 pci_reassigndev_resource_alignment(dev);
1742
1743 /* Clear the state_saved flag. */
1744 dev->state_saved = false;
1745
1746 /* Initialize various capabilities */
1747 pci_init_capabilities(dev);
1748
1749 /*
1750 * Add the device to our list of discovered devices
1751 * and the bus list for fixup functions, etc.
1752 */
1753 down_write(&pci_bus_sem);
1754 list_add_tail(&dev->bus_list, &bus->devices);
1755 up_write(&pci_bus_sem);
1756
1757 ret = pcibios_add_device(dev);
1758 WARN_ON(ret < 0);
1759
1760 /* Setup MSI irq domain */
1761 pci_set_msi_domain(dev);
1762
1763 /* Notifier could use PCI capabilities */
1764 dev->match_driver = false;
1765 ret = device_add(&dev->dev);
1766 WARN_ON(ret < 0);
1767 }
1768
pci_scan_single_device(struct pci_bus * bus,int devfn)1769 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1770 {
1771 struct pci_dev *dev;
1772
1773 dev = pci_get_slot(bus, devfn);
1774 if (dev) {
1775 pci_dev_put(dev);
1776 return dev;
1777 }
1778
1779 dev = pci_scan_device(bus, devfn);
1780 if (!dev)
1781 return NULL;
1782
1783 pci_device_add(dev, bus);
1784
1785 return dev;
1786 }
1787 EXPORT_SYMBOL(pci_scan_single_device);
1788
next_fn(struct pci_bus * bus,struct pci_dev * dev,unsigned fn)1789 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1790 {
1791 int pos;
1792 u16 cap = 0;
1793 unsigned next_fn;
1794
1795 if (pci_ari_enabled(bus)) {
1796 if (!dev)
1797 return 0;
1798 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1799 if (!pos)
1800 return 0;
1801
1802 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1803 next_fn = PCI_ARI_CAP_NFN(cap);
1804 if (next_fn <= fn)
1805 return 0; /* protect against malformed list */
1806
1807 return next_fn;
1808 }
1809
1810 /* dev may be NULL for non-contiguous multifunction devices */
1811 if (!dev || dev->multifunction)
1812 return (fn + 1) % 8;
1813
1814 return 0;
1815 }
1816
only_one_child(struct pci_bus * bus)1817 static int only_one_child(struct pci_bus *bus)
1818 {
1819 struct pci_dev *parent = bus->self;
1820
1821 if (!parent || !pci_is_pcie(parent))
1822 return 0;
1823 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1824 return 1;
1825 if (parent->has_secondary_link &&
1826 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1827 return 1;
1828 return 0;
1829 }
1830
1831 /**
1832 * pci_scan_slot - scan a PCI slot on a bus for devices.
1833 * @bus: PCI bus to scan
1834 * @devfn: slot number to scan (must have zero function.)
1835 *
1836 * Scan a PCI slot on the specified PCI bus for devices, adding
1837 * discovered devices to the @bus->devices list. New devices
1838 * will not have is_added set.
1839 *
1840 * Returns the number of new devices found.
1841 */
pci_scan_slot(struct pci_bus * bus,int devfn)1842 int pci_scan_slot(struct pci_bus *bus, int devfn)
1843 {
1844 unsigned fn, nr = 0;
1845 struct pci_dev *dev;
1846
1847 if (only_one_child(bus) && (devfn > 0))
1848 return 0; /* Already scanned the entire slot */
1849
1850 dev = pci_scan_single_device(bus, devfn);
1851 if (!dev)
1852 return 0;
1853 if (!dev->is_added)
1854 nr++;
1855
1856 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1857 dev = pci_scan_single_device(bus, devfn + fn);
1858 if (dev) {
1859 if (!dev->is_added)
1860 nr++;
1861 dev->multifunction = 1;
1862 }
1863 }
1864
1865 /* only one slot has pcie device */
1866 if (bus->self && nr)
1867 pcie_aspm_init_link_state(bus->self);
1868
1869 return nr;
1870 }
1871 EXPORT_SYMBOL(pci_scan_slot);
1872
pcie_find_smpss(struct pci_dev * dev,void * data)1873 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1874 {
1875 u8 *smpss = data;
1876
1877 if (!pci_is_pcie(dev))
1878 return 0;
1879
1880 /*
1881 * We don't have a way to change MPS settings on devices that have
1882 * drivers attached. A hot-added device might support only the minimum
1883 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1884 * where devices may be hot-added, we limit the fabric MPS to 128 so
1885 * hot-added devices will work correctly.
1886 *
1887 * However, if we hot-add a device to a slot directly below a Root
1888 * Port, it's impossible for there to be other existing devices below
1889 * the port. We don't limit the MPS in this case because we can
1890 * reconfigure MPS on both the Root Port and the hot-added device,
1891 * and there are no other devices involved.
1892 *
1893 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1894 */
1895 if (dev->is_hotplug_bridge &&
1896 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1897 *smpss = 0;
1898
1899 if (*smpss > dev->pcie_mpss)
1900 *smpss = dev->pcie_mpss;
1901
1902 return 0;
1903 }
1904
pcie_write_mps(struct pci_dev * dev,int mps)1905 static void pcie_write_mps(struct pci_dev *dev, int mps)
1906 {
1907 int rc;
1908
1909 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1910 mps = 128 << dev->pcie_mpss;
1911
1912 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1913 dev->bus->self)
1914 /* For "Performance", the assumption is made that
1915 * downstream communication will never be larger than
1916 * the MRRS. So, the MPS only needs to be configured
1917 * for the upstream communication. This being the case,
1918 * walk from the top down and set the MPS of the child
1919 * to that of the parent bus.
1920 *
1921 * Configure the device MPS with the smaller of the
1922 * device MPSS or the bridge MPS (which is assumed to be
1923 * properly configured at this point to the largest
1924 * allowable MPS based on its parent bus).
1925 */
1926 mps = min(mps, pcie_get_mps(dev->bus->self));
1927 }
1928
1929 rc = pcie_set_mps(dev, mps);
1930 if (rc)
1931 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1932 }
1933
pcie_write_mrrs(struct pci_dev * dev)1934 static void pcie_write_mrrs(struct pci_dev *dev)
1935 {
1936 int rc, mrrs;
1937
1938 /* In the "safe" case, do not configure the MRRS. There appear to be
1939 * issues with setting MRRS to 0 on a number of devices.
1940 */
1941 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1942 return;
1943
1944 /* For Max performance, the MRRS must be set to the largest supported
1945 * value. However, it cannot be configured larger than the MPS the
1946 * device or the bus can support. This should already be properly
1947 * configured by a prior call to pcie_write_mps.
1948 */
1949 mrrs = pcie_get_mps(dev);
1950
1951 /* MRRS is a R/W register. Invalid values can be written, but a
1952 * subsequent read will verify if the value is acceptable or not.
1953 * If the MRRS value provided is not acceptable (e.g., too large),
1954 * shrink the value until it is acceptable to the HW.
1955 */
1956 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1957 rc = pcie_set_readrq(dev, mrrs);
1958 if (!rc)
1959 break;
1960
1961 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1962 mrrs /= 2;
1963 }
1964
1965 if (mrrs < 128)
1966 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1967 }
1968
pcie_bus_configure_set(struct pci_dev * dev,void * data)1969 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1970 {
1971 int mps, orig_mps;
1972
1973 if (!pci_is_pcie(dev))
1974 return 0;
1975
1976 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
1977 pcie_bus_config == PCIE_BUS_DEFAULT)
1978 return 0;
1979
1980 mps = 128 << *(u8 *)data;
1981 orig_mps = pcie_get_mps(dev);
1982
1983 pcie_write_mps(dev, mps);
1984 pcie_write_mrrs(dev);
1985
1986 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1987 pcie_get_mps(dev), 128 << dev->pcie_mpss,
1988 orig_mps, pcie_get_readrq(dev));
1989
1990 return 0;
1991 }
1992
1993 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1994 * parents then children fashion. If this changes, then this code will not
1995 * work as designed.
1996 */
pcie_bus_configure_settings(struct pci_bus * bus)1997 void pcie_bus_configure_settings(struct pci_bus *bus)
1998 {
1999 u8 smpss = 0;
2000
2001 if (!bus->self)
2002 return;
2003
2004 if (!pci_is_pcie(bus->self))
2005 return;
2006
2007 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2008 * to be aware of the MPS of the destination. To work around this,
2009 * simply force the MPS of the entire system to the smallest possible.
2010 */
2011 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2012 smpss = 0;
2013
2014 if (pcie_bus_config == PCIE_BUS_SAFE) {
2015 smpss = bus->self->pcie_mpss;
2016
2017 pcie_find_smpss(bus->self, &smpss);
2018 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2019 }
2020
2021 pcie_bus_configure_set(bus->self, &smpss);
2022 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2023 }
2024 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2025
pci_scan_child_bus(struct pci_bus * bus)2026 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2027 {
2028 unsigned int devfn, pass, max = bus->busn_res.start;
2029 struct pci_dev *dev;
2030
2031 dev_dbg(&bus->dev, "scanning bus\n");
2032
2033 /* Go find them, Rover! */
2034 for (devfn = 0; devfn < 0x100; devfn += 8)
2035 pci_scan_slot(bus, devfn);
2036
2037 /* Reserve buses for SR-IOV capability. */
2038 max += pci_iov_bus_range(bus);
2039
2040 /*
2041 * After performing arch-dependent fixup of the bus, look behind
2042 * all PCI-to-PCI bridges on this bus.
2043 */
2044 if (!bus->is_added) {
2045 dev_dbg(&bus->dev, "fixups for bus\n");
2046 pcibios_fixup_bus(bus);
2047 bus->is_added = 1;
2048 }
2049
2050 for (pass = 0; pass < 2; pass++)
2051 list_for_each_entry(dev, &bus->devices, bus_list) {
2052 if (pci_is_bridge(dev))
2053 max = pci_scan_bridge(bus, dev, max, pass);
2054 }
2055
2056 /*
2057 * We've scanned the bus and so we know all about what's on
2058 * the other side of any bridges that may be on this bus plus
2059 * any devices.
2060 *
2061 * Return how far we've got finding sub-buses.
2062 */
2063 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2064 return max;
2065 }
2066 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2067
2068 /**
2069 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2070 * @bridge: Host bridge to set up.
2071 *
2072 * Default empty implementation. Replace with an architecture-specific setup
2073 * routine, if necessary.
2074 */
pcibios_root_bridge_prepare(struct pci_host_bridge * bridge)2075 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2076 {
2077 return 0;
2078 }
2079
pcibios_add_bus(struct pci_bus * bus)2080 void __weak pcibios_add_bus(struct pci_bus *bus)
2081 {
2082 }
2083
pcibios_remove_bus(struct pci_bus * bus)2084 void __weak pcibios_remove_bus(struct pci_bus *bus)
2085 {
2086 }
2087
pci_create_root_bus(struct device * parent,int bus,struct pci_ops * ops,void * sysdata,struct list_head * resources)2088 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2089 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2090 {
2091 int error;
2092 struct pci_host_bridge *bridge;
2093 struct pci_bus *b, *b2;
2094 struct resource_entry *window, *n;
2095 struct resource *res;
2096 resource_size_t offset;
2097 char bus_addr[64];
2098 char *fmt;
2099
2100 b = pci_alloc_bus(NULL);
2101 if (!b)
2102 return NULL;
2103
2104 b->sysdata = sysdata;
2105 b->ops = ops;
2106 b->number = b->busn_res.start = bus;
2107 pci_bus_assign_domain_nr(b, parent);
2108 b2 = pci_find_bus(pci_domain_nr(b), bus);
2109 if (b2) {
2110 /* If we already got to this bus through a different bridge, ignore it */
2111 dev_dbg(&b2->dev, "bus already known\n");
2112 goto err_out;
2113 }
2114
2115 bridge = pci_alloc_host_bridge(b);
2116 if (!bridge)
2117 goto err_out;
2118
2119 bridge->dev.parent = parent;
2120 bridge->dev.release = pci_release_host_bridge_dev;
2121 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2122 error = pcibios_root_bridge_prepare(bridge);
2123 if (error) {
2124 kfree(bridge);
2125 goto err_out;
2126 }
2127
2128 error = device_register(&bridge->dev);
2129 if (error) {
2130 put_device(&bridge->dev);
2131 goto err_out;
2132 }
2133 b->bridge = get_device(&bridge->dev);
2134 device_enable_async_suspend(b->bridge);
2135 pci_set_bus_of_node(b);
2136 pci_set_bus_msi_domain(b);
2137
2138 if (!parent)
2139 set_dev_node(b->bridge, pcibus_to_node(b));
2140
2141 b->dev.class = &pcibus_class;
2142 b->dev.parent = b->bridge;
2143 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2144 error = device_register(&b->dev);
2145 if (error)
2146 goto class_dev_reg_err;
2147
2148 pcibios_add_bus(b);
2149
2150 /* Create legacy_io and legacy_mem files for this bus */
2151 pci_create_legacy_files(b);
2152
2153 if (parent)
2154 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2155 else
2156 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2157
2158 /* Add initial resources to the bus */
2159 resource_list_for_each_entry_safe(window, n, resources) {
2160 list_move_tail(&window->node, &bridge->windows);
2161 res = window->res;
2162 offset = window->offset;
2163 if (res->flags & IORESOURCE_BUS)
2164 pci_bus_insert_busn_res(b, bus, res->end);
2165 else
2166 pci_bus_add_resource(b, res, 0);
2167 if (offset) {
2168 if (resource_type(res) == IORESOURCE_IO)
2169 fmt = " (bus address [%#06llx-%#06llx])";
2170 else
2171 fmt = " (bus address [%#010llx-%#010llx])";
2172 snprintf(bus_addr, sizeof(bus_addr), fmt,
2173 (unsigned long long) (res->start - offset),
2174 (unsigned long long) (res->end - offset));
2175 } else
2176 bus_addr[0] = '\0';
2177 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2178 }
2179
2180 down_write(&pci_bus_sem);
2181 list_add_tail(&b->node, &pci_root_buses);
2182 up_write(&pci_bus_sem);
2183
2184 return b;
2185
2186 class_dev_reg_err:
2187 put_device(&bridge->dev);
2188 device_unregister(&bridge->dev);
2189 err_out:
2190 kfree(b);
2191 return NULL;
2192 }
2193 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2194
pci_bus_insert_busn_res(struct pci_bus * b,int bus,int bus_max)2195 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2196 {
2197 struct resource *res = &b->busn_res;
2198 struct resource *parent_res, *conflict;
2199
2200 res->start = bus;
2201 res->end = bus_max;
2202 res->flags = IORESOURCE_BUS;
2203
2204 if (!pci_is_root_bus(b))
2205 parent_res = &b->parent->busn_res;
2206 else {
2207 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2208 res->flags |= IORESOURCE_PCI_FIXED;
2209 }
2210
2211 conflict = request_resource_conflict(parent_res, res);
2212
2213 if (conflict)
2214 dev_printk(KERN_DEBUG, &b->dev,
2215 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2216 res, pci_is_root_bus(b) ? "domain " : "",
2217 parent_res, conflict->name, conflict);
2218
2219 return conflict == NULL;
2220 }
2221
pci_bus_update_busn_res_end(struct pci_bus * b,int bus_max)2222 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2223 {
2224 struct resource *res = &b->busn_res;
2225 struct resource old_res = *res;
2226 resource_size_t size;
2227 int ret;
2228
2229 if (res->start > bus_max)
2230 return -EINVAL;
2231
2232 size = bus_max - res->start + 1;
2233 ret = adjust_resource(res, res->start, size);
2234 dev_printk(KERN_DEBUG, &b->dev,
2235 "busn_res: %pR end %s updated to %02x\n",
2236 &old_res, ret ? "can not be" : "is", bus_max);
2237
2238 if (!ret && !res->parent)
2239 pci_bus_insert_busn_res(b, res->start, res->end);
2240
2241 return ret;
2242 }
2243
pci_bus_release_busn_res(struct pci_bus * b)2244 void pci_bus_release_busn_res(struct pci_bus *b)
2245 {
2246 struct resource *res = &b->busn_res;
2247 int ret;
2248
2249 if (!res->flags || !res->parent)
2250 return;
2251
2252 ret = release_resource(res);
2253 dev_printk(KERN_DEBUG, &b->dev,
2254 "busn_res: %pR %s released\n",
2255 res, ret ? "can not be" : "is");
2256 }
2257
pci_scan_root_bus_msi(struct device * parent,int bus,struct pci_ops * ops,void * sysdata,struct list_head * resources,struct msi_controller * msi)2258 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2259 struct pci_ops *ops, void *sysdata,
2260 struct list_head *resources, struct msi_controller *msi)
2261 {
2262 struct resource_entry *window;
2263 bool found = false;
2264 struct pci_bus *b;
2265 int max;
2266
2267 resource_list_for_each_entry(window, resources)
2268 if (window->res->flags & IORESOURCE_BUS) {
2269 found = true;
2270 break;
2271 }
2272
2273 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2274 if (!b)
2275 return NULL;
2276
2277 b->msi = msi;
2278
2279 if (!found) {
2280 dev_info(&b->dev,
2281 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2282 bus);
2283 pci_bus_insert_busn_res(b, bus, 255);
2284 }
2285
2286 max = pci_scan_child_bus(b);
2287
2288 if (!found)
2289 pci_bus_update_busn_res_end(b, max);
2290
2291 return b;
2292 }
2293
pci_scan_root_bus(struct device * parent,int bus,struct pci_ops * ops,void * sysdata,struct list_head * resources)2294 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2295 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2296 {
2297 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2298 NULL);
2299 }
2300 EXPORT_SYMBOL(pci_scan_root_bus);
2301
pci_scan_bus(int bus,struct pci_ops * ops,void * sysdata)2302 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2303 void *sysdata)
2304 {
2305 LIST_HEAD(resources);
2306 struct pci_bus *b;
2307
2308 pci_add_resource(&resources, &ioport_resource);
2309 pci_add_resource(&resources, &iomem_resource);
2310 pci_add_resource(&resources, &busn_resource);
2311 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2312 if (b) {
2313 pci_scan_child_bus(b);
2314 } else {
2315 pci_free_resource_list(&resources);
2316 }
2317 return b;
2318 }
2319 EXPORT_SYMBOL(pci_scan_bus);
2320
2321 /**
2322 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2323 * @bridge: PCI bridge for the bus to scan
2324 *
2325 * Scan a PCI bus and child buses for new devices, add them,
2326 * and enable them, resizing bridge mmio/io resource if necessary
2327 * and possible. The caller must ensure the child devices are already
2328 * removed for resizing to occur.
2329 *
2330 * Returns the max number of subordinate bus discovered.
2331 */
pci_rescan_bus_bridge_resize(struct pci_dev * bridge)2332 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2333 {
2334 unsigned int max;
2335 struct pci_bus *bus = bridge->subordinate;
2336
2337 max = pci_scan_child_bus(bus);
2338
2339 pci_assign_unassigned_bridge_resources(bridge);
2340
2341 pci_bus_add_devices(bus);
2342
2343 return max;
2344 }
2345
2346 /**
2347 * pci_rescan_bus - scan a PCI bus for devices.
2348 * @bus: PCI bus to scan
2349 *
2350 * Scan a PCI bus and child buses for new devices, adds them,
2351 * and enables them.
2352 *
2353 * Returns the max number of subordinate bus discovered.
2354 */
pci_rescan_bus(struct pci_bus * bus)2355 unsigned int pci_rescan_bus(struct pci_bus *bus)
2356 {
2357 unsigned int max;
2358
2359 max = pci_scan_child_bus(bus);
2360 pci_assign_unassigned_bus_resources(bus);
2361 pci_bus_add_devices(bus);
2362
2363 return max;
2364 }
2365 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2366
2367 /*
2368 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2369 * routines should always be executed under this mutex.
2370 */
2371 static DEFINE_MUTEX(pci_rescan_remove_lock);
2372
pci_lock_rescan_remove(void)2373 void pci_lock_rescan_remove(void)
2374 {
2375 mutex_lock(&pci_rescan_remove_lock);
2376 }
2377 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2378
pci_unlock_rescan_remove(void)2379 void pci_unlock_rescan_remove(void)
2380 {
2381 mutex_unlock(&pci_rescan_remove_lock);
2382 }
2383 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2384
pci_sort_bf_cmp(const struct device * d_a,const struct device * d_b)2385 static int __init pci_sort_bf_cmp(const struct device *d_a,
2386 const struct device *d_b)
2387 {
2388 const struct pci_dev *a = to_pci_dev(d_a);
2389 const struct pci_dev *b = to_pci_dev(d_b);
2390
2391 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2392 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2393
2394 if (a->bus->number < b->bus->number) return -1;
2395 else if (a->bus->number > b->bus->number) return 1;
2396
2397 if (a->devfn < b->devfn) return -1;
2398 else if (a->devfn > b->devfn) return 1;
2399
2400 return 0;
2401 }
2402
pci_sort_breadthfirst(void)2403 void __init pci_sort_breadthfirst(void)
2404 {
2405 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2406 }
2407