1/****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 23 * USA 24 * 25 * The full GNU General Public License is included in this distribution 26 * in the file called COPYING. 27 * 28 * Contact Information: 29 * Intel Linux Wireless <ilw@linux.intel.com> 30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 31 * 32 * BSD LICENSE 33 * 34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 35 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 42 * * Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * * Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in 46 * the documentation and/or other materials provided with the 47 * distribution. 48 * * Neither the name Intel Corporation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 *****************************************************************************/ 65#ifndef __iwl_csr_h__ 66#define __iwl_csr_h__ 67/* 68 * CSR (control and status registers) 69 * 70 * CSR registers are mapped directly into PCI bus space, and are accessible 71 * whenever platform supplies power to device, even when device is in 72 * low power states due to driver-invoked device resets 73 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 74 * 75 * Use iwl_write32() and iwl_read32() family to access these registers; 76 * these provide simple PCI bus access, without waking up the MAC. 77 * Do not use iwl_write_direct32() family for these registers; 78 * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 79 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 80 * the CSR registers. 81 * 82 * NOTE: Device does need to be awake in order to read this memory 83 * via CSR_EEPROM and CSR_OTP registers 84 */ 85#define CSR_BASE (0x000) 86 87#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ 88#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ 89#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ 90#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ 91#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ 92#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ 93#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ 94#define CSR_GP_CNTRL (CSR_BASE+0x024) 95 96/* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */ 97#define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) 98 99/* 100 * Hardware revision info 101 * Bit fields: 102 * 31-16: Reserved 103 * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions 104 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 105 * 1-0: "Dash" (-) value, as in A-1, etc. 106 */ 107#define CSR_HW_REV (CSR_BASE+0x028) 108 109/* 110 * EEPROM and OTP (one-time-programmable) memory reads 111 * 112 * NOTE: Device must be awake, initialized via apm_ops.init(), 113 * in order to read. 114 */ 115#define CSR_EEPROM_REG (CSR_BASE+0x02c) 116#define CSR_EEPROM_GP (CSR_BASE+0x030) 117#define CSR_OTP_GP_REG (CSR_BASE+0x034) 118 119#define CSR_GIO_REG (CSR_BASE+0x03C) 120#define CSR_GP_UCODE_REG (CSR_BASE+0x048) 121#define CSR_GP_DRIVER_REG (CSR_BASE+0x050) 122 123/* 124 * UCODE-DRIVER GP (general purpose) mailbox registers. 125 * SET/CLR registers set/clear bit(s) if "1" is written. 126 */ 127#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) 128#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) 129#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) 130#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) 131 132#define CSR_MBOX_SET_REG (CSR_BASE + 0x88) 133 134#define CSR_LED_REG (CSR_BASE+0x094) 135#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0) 136#define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE+0x0A8) /* 6000 and up */ 137 138 139/* GIO Chicken Bits (PCI Express bus link power management) */ 140#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) 141 142/* Analog phase-lock-loop configuration */ 143#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) 144 145/* 146 * CSR HW resources monitor registers 147 */ 148#define CSR_MONITOR_CFG_REG (CSR_BASE+0x214) 149#define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228) 150#define CSR_MONITOR_XTAL_RESOURCES (0x00000010) 151 152/* 153 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 154 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 155 * See also CSR_HW_REV register. 156 * Bit fields: 157 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 158 * 1-0: "Dash" (-) value, as in C-1, etc. 159 */ 160#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) 161 162#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) 163#define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250) 164 165/* Bits for CSR_HW_IF_CONFIG_REG */ 166#define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 167#define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 168#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 169#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 170#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 171#define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 172#define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 173#define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 174 175#define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 176#define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 177#define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 178#define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 179#define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 180#define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 181 182#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 183#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 184#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 185#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 186#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 187#define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 188#define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 189 190#define CSR_MBOX_SET_REG_OS_ALIVE BIT(5) 191 192#define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 193#define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 194 195/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 196 * acknowledged (reset) by host writing "1" to flagged bits. */ 197#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 198#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 199#define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 200#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 201#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 202#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 203#define CSR_INT_BIT_PAGING (1 << 24) /* SDIO PAGING */ 204#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 205#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 206#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 207#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 208#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 209 210#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ 211 CSR_INT_BIT_HW_ERR | \ 212 CSR_INT_BIT_FH_TX | \ 213 CSR_INT_BIT_SW_ERR | \ 214 CSR_INT_BIT_PAGING | \ 215 CSR_INT_BIT_RF_KILL | \ 216 CSR_INT_BIT_SW_RX | \ 217 CSR_INT_BIT_WAKEUP | \ 218 CSR_INT_BIT_ALIVE | \ 219 CSR_INT_BIT_RX_PERIODIC) 220 221/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 222#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 223#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 224#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 225#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 226#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 227#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 228 229#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ 230 CSR_FH_INT_BIT_RX_CHNL1 | \ 231 CSR_FH_INT_BIT_RX_CHNL0) 232 233#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ 234 CSR_FH_INT_BIT_TX_CHNL0) 235 236/* GPIO */ 237#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 238#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 239#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 240 241/* RESET */ 242#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 243#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 244#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 245#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 246#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 247#define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 248 249/* 250 * GP (general purpose) CONTROL REGISTER 251 * Bit fields: 252 * 27: HW_RF_KILL_SW 253 * Indicates state of (platform's) hardware RF-Kill switch 254 * 26-24: POWER_SAVE_TYPE 255 * Indicates current power-saving mode: 256 * 000 -- No power saving 257 * 001 -- MAC power-down 258 * 010 -- PHY (radio) power-down 259 * 011 -- Error 260 * 10: XTAL ON request 261 * 9-6: SYS_CONFIG 262 * Indicates current system configuration, reflecting pins on chip 263 * as forced high/low by device circuit board. 264 * 4: GOING_TO_SLEEP 265 * Indicates MAC is entering a power-saving sleep power-down. 266 * Not a good time to access device-internal resources. 267 * 3: MAC_ACCESS_REQ 268 * Host sets this to request and maintain MAC wakeup, to allow host 269 * access to device-internal resources. Host must wait for 270 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 271 * device registers. 272 * 2: INIT_DONE 273 * Host sets this to put device into fully operational D0 power mode. 274 * Host resets this after SW_RESET to put device into low power mode. 275 * 0: MAC_CLOCK_READY 276 * Indicates MAC (ucode processor, etc.) is powered up and can run. 277 * Internal resources are accessible. 278 * NOTE: This does not indicate that the processor is actually running. 279 * NOTE: This does not indicate that device has completed 280 * init or post-power-down restore of internal SRAM memory. 281 * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 282 * SRAM is restored and uCode is in normal operation mode. 283 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 284 * do not need to save/restore it. 285 * NOTE: After device reset, this bit remains "0" until host sets 286 * INIT_DONE 287 */ 288#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 289#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 290#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 291#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 292#define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400) 293 294#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 295 296#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 297#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 298#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 299 300 301/* HW REV */ 302#define CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 303#define CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 304 305 306/** 307 * hw_rev values 308 */ 309enum { 310 SILICON_A_STEP = 0, 311 SILICON_B_STEP, 312 SILICON_C_STEP, 313}; 314 315 316#define CSR_HW_REV_TYPE_MSK (0x000FFF0) 317#define CSR_HW_REV_TYPE_5300 (0x0000020) 318#define CSR_HW_REV_TYPE_5350 (0x0000030) 319#define CSR_HW_REV_TYPE_5100 (0x0000050) 320#define CSR_HW_REV_TYPE_5150 (0x0000040) 321#define CSR_HW_REV_TYPE_1000 (0x0000060) 322#define CSR_HW_REV_TYPE_6x00 (0x0000070) 323#define CSR_HW_REV_TYPE_6x50 (0x0000080) 324#define CSR_HW_REV_TYPE_6150 (0x0000084) 325#define CSR_HW_REV_TYPE_6x05 (0x00000B0) 326#define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05 327#define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05 328#define CSR_HW_REV_TYPE_2x30 (0x00000C0) 329#define CSR_HW_REV_TYPE_2x00 (0x0000100) 330#define CSR_HW_REV_TYPE_105 (0x0000110) 331#define CSR_HW_REV_TYPE_135 (0x0000120) 332#define CSR_HW_REV_TYPE_7265D (0x0000210) 333#define CSR_HW_REV_TYPE_NONE (0x00001F0) 334 335/* EEPROM REG */ 336#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 337#define CSR_EEPROM_REG_BIT_CMD (0x00000002) 338#define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 339#define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 340 341/* EEPROM GP */ 342#define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 343#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 344#define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 345#define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 346#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 347#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 348 349/* One-time-programmable memory general purpose reg */ 350#define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 351#define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 352#define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 353#define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 354 355/* GP REG */ 356#define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 357#define CSR_GP_REG_NO_POWER_SAVE (0x00000000) 358#define CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 359#define CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 360#define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 361 362 363/* CSR GIO */ 364#define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 365 366/* 367 * UCODE-DRIVER GP (general purpose) mailbox register 1 368 * Host driver and uCode write and/or read this register to communicate with 369 * each other. 370 * Bit fields: 371 * 4: UCODE_DISABLE 372 * Host sets this to request permanent halt of uCode, same as 373 * sending CARD_STATE command with "halt" bit set. 374 * 3: CT_KILL_EXIT 375 * Host sets this to request exit from CT_KILL state, i.e. host thinks 376 * device temperature is low enough to continue normal operation. 377 * 2: CMD_BLOCKED 378 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 379 * to release uCode to clear all Tx and command queues, enter 380 * unassociated mode, and power down. 381 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 382 * 1: SW_BIT_RFKILL 383 * Host sets this when issuing CARD_STATE command to request 384 * device sleep. 385 * 0: MAC_SLEEP 386 * uCode sets this when preparing a power-saving power-down. 387 * uCode resets this when power-up is complete and SRAM is sane. 388 * NOTE: device saves internal SRAM data to host when powering down, 389 * and must restore this data after powering back up. 390 * MAC_SLEEP is the best indication that restore is complete. 391 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 392 * do not need to save/restore it. 393 */ 394#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 395#define CSR_UCODE_SW_BIT_RFKILL (0x00000002) 396#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 397#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 398#define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 399 400/* GP Driver */ 401#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 402#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 403#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 404#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 405#define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 406#define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 407 408#define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 409 410/* GIO Chicken Bits (PCI Express bus link power management) */ 411#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 412#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 413 414/* LED */ 415#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 416#define CSR_LED_REG_TURN_ON (0x60) 417#define CSR_LED_REG_TURN_OFF (0x20) 418 419/* ANA_PLL */ 420#define CSR50_ANA_PLL_CFG_VAL (0x00880300) 421 422/* HPET MEM debug */ 423#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 424 425/* DRAM INT TABLE */ 426#define CSR_DRAM_INT_TBL_ENABLE (1 << 31) 427#define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 428#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 429 430/* 431 * SHR target access (Shared block memory space) 432 * 433 * Shared internal registers can be accessed directly from PCI bus through SHR 434 * arbiter without need for the MAC HW to be powered up. This is possible due to 435 * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and 436 * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers. 437 * 438 * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW 439 * need not be powered up so no "grab inc access" is required. 440 */ 441 442/* 443 * Registers for accessing shared registers (e.g. SHR_APMG_GP1, 444 * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC), 445 * first, write to the control register: 446 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) 447 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access) 448 * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0]. 449 * 450 * To write the register, first, write to the data register 451 * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then: 452 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) 453 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access) 454 */ 455#define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec) 456#define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4) 457 458/* 459 * HBUS (Host-side Bus) 460 * 461 * HBUS registers are mapped directly into PCI bus space, but are used 462 * to indirectly access device's internal memory or registers that 463 * may be powered-down. 464 * 465 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 466 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 467 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 468 * internal resources. 469 * 470 * Do not use iwl_write32()/iwl_read32() family to access these registers; 471 * these provide only simple PCI bus access, without waking up the MAC. 472 */ 473#define HBUS_BASE (0x400) 474 475/* 476 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 477 * structures, error log, event log, verifying uCode load). 478 * First write to address register, then read from or write to data register 479 * to complete the job. Once the address register is set up, accesses to 480 * data registers auto-increment the address by one dword. 481 * Bit usage for address registers (read or write): 482 * 0-31: memory address within device 483 */ 484#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) 485#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) 486#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) 487#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) 488 489/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 490#define HBUS_TARG_MBX_C (HBUS_BASE+0x030) 491#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 492 493/* 494 * Registers for accessing device's internal peripheral registers 495 * (e.g. SCD, BSM, etc.). First write to address register, 496 * then read from or write to data register to complete the job. 497 * Bit usage for address registers (read or write): 498 * 0-15: register address (offset) within device 499 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 500 */ 501#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) 502#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) 503#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) 504#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) 505 506/* Used to enable DBGM */ 507#define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c) 508 509/* 510 * Per-Tx-queue write pointer (index, really!) 511 * Indicates index to next TFD that driver will fill (1 past latest filled). 512 * Bit usage: 513 * 0-7: queue write index 514 * 11-8: queue selector 515 */ 516#define HBUS_TARG_WRPTR (HBUS_BASE+0x060) 517 518/********************************************************** 519 * CSR values 520 **********************************************************/ 521 /* 522 * host interrupt timeout value 523 * used with setting interrupt coalescing timer 524 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 525 * 526 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 527 */ 528#define IWL_HOST_INT_TIMEOUT_MAX (0xFF) 529#define IWL_HOST_INT_TIMEOUT_DEF (0x40) 530#define IWL_HOST_INT_TIMEOUT_MIN (0x0) 531#define IWL_HOST_INT_OPER_MODE BIT(31) 532 533/***************************************************************************** 534 * 7000/3000 series SHR DTS addresses * 535 *****************************************************************************/ 536 537/* Diode Results Register Structure: */ 538enum dtd_diode_reg { 539 DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 540 DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 541 DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 542 DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 543 DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 544 DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 545/* Those are the masks INSIDE the flags bit-field: */ 546 DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 547 DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 548 DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 549 DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 550}; 551 552#endif /* !__iwl_csr_h__ */ 553