1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/dma-mapping.h> 18#include "ath9k.h" 19#include "ar9003_mac.h" 20 21#define BITS_PER_BYTE 8 22#define OFDM_PLCP_BITS 22 23#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) 24#define L_STF 8 25#define L_LTF 8 26#define L_SIG 4 27#define HT_SIG 8 28#define HT_STF 4 29#define HT_LTF(_ns) (4 * (_ns)) 30#define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ 31#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ 32#define TIME_SYMBOLS(t) ((t) >> 2) 33#define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18) 34#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) 35#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) 36 37 38static u16 bits_per_symbol[][2] = { 39 /* 20MHz 40MHz */ 40 { 26, 54 }, /* 0: BPSK */ 41 { 52, 108 }, /* 1: QPSK 1/2 */ 42 { 78, 162 }, /* 2: QPSK 3/4 */ 43 { 104, 216 }, /* 3: 16-QAM 1/2 */ 44 { 156, 324 }, /* 4: 16-QAM 3/4 */ 45 { 208, 432 }, /* 5: 64-QAM 2/3 */ 46 { 234, 486 }, /* 6: 64-QAM 3/4 */ 47 { 260, 540 }, /* 7: 64-QAM 5/6 */ 48}; 49 50static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 51 struct ath_atx_tid *tid, struct sk_buff *skb); 52static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 53 int tx_flags, struct ath_txq *txq); 54static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 55 struct ath_txq *txq, struct list_head *bf_q, 56 struct ath_tx_status *ts, int txok); 57static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 58 struct list_head *head, bool internal); 59static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 60 struct ath_tx_status *ts, int nframes, int nbad, 61 int txok); 62static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 63 int seqno); 64static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 65 struct ath_txq *txq, 66 struct ath_atx_tid *tid, 67 struct sk_buff *skb); 68 69enum { 70 MCS_HT20, 71 MCS_HT20_SGI, 72 MCS_HT40, 73 MCS_HT40_SGI, 74}; 75 76/*********************/ 77/* Aggregation logic */ 78/*********************/ 79 80void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq) 81 __acquires(&txq->axq_lock) 82{ 83 spin_lock_bh(&txq->axq_lock); 84} 85 86void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq) 87 __releases(&txq->axq_lock) 88{ 89 spin_unlock_bh(&txq->axq_lock); 90} 91 92void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) 93 __releases(&txq->axq_lock) 94{ 95 struct sk_buff_head q; 96 struct sk_buff *skb; 97 98 __skb_queue_head_init(&q); 99 skb_queue_splice_init(&txq->complete_q, &q); 100 spin_unlock_bh(&txq->axq_lock); 101 102 while ((skb = __skb_dequeue(&q))) 103 ieee80211_tx_status(sc->hw, skb); 104} 105 106static void ath_tx_queue_tid(struct ath_softc *sc, struct ath_txq *txq, 107 struct ath_atx_tid *tid) 108{ 109 struct list_head *list; 110 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv; 111 struct ath_chanctx *ctx = avp->chanctx; 112 113 if (!ctx) 114 return; 115 116 list = &ctx->acq[TID_TO_WME_AC(tid->tidno)]; 117 if (list_empty(&tid->list)) 118 list_add_tail(&tid->list, list); 119} 120 121static struct ath_frame_info *get_frame_info(struct sk_buff *skb) 122{ 123 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 124 BUILD_BUG_ON(sizeof(struct ath_frame_info) > 125 sizeof(tx_info->rate_driver_data)); 126 return (struct ath_frame_info *) &tx_info->rate_driver_data[0]; 127} 128 129static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno) 130{ 131 if (!tid->an->sta) 132 return; 133 134 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno, 135 seqno << IEEE80211_SEQ_SEQ_SHIFT); 136} 137 138static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta, 139 struct ath_buf *bf) 140{ 141 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates, 142 ARRAY_SIZE(bf->rates)); 143} 144 145static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq, 146 struct sk_buff *skb) 147{ 148 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 149 struct ath_frame_info *fi = get_frame_info(skb); 150 int q = fi->txq; 151 152 if (q < 0) 153 return; 154 155 txq = sc->tx.txq_map[q]; 156 if (WARN_ON(--txq->pending_frames < 0)) 157 txq->pending_frames = 0; 158 159 if (txq->stopped && 160 txq->pending_frames < sc->tx.txq_max_pending[q]) { 161 if (ath9k_is_chanctx_enabled()) 162 ieee80211_wake_queue(sc->hw, info->hw_queue); 163 else 164 ieee80211_wake_queue(sc->hw, q); 165 txq->stopped = false; 166 } 167} 168 169static struct ath_atx_tid * 170ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb) 171{ 172 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 173 return ATH_AN_2_TID(an, tidno); 174} 175 176static bool ath_tid_has_buffered(struct ath_atx_tid *tid) 177{ 178 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q); 179} 180 181static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid) 182{ 183 struct sk_buff *skb; 184 185 skb = __skb_dequeue(&tid->retry_q); 186 if (!skb) 187 skb = __skb_dequeue(&tid->buf_q); 188 189 return skb; 190} 191 192/* 193 * ath_tx_tid_change_state: 194 * - clears a-mpdu flag of previous session 195 * - force sequence number allocation to fix next BlockAck Window 196 */ 197static void 198ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid) 199{ 200 struct ath_txq *txq = tid->txq; 201 struct ieee80211_tx_info *tx_info; 202 struct sk_buff *skb, *tskb; 203 struct ath_buf *bf; 204 struct ath_frame_info *fi; 205 206 skb_queue_walk_safe(&tid->buf_q, skb, tskb) { 207 fi = get_frame_info(skb); 208 bf = fi->bf; 209 210 tx_info = IEEE80211_SKB_CB(skb); 211 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; 212 213 if (bf) 214 continue; 215 216 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 217 if (!bf) { 218 __skb_unlink(skb, &tid->buf_q); 219 ath_txq_skb_done(sc, txq, skb); 220 ieee80211_free_txskb(sc->hw, skb); 221 continue; 222 } 223 } 224 225} 226 227static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 228{ 229 struct ath_txq *txq = tid->txq; 230 struct sk_buff *skb; 231 struct ath_buf *bf; 232 struct list_head bf_head; 233 struct ath_tx_status ts; 234 struct ath_frame_info *fi; 235 bool sendbar = false; 236 237 INIT_LIST_HEAD(&bf_head); 238 239 memset(&ts, 0, sizeof(ts)); 240 241 while ((skb = __skb_dequeue(&tid->retry_q))) { 242 fi = get_frame_info(skb); 243 bf = fi->bf; 244 if (!bf) { 245 ath_txq_skb_done(sc, txq, skb); 246 ieee80211_free_txskb(sc->hw, skb); 247 continue; 248 } 249 250 if (fi->baw_tracked) { 251 ath_tx_update_baw(sc, tid, bf->bf_state.seqno); 252 sendbar = true; 253 } 254 255 list_add_tail(&bf->list, &bf_head); 256 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 257 } 258 259 if (sendbar) { 260 ath_txq_unlock(sc, txq); 261 ath_send_bar(tid, tid->seq_start); 262 ath_txq_lock(sc, txq); 263 } 264} 265 266static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 267 int seqno) 268{ 269 int index, cindex; 270 271 index = ATH_BA_INDEX(tid->seq_start, seqno); 272 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 273 274 __clear_bit(cindex, tid->tx_buf); 275 276 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { 277 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 278 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 279 if (tid->bar_index >= 0) 280 tid->bar_index--; 281 } 282} 283 284static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 285 struct ath_buf *bf) 286{ 287 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 288 u16 seqno = bf->bf_state.seqno; 289 int index, cindex; 290 291 index = ATH_BA_INDEX(tid->seq_start, seqno); 292 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 293 __set_bit(cindex, tid->tx_buf); 294 fi->baw_tracked = 1; 295 296 if (index >= ((tid->baw_tail - tid->baw_head) & 297 (ATH_TID_MAX_BUFS - 1))) { 298 tid->baw_tail = cindex; 299 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 300 } 301} 302 303static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, 304 struct ath_atx_tid *tid) 305 306{ 307 struct sk_buff *skb; 308 struct ath_buf *bf; 309 struct list_head bf_head; 310 struct ath_tx_status ts; 311 struct ath_frame_info *fi; 312 313 memset(&ts, 0, sizeof(ts)); 314 INIT_LIST_HEAD(&bf_head); 315 316 while ((skb = ath_tid_dequeue(tid))) { 317 fi = get_frame_info(skb); 318 bf = fi->bf; 319 320 if (!bf) { 321 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq); 322 continue; 323 } 324 325 list_add_tail(&bf->list, &bf_head); 326 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 327 } 328} 329 330static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, 331 struct sk_buff *skb, int count) 332{ 333 struct ath_frame_info *fi = get_frame_info(skb); 334 struct ath_buf *bf = fi->bf; 335 struct ieee80211_hdr *hdr; 336 int prev = fi->retries; 337 338 TX_STAT_INC(txq->axq_qnum, a_retries); 339 fi->retries += count; 340 341 if (prev > 0) 342 return; 343 344 hdr = (struct ieee80211_hdr *)skb->data; 345 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 346 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 347 sizeof(*hdr), DMA_TO_DEVICE); 348} 349 350static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) 351{ 352 struct ath_buf *bf = NULL; 353 354 spin_lock_bh(&sc->tx.txbuflock); 355 356 if (unlikely(list_empty(&sc->tx.txbuf))) { 357 spin_unlock_bh(&sc->tx.txbuflock); 358 return NULL; 359 } 360 361 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 362 list_del(&bf->list); 363 364 spin_unlock_bh(&sc->tx.txbuflock); 365 366 return bf; 367} 368 369static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) 370{ 371 spin_lock_bh(&sc->tx.txbuflock); 372 list_add_tail(&bf->list, &sc->tx.txbuf); 373 spin_unlock_bh(&sc->tx.txbuflock); 374} 375 376static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) 377{ 378 struct ath_buf *tbf; 379 380 tbf = ath_tx_get_buffer(sc); 381 if (WARN_ON(!tbf)) 382 return NULL; 383 384 ATH_TXBUF_RESET(tbf); 385 386 tbf->bf_mpdu = bf->bf_mpdu; 387 tbf->bf_buf_addr = bf->bf_buf_addr; 388 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); 389 tbf->bf_state = bf->bf_state; 390 tbf->bf_state.stale = false; 391 392 return tbf; 393} 394 395static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf, 396 struct ath_tx_status *ts, int txok, 397 int *nframes, int *nbad) 398{ 399 struct ath_frame_info *fi; 400 u16 seq_st = 0; 401 u32 ba[WME_BA_BMP_SIZE >> 5]; 402 int ba_index; 403 int isaggr = 0; 404 405 *nbad = 0; 406 *nframes = 0; 407 408 isaggr = bf_isaggr(bf); 409 if (isaggr) { 410 seq_st = ts->ts_seqnum; 411 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 412 } 413 414 while (bf) { 415 fi = get_frame_info(bf->bf_mpdu); 416 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno); 417 418 (*nframes)++; 419 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) 420 (*nbad)++; 421 422 bf = bf->bf_next; 423 } 424} 425 426 427static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, 428 struct ath_buf *bf, struct list_head *bf_q, 429 struct ath_tx_status *ts, int txok) 430{ 431 struct ath_node *an = NULL; 432 struct sk_buff *skb; 433 struct ieee80211_sta *sta; 434 struct ieee80211_hw *hw = sc->hw; 435 struct ieee80211_hdr *hdr; 436 struct ieee80211_tx_info *tx_info; 437 struct ath_atx_tid *tid = NULL; 438 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 439 struct list_head bf_head; 440 struct sk_buff_head bf_pending; 441 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; 442 u32 ba[WME_BA_BMP_SIZE >> 5]; 443 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; 444 bool rc_update = true, isba; 445 struct ieee80211_tx_rate rates[4]; 446 struct ath_frame_info *fi; 447 int nframes; 448 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 449 int i, retries; 450 int bar_index = -1; 451 452 skb = bf->bf_mpdu; 453 hdr = (struct ieee80211_hdr *)skb->data; 454 455 tx_info = IEEE80211_SKB_CB(skb); 456 457 memcpy(rates, bf->rates, sizeof(rates)); 458 459 retries = ts->ts_longretry + 1; 460 for (i = 0; i < ts->ts_rateindex; i++) 461 retries += rates[i].count; 462 463 rcu_read_lock(); 464 465 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); 466 if (!sta) { 467 rcu_read_unlock(); 468 469 INIT_LIST_HEAD(&bf_head); 470 while (bf) { 471 bf_next = bf->bf_next; 472 473 if (!bf->bf_state.stale || bf_next != NULL) 474 list_move_tail(&bf->list, &bf_head); 475 476 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0); 477 478 bf = bf_next; 479 } 480 return; 481 } 482 483 an = (struct ath_node *)sta->drv_priv; 484 tid = ath_get_skb_tid(sc, an, skb); 485 seq_first = tid->seq_start; 486 isba = ts->ts_flags & ATH9K_TX_BA; 487 488 /* 489 * The hardware occasionally sends a tx status for the wrong TID. 490 * In this case, the BA status cannot be considered valid and all 491 * subframes need to be retransmitted 492 * 493 * Only BlockAcks have a TID and therefore normal Acks cannot be 494 * checked 495 */ 496 if (isba && tid->tidno != ts->tid) 497 txok = false; 498 499 isaggr = bf_isaggr(bf); 500 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 501 502 if (isaggr && txok) { 503 if (ts->ts_flags & ATH9K_TX_BA) { 504 seq_st = ts->ts_seqnum; 505 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 506 } else { 507 /* 508 * AR5416 can become deaf/mute when BA 509 * issue happens. Chip needs to be reset. 510 * But AP code may have sychronization issues 511 * when perform internal reset in this routine. 512 * Only enable reset in STA mode for now. 513 */ 514 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) 515 needreset = 1; 516 } 517 } 518 519 __skb_queue_head_init(&bf_pending); 520 521 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad); 522 while (bf) { 523 u16 seqno = bf->bf_state.seqno; 524 525 txfail = txpending = sendbar = 0; 526 bf_next = bf->bf_next; 527 528 skb = bf->bf_mpdu; 529 tx_info = IEEE80211_SKB_CB(skb); 530 fi = get_frame_info(skb); 531 532 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) || 533 !tid->active) { 534 /* 535 * Outside of the current BlockAck window, 536 * maybe part of a previous session 537 */ 538 txfail = 1; 539 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) { 540 /* transmit completion, subframe is 541 * acked by block ack */ 542 acked_cnt++; 543 } else if (!isaggr && txok) { 544 /* transmit completion */ 545 acked_cnt++; 546 } else if (flush) { 547 txpending = 1; 548 } else if (fi->retries < ATH_MAX_SW_RETRIES) { 549 if (txok || !an->sleeping) 550 ath_tx_set_retry(sc, txq, bf->bf_mpdu, 551 retries); 552 553 txpending = 1; 554 } else { 555 txfail = 1; 556 txfail_cnt++; 557 bar_index = max_t(int, bar_index, 558 ATH_BA_INDEX(seq_first, seqno)); 559 } 560 561 /* 562 * Make sure the last desc is reclaimed if it 563 * not a holding desc. 564 */ 565 INIT_LIST_HEAD(&bf_head); 566 if (bf_next != NULL || !bf_last->bf_state.stale) 567 list_move_tail(&bf->list, &bf_head); 568 569 if (!txpending) { 570 /* 571 * complete the acked-ones/xretried ones; update 572 * block-ack window 573 */ 574 ath_tx_update_baw(sc, tid, seqno); 575 576 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { 577 memcpy(tx_info->control.rates, rates, sizeof(rates)); 578 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); 579 rc_update = false; 580 if (bf == bf->bf_lastbf) 581 ath_dynack_sample_tx_ts(sc->sc_ah, 582 bf->bf_mpdu, 583 ts); 584 } 585 586 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 587 !txfail); 588 } else { 589 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) { 590 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP; 591 ieee80211_sta_eosp(sta); 592 } 593 /* retry the un-acked ones */ 594 if (bf->bf_next == NULL && bf_last->bf_state.stale) { 595 struct ath_buf *tbf; 596 597 tbf = ath_clone_txbuf(sc, bf_last); 598 /* 599 * Update tx baw and complete the 600 * frame with failed status if we 601 * run out of tx buf. 602 */ 603 if (!tbf) { 604 ath_tx_update_baw(sc, tid, seqno); 605 606 ath_tx_complete_buf(sc, bf, txq, 607 &bf_head, ts, 0); 608 bar_index = max_t(int, bar_index, 609 ATH_BA_INDEX(seq_first, seqno)); 610 break; 611 } 612 613 fi->bf = tbf; 614 } 615 616 /* 617 * Put this buffer to the temporary pending 618 * queue to retain ordering 619 */ 620 __skb_queue_tail(&bf_pending, skb); 621 } 622 623 bf = bf_next; 624 } 625 626 /* prepend un-acked frames to the beginning of the pending frame queue */ 627 if (!skb_queue_empty(&bf_pending)) { 628 if (an->sleeping) 629 ieee80211_sta_set_buffered(sta, tid->tidno, true); 630 631 skb_queue_splice_tail(&bf_pending, &tid->retry_q); 632 if (!an->sleeping) { 633 ath_tx_queue_tid(sc, txq, tid); 634 635 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) 636 tid->clear_ps_filter = true; 637 } 638 } 639 640 if (bar_index >= 0) { 641 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index); 642 643 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq)) 644 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq); 645 646 ath_txq_unlock(sc, txq); 647 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1)); 648 ath_txq_lock(sc, txq); 649 } 650 651 rcu_read_unlock(); 652 653 if (needreset) 654 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR); 655} 656 657static bool bf_is_ampdu_not_probing(struct ath_buf *bf) 658{ 659 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); 660 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 661} 662 663static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, 664 struct ath_tx_status *ts, struct ath_buf *bf, 665 struct list_head *bf_head) 666{ 667 struct ieee80211_tx_info *info; 668 bool txok, flush; 669 670 txok = !(ts->ts_status & ATH9K_TXERR_MASK); 671 flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 672 txq->axq_tx_inprogress = false; 673 674 txq->axq_depth--; 675 if (bf_is_ampdu_not_probing(bf)) 676 txq->axq_ampdu_depth--; 677 678 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, 679 ts->ts_rateindex); 680 if (!bf_isampdu(bf)) { 681 if (!flush) { 682 info = IEEE80211_SKB_CB(bf->bf_mpdu); 683 memcpy(info->control.rates, bf->rates, 684 sizeof(info->control.rates)); 685 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); 686 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts); 687 } 688 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok); 689 } else 690 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok); 691 692 if (!flush) 693 ath_txq_schedule(sc, txq); 694} 695 696static bool ath_lookup_legacy(struct ath_buf *bf) 697{ 698 struct sk_buff *skb; 699 struct ieee80211_tx_info *tx_info; 700 struct ieee80211_tx_rate *rates; 701 int i; 702 703 skb = bf->bf_mpdu; 704 tx_info = IEEE80211_SKB_CB(skb); 705 rates = tx_info->control.rates; 706 707 for (i = 0; i < 4; i++) { 708 if (!rates[i].count || rates[i].idx < 0) 709 break; 710 711 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) 712 return true; 713 } 714 715 return false; 716} 717 718static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 719 struct ath_atx_tid *tid) 720{ 721 struct sk_buff *skb; 722 struct ieee80211_tx_info *tx_info; 723 struct ieee80211_tx_rate *rates; 724 u32 max_4ms_framelen, frmlen; 725 u16 aggr_limit, bt_aggr_limit, legacy = 0; 726 int q = tid->txq->mac80211_qnum; 727 int i; 728 729 skb = bf->bf_mpdu; 730 tx_info = IEEE80211_SKB_CB(skb); 731 rates = bf->rates; 732 733 /* 734 * Find the lowest frame length among the rate series that will have a 735 * 4ms (or TXOP limited) transmit duration. 736 */ 737 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; 738 739 for (i = 0; i < 4; i++) { 740 int modeidx; 741 742 if (!rates[i].count) 743 continue; 744 745 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { 746 legacy = 1; 747 break; 748 } 749 750 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 751 modeidx = MCS_HT40; 752 else 753 modeidx = MCS_HT20; 754 755 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 756 modeidx++; 757 758 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx]; 759 max_4ms_framelen = min(max_4ms_framelen, frmlen); 760 } 761 762 /* 763 * limit aggregate size by the minimum rate if rate selected is 764 * not a probe rate, if rate selected is a probe rate then 765 * avoid aggregation of this packet. 766 */ 767 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) 768 return 0; 769 770 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX); 771 772 /* 773 * Override the default aggregation limit for BTCOEX. 774 */ 775 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen); 776 if (bt_aggr_limit) 777 aggr_limit = bt_aggr_limit; 778 779 if (tid->an->maxampdu) 780 aggr_limit = min(aggr_limit, tid->an->maxampdu); 781 782 return aggr_limit; 783} 784 785/* 786 * Returns the number of delimiters to be added to 787 * meet the minimum required mpdudensity. 788 */ 789static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 790 struct ath_buf *bf, u16 frmlen, 791 bool first_subfrm) 792{ 793#define FIRST_DESC_NDELIMS 60 794 u32 nsymbits, nsymbols; 795 u16 minlen; 796 u8 flags, rix; 797 int width, streams, half_gi, ndelim, mindelim; 798 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 799 800 /* Select standard number of delimiters based on frame length alone */ 801 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 802 803 /* 804 * If encryption enabled, hardware requires some more padding between 805 * subframes. 806 * TODO - this could be improved to be dependent on the rate. 807 * The hardware can keep up at lower rates, but not higher rates 808 */ 809 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) && 810 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) 811 ndelim += ATH_AGGR_ENCRYPTDELIM; 812 813 /* 814 * Add delimiter when using RTS/CTS with aggregation 815 * and non enterprise AR9003 card 816 */ 817 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && 818 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) 819 ndelim = max(ndelim, FIRST_DESC_NDELIMS); 820 821 /* 822 * Convert desired mpdu density from microeconds to bytes based 823 * on highest rate in rate series (i.e. first rate) to determine 824 * required minimum length for subframe. Take into account 825 * whether high rate is 20 or 40Mhz and half or full GI. 826 * 827 * If there is no mpdu density restriction, no further calculation 828 * is needed. 829 */ 830 831 if (tid->an->mpdudensity == 0) 832 return ndelim; 833 834 rix = bf->rates[0].idx; 835 flags = bf->rates[0].flags; 836 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 837 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 838 839 if (half_gi) 840 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); 841 else 842 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); 843 844 if (nsymbols == 0) 845 nsymbols = 1; 846 847 streams = HT_RC_2_STREAMS(rix); 848 nsymbits = bits_per_symbol[rix % 8][width] * streams; 849 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 850 851 if (frmlen < minlen) { 852 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; 853 ndelim = max(mindelim, ndelim); 854 } 855 856 return ndelim; 857} 858 859static struct ath_buf * 860ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq, 861 struct ath_atx_tid *tid, struct sk_buff_head **q) 862{ 863 struct ieee80211_tx_info *tx_info; 864 struct ath_frame_info *fi; 865 struct sk_buff *skb; 866 struct ath_buf *bf; 867 u16 seqno; 868 869 while (1) { 870 *q = &tid->retry_q; 871 if (skb_queue_empty(*q)) 872 *q = &tid->buf_q; 873 874 skb = skb_peek(*q); 875 if (!skb) 876 break; 877 878 fi = get_frame_info(skb); 879 bf = fi->bf; 880 if (!fi->bf) 881 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 882 else 883 bf->bf_state.stale = false; 884 885 if (!bf) { 886 __skb_unlink(skb, *q); 887 ath_txq_skb_done(sc, txq, skb); 888 ieee80211_free_txskb(sc->hw, skb); 889 continue; 890 } 891 892 bf->bf_next = NULL; 893 bf->bf_lastbf = bf; 894 895 tx_info = IEEE80211_SKB_CB(skb); 896 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT; 897 898 /* 899 * No aggregation session is running, but there may be frames 900 * from a previous session or a failed attempt in the queue. 901 * Send them out as normal data frames 902 */ 903 if (!tid->active) 904 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; 905 906 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 907 bf->bf_state.bf_type = 0; 908 return bf; 909 } 910 911 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; 912 seqno = bf->bf_state.seqno; 913 914 /* do not step over block-ack window */ 915 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) 916 break; 917 918 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) { 919 struct ath_tx_status ts = {}; 920 struct list_head bf_head; 921 922 INIT_LIST_HEAD(&bf_head); 923 list_add(&bf->list, &bf_head); 924 __skb_unlink(skb, *q); 925 ath_tx_update_baw(sc, tid, seqno); 926 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 927 continue; 928 } 929 930 return bf; 931 } 932 933 return NULL; 934} 935 936static bool 937ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq, 938 struct ath_atx_tid *tid, struct list_head *bf_q, 939 struct ath_buf *bf_first, struct sk_buff_head *tid_q, 940 int *aggr_len) 941{ 942#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) 943 struct ath_buf *bf = bf_first, *bf_prev = NULL; 944 int nframes = 0, ndelim; 945 u16 aggr_limit = 0, al = 0, bpad = 0, 946 al_delta, h_baw = tid->baw_size / 2; 947 struct ieee80211_tx_info *tx_info; 948 struct ath_frame_info *fi; 949 struct sk_buff *skb; 950 bool closed = false; 951 952 bf = bf_first; 953 aggr_limit = ath_lookup_rate(sc, bf, tid); 954 955 do { 956 skb = bf->bf_mpdu; 957 fi = get_frame_info(skb); 958 959 /* do not exceed aggregation limit */ 960 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; 961 if (nframes) { 962 if (aggr_limit < al + bpad + al_delta || 963 ath_lookup_legacy(bf) || nframes >= h_baw) 964 break; 965 966 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 967 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) || 968 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) 969 break; 970 } 971 972 /* add padding for previous frame to aggregation length */ 973 al += bpad + al_delta; 974 975 /* 976 * Get the delimiters needed to meet the MPDU 977 * density for this node. 978 */ 979 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen, 980 !nframes); 981 bpad = PADBYTES(al_delta) + (ndelim << 2); 982 983 nframes++; 984 bf->bf_next = NULL; 985 986 /* link buffers of this frame to the aggregate */ 987 if (!fi->baw_tracked) 988 ath_tx_addto_baw(sc, tid, bf); 989 bf->bf_state.ndelim = ndelim; 990 991 __skb_unlink(skb, tid_q); 992 list_add_tail(&bf->list, bf_q); 993 if (bf_prev) 994 bf_prev->bf_next = bf; 995 996 bf_prev = bf; 997 998 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); 999 if (!bf) { 1000 closed = true; 1001 break; 1002 } 1003 } while (ath_tid_has_buffered(tid)); 1004 1005 bf = bf_first; 1006 bf->bf_lastbf = bf_prev; 1007 1008 if (bf == bf_prev) { 1009 al = get_frame_info(bf->bf_mpdu)->framelen; 1010 bf->bf_state.bf_type = BUF_AMPDU; 1011 } else { 1012 TX_STAT_INC(txq->axq_qnum, a_aggr); 1013 } 1014 1015 *aggr_len = al; 1016 1017 return closed; 1018#undef PADBYTES 1019} 1020 1021/* 1022 * rix - rate index 1023 * pktlen - total bytes (delims + data + fcs + pads + pad delims) 1024 * width - 0 for 20 MHz, 1 for 40 MHz 1025 * half_gi - to use 4us v/s 3.6 us for symbol time 1026 */ 1027static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, 1028 int width, int half_gi, bool shortPreamble) 1029{ 1030 u32 nbits, nsymbits, duration, nsymbols; 1031 int streams; 1032 1033 /* find number of symbols: PLCP + data */ 1034 streams = HT_RC_2_STREAMS(rix); 1035 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 1036 nsymbits = bits_per_symbol[rix % 8][width] * streams; 1037 nsymbols = (nbits + nsymbits - 1) / nsymbits; 1038 1039 if (!half_gi) 1040 duration = SYMBOL_TIME(nsymbols); 1041 else 1042 duration = SYMBOL_TIME_HALFGI(nsymbols); 1043 1044 /* addup duration for legacy/ht training and signal fields */ 1045 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1046 1047 return duration; 1048} 1049 1050static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi) 1051{ 1052 int streams = HT_RC_2_STREAMS(mcs); 1053 int symbols, bits; 1054 int bytes = 0; 1055 1056 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1057 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec); 1058 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams; 1059 bits -= OFDM_PLCP_BITS; 1060 bytes = bits / 8; 1061 if (bytes > 65532) 1062 bytes = 65532; 1063 1064 return bytes; 1065} 1066 1067void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop) 1068{ 1069 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi; 1070 int mcs; 1071 1072 /* 4ms is the default (and maximum) duration */ 1073 if (!txop || txop > 4096) 1074 txop = 4096; 1075 1076 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20]; 1077 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI]; 1078 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40]; 1079 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI]; 1080 for (mcs = 0; mcs < 32; mcs++) { 1081 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false); 1082 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true); 1083 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false); 1084 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true); 1085 } 1086} 1087 1088static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf, 1089 u8 rateidx, bool is_40, bool is_cck) 1090{ 1091 u8 max_power; 1092 struct sk_buff *skb; 1093 struct ath_frame_info *fi; 1094 struct ieee80211_tx_info *info; 1095 struct ath_hw *ah = sc->sc_ah; 1096 1097 if (sc->tx99_state || !ah->tpc_enabled) 1098 return MAX_RATE_POWER; 1099 1100 skb = bf->bf_mpdu; 1101 fi = get_frame_info(skb); 1102 info = IEEE80211_SKB_CB(skb); 1103 1104 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1105 int txpower = fi->tx_power; 1106 1107 if (is_40) { 1108 u8 power_ht40delta; 1109 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 1110 1111 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) { 1112 bool is_2ghz; 1113 struct modal_eep_header *pmodal; 1114 1115 is_2ghz = info->band == IEEE80211_BAND_2GHZ; 1116 pmodal = &eep->modalHeader[is_2ghz]; 1117 power_ht40delta = pmodal->ht40PowerIncForPdadc; 1118 } else { 1119 power_ht40delta = 2; 1120 } 1121 txpower += power_ht40delta; 1122 } 1123 1124 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) || 1125 AR_SREV_9271(ah)) { 1126 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB; 1127 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 1128 s8 power_offset; 1129 1130 power_offset = ah->eep_ops->get_eeprom(ah, 1131 EEP_PWR_TABLE_OFFSET); 1132 txpower -= 2 * power_offset; 1133 } 1134 1135 if (OLC_FOR_AR9280_20_LATER && is_cck) 1136 txpower -= 2; 1137 1138 txpower = max(txpower, 0); 1139 max_power = min_t(u8, ah->tx_power[rateidx], txpower); 1140 1141 /* XXX: clamp minimum TX power at 1 for AR9160 since if 1142 * max_power is set to 0, frames are transmitted at max 1143 * TX power 1144 */ 1145 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah)) 1146 max_power = 1; 1147 } else if (!bf->bf_state.bfs_paprd) { 1148 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC)) 1149 max_power = min_t(u8, ah->tx_power_stbc[rateidx], 1150 fi->tx_power); 1151 else 1152 max_power = min_t(u8, ah->tx_power[rateidx], 1153 fi->tx_power); 1154 } else { 1155 max_power = ah->paprd_training_power; 1156 } 1157 1158 return max_power; 1159} 1160 1161static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, 1162 struct ath_tx_info *info, int len, bool rts) 1163{ 1164 struct ath_hw *ah = sc->sc_ah; 1165 struct ath_common *common = ath9k_hw_common(ah); 1166 struct sk_buff *skb; 1167 struct ieee80211_tx_info *tx_info; 1168 struct ieee80211_tx_rate *rates; 1169 const struct ieee80211_rate *rate; 1170 struct ieee80211_hdr *hdr; 1171 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 1172 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1173 int i; 1174 u8 rix = 0; 1175 1176 skb = bf->bf_mpdu; 1177 tx_info = IEEE80211_SKB_CB(skb); 1178 rates = bf->rates; 1179 hdr = (struct ieee80211_hdr *)skb->data; 1180 1181 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 1182 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); 1183 info->rtscts_rate = fi->rtscts_rate; 1184 1185 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) { 1186 bool is_40, is_sgi, is_sp, is_cck; 1187 int phy; 1188 1189 if (!rates[i].count || (rates[i].idx < 0)) 1190 continue; 1191 1192 rix = rates[i].idx; 1193 info->rates[i].Tries = rates[i].count; 1194 1195 /* 1196 * Handle RTS threshold for unaggregated HT frames. 1197 */ 1198 if (bf_isampdu(bf) && !bf_isaggr(bf) && 1199 (rates[i].flags & IEEE80211_TX_RC_MCS) && 1200 unlikely(rts_thresh != (u32) -1)) { 1201 if (!rts_thresh || (len > rts_thresh)) 1202 rts = true; 1203 } 1204 1205 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { 1206 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1207 info->flags |= ATH9K_TXDESC_RTSENA; 1208 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 1209 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1210 info->flags |= ATH9K_TXDESC_CTSENA; 1211 } 1212 1213 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1214 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; 1215 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 1216 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 1217 1218 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); 1219 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); 1220 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); 1221 1222 if (rates[i].flags & IEEE80211_TX_RC_MCS) { 1223 /* MCS rates */ 1224 info->rates[i].Rate = rix | 0x80; 1225 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1226 ah->txchainmask, info->rates[i].Rate); 1227 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len, 1228 is_40, is_sgi, is_sp); 1229 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) 1230 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; 1231 1232 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, 1233 is_40, false); 1234 continue; 1235 } 1236 1237 /* legacy rates */ 1238 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx]; 1239 if ((tx_info->band == IEEE80211_BAND_2GHZ) && 1240 !(rate->flags & IEEE80211_RATE_ERP_G)) 1241 phy = WLAN_RC_PHY_CCK; 1242 else 1243 phy = WLAN_RC_PHY_OFDM; 1244 1245 info->rates[i].Rate = rate->hw_value; 1246 if (rate->hw_value_short) { 1247 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1248 info->rates[i].Rate |= rate->hw_value_short; 1249 } else { 1250 is_sp = false; 1251 } 1252 1253 if (bf->bf_state.bfs_paprd) 1254 info->rates[i].ChSel = ah->txchainmask; 1255 else 1256 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1257 ah->txchainmask, info->rates[i].Rate); 1258 1259 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, 1260 phy, rate->bitrate * 100, len, rix, is_sp); 1261 1262 is_cck = IS_CCK_RATE(info->rates[i].Rate); 1263 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false, 1264 is_cck); 1265 } 1266 1267 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1268 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) 1269 info->flags &= ~ATH9K_TXDESC_RTSENA; 1270 1271 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ 1272 if (info->flags & ATH9K_TXDESC_RTSENA) 1273 info->flags &= ~ATH9K_TXDESC_CTSENA; 1274} 1275 1276static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) 1277{ 1278 struct ieee80211_hdr *hdr; 1279 enum ath9k_pkt_type htype; 1280 __le16 fc; 1281 1282 hdr = (struct ieee80211_hdr *)skb->data; 1283 fc = hdr->frame_control; 1284 1285 if (ieee80211_is_beacon(fc)) 1286 htype = ATH9K_PKT_TYPE_BEACON; 1287 else if (ieee80211_is_probe_resp(fc)) 1288 htype = ATH9K_PKT_TYPE_PROBE_RESP; 1289 else if (ieee80211_is_atim(fc)) 1290 htype = ATH9K_PKT_TYPE_ATIM; 1291 else if (ieee80211_is_pspoll(fc)) 1292 htype = ATH9K_PKT_TYPE_PSPOLL; 1293 else 1294 htype = ATH9K_PKT_TYPE_NORMAL; 1295 1296 return htype; 1297} 1298 1299static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, 1300 struct ath_txq *txq, int len) 1301{ 1302 struct ath_hw *ah = sc->sc_ah; 1303 struct ath_buf *bf_first = NULL; 1304 struct ath_tx_info info; 1305 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1306 bool rts = false; 1307 1308 memset(&info, 0, sizeof(info)); 1309 info.is_first = true; 1310 info.is_last = true; 1311 info.qcu = txq->axq_qnum; 1312 1313 while (bf) { 1314 struct sk_buff *skb = bf->bf_mpdu; 1315 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1316 struct ath_frame_info *fi = get_frame_info(skb); 1317 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); 1318 1319 info.type = get_hw_packet_type(skb); 1320 if (bf->bf_next) 1321 info.link = bf->bf_next->bf_daddr; 1322 else 1323 info.link = (sc->tx99_state) ? bf->bf_daddr : 0; 1324 1325 if (!bf_first) { 1326 bf_first = bf; 1327 1328 if (!sc->tx99_state) 1329 info.flags = ATH9K_TXDESC_INTREQ; 1330 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) || 1331 txq == sc->tx.uapsdq) 1332 info.flags |= ATH9K_TXDESC_CLRDMASK; 1333 1334 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1335 info.flags |= ATH9K_TXDESC_NOACK; 1336 if (tx_info->flags & IEEE80211_TX_CTL_LDPC) 1337 info.flags |= ATH9K_TXDESC_LDPC; 1338 1339 if (bf->bf_state.bfs_paprd) 1340 info.flags |= (u32) bf->bf_state.bfs_paprd << 1341 ATH9K_TXDESC_PAPRD_S; 1342 1343 /* 1344 * mac80211 doesn't handle RTS threshold for HT because 1345 * the decision has to be taken based on AMPDU length 1346 * and aggregation is done entirely inside ath9k. 1347 * Set the RTS/CTS flag for the first subframe based 1348 * on the threshold. 1349 */ 1350 if (aggr && (bf == bf_first) && 1351 unlikely(rts_thresh != (u32) -1)) { 1352 /* 1353 * "len" is the size of the entire AMPDU. 1354 */ 1355 if (!rts_thresh || (len > rts_thresh)) 1356 rts = true; 1357 } 1358 1359 if (!aggr) 1360 len = fi->framelen; 1361 1362 ath_buf_set_rate(sc, bf, &info, len, rts); 1363 } 1364 1365 info.buf_addr[0] = bf->bf_buf_addr; 1366 info.buf_len[0] = skb->len; 1367 info.pkt_len = fi->framelen; 1368 info.keyix = fi->keyix; 1369 info.keytype = fi->keytype; 1370 1371 if (aggr) { 1372 if (bf == bf_first) 1373 info.aggr = AGGR_BUF_FIRST; 1374 else if (bf == bf_first->bf_lastbf) 1375 info.aggr = AGGR_BUF_LAST; 1376 else 1377 info.aggr = AGGR_BUF_MIDDLE; 1378 1379 info.ndelim = bf->bf_state.ndelim; 1380 info.aggr_len = len; 1381 } 1382 1383 if (bf == bf_first->bf_lastbf) 1384 bf_first = NULL; 1385 1386 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); 1387 bf = bf->bf_next; 1388 } 1389} 1390 1391static void 1392ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq, 1393 struct ath_atx_tid *tid, struct list_head *bf_q, 1394 struct ath_buf *bf_first, struct sk_buff_head *tid_q) 1395{ 1396 struct ath_buf *bf = bf_first, *bf_prev = NULL; 1397 struct sk_buff *skb; 1398 int nframes = 0; 1399 1400 do { 1401 struct ieee80211_tx_info *tx_info; 1402 skb = bf->bf_mpdu; 1403 1404 nframes++; 1405 __skb_unlink(skb, tid_q); 1406 list_add_tail(&bf->list, bf_q); 1407 if (bf_prev) 1408 bf_prev->bf_next = bf; 1409 bf_prev = bf; 1410 1411 if (nframes >= 2) 1412 break; 1413 1414 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); 1415 if (!bf) 1416 break; 1417 1418 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1419 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) 1420 break; 1421 1422 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1423 } while (1); 1424} 1425 1426static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, 1427 struct ath_atx_tid *tid, bool *stop) 1428{ 1429 struct ath_buf *bf; 1430 struct ieee80211_tx_info *tx_info; 1431 struct sk_buff_head *tid_q; 1432 struct list_head bf_q; 1433 int aggr_len = 0; 1434 bool aggr, last = true; 1435 1436 if (!ath_tid_has_buffered(tid)) 1437 return false; 1438 1439 INIT_LIST_HEAD(&bf_q); 1440 1441 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); 1442 if (!bf) 1443 return false; 1444 1445 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1446 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU); 1447 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) || 1448 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) { 1449 *stop = true; 1450 return false; 1451 } 1452 1453 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1454 if (aggr) 1455 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf, 1456 tid_q, &aggr_len); 1457 else 1458 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q); 1459 1460 if (list_empty(&bf_q)) 1461 return false; 1462 1463 if (tid->clear_ps_filter || tid->an->no_ps_filter) { 1464 tid->clear_ps_filter = false; 1465 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 1466 } 1467 1468 ath_tx_fill_desc(sc, bf, txq, aggr_len); 1469 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1470 return true; 1471} 1472 1473int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 1474 u16 tid, u16 *ssn) 1475{ 1476 struct ath_atx_tid *txtid; 1477 struct ath_txq *txq; 1478 struct ath_node *an; 1479 u8 density; 1480 1481 an = (struct ath_node *)sta->drv_priv; 1482 txtid = ATH_AN_2_TID(an, tid); 1483 txq = txtid->txq; 1484 1485 ath_txq_lock(sc, txq); 1486 1487 /* update ampdu factor/density, they may have changed. This may happen 1488 * in HT IBSS when a beacon with HT-info is received after the station 1489 * has already been added. 1490 */ 1491 if (sta->ht_cap.ht_supported) { 1492 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 1493 sta->ht_cap.ampdu_factor)) - 1; 1494 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); 1495 an->mpdudensity = density; 1496 } 1497 1498 /* force sequence number allocation for pending frames */ 1499 ath_tx_tid_change_state(sc, txtid); 1500 1501 txtid->active = true; 1502 *ssn = txtid->seq_start = txtid->seq_next; 1503 txtid->bar_index = -1; 1504 1505 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf)); 1506 txtid->baw_head = txtid->baw_tail = 0; 1507 1508 ath_txq_unlock_complete(sc, txq); 1509 1510 return 0; 1511} 1512 1513void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 1514{ 1515 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1516 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); 1517 struct ath_txq *txq = txtid->txq; 1518 1519 ath_txq_lock(sc, txq); 1520 txtid->active = false; 1521 ath_tx_flush_tid(sc, txtid); 1522 ath_tx_tid_change_state(sc, txtid); 1523 ath_txq_unlock_complete(sc, txq); 1524} 1525 1526void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 1527 struct ath_node *an) 1528{ 1529 struct ath_atx_tid *tid; 1530 struct ath_txq *txq; 1531 bool buffered; 1532 int tidno; 1533 1534 for (tidno = 0, tid = &an->tid[tidno]; 1535 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { 1536 1537 txq = tid->txq; 1538 1539 ath_txq_lock(sc, txq); 1540 1541 if (list_empty(&tid->list)) { 1542 ath_txq_unlock(sc, txq); 1543 continue; 1544 } 1545 1546 buffered = ath_tid_has_buffered(tid); 1547 1548 list_del_init(&tid->list); 1549 1550 ath_txq_unlock(sc, txq); 1551 1552 ieee80211_sta_set_buffered(sta, tidno, buffered); 1553 } 1554} 1555 1556void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an) 1557{ 1558 struct ath_atx_tid *tid; 1559 struct ath_txq *txq; 1560 int tidno; 1561 1562 for (tidno = 0, tid = &an->tid[tidno]; 1563 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { 1564 1565 txq = tid->txq; 1566 1567 ath_txq_lock(sc, txq); 1568 tid->clear_ps_filter = true; 1569 1570 if (ath_tid_has_buffered(tid)) { 1571 ath_tx_queue_tid(sc, txq, tid); 1572 ath_txq_schedule(sc, txq); 1573 } 1574 1575 ath_txq_unlock_complete(sc, txq); 1576 } 1577} 1578 1579void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, 1580 u16 tidno) 1581{ 1582 struct ath_atx_tid *tid; 1583 struct ath_node *an; 1584 struct ath_txq *txq; 1585 1586 an = (struct ath_node *)sta->drv_priv; 1587 tid = ATH_AN_2_TID(an, tidno); 1588 txq = tid->txq; 1589 1590 ath_txq_lock(sc, txq); 1591 1592 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; 1593 1594 if (ath_tid_has_buffered(tid)) { 1595 ath_tx_queue_tid(sc, txq, tid); 1596 ath_txq_schedule(sc, txq); 1597 } 1598 1599 ath_txq_unlock_complete(sc, txq); 1600} 1601 1602void ath9k_release_buffered_frames(struct ieee80211_hw *hw, 1603 struct ieee80211_sta *sta, 1604 u16 tids, int nframes, 1605 enum ieee80211_frame_release_type reason, 1606 bool more_data) 1607{ 1608 struct ath_softc *sc = hw->priv; 1609 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1610 struct ath_txq *txq = sc->tx.uapsdq; 1611 struct ieee80211_tx_info *info; 1612 struct list_head bf_q; 1613 struct ath_buf *bf_tail = NULL, *bf; 1614 struct sk_buff_head *tid_q; 1615 int sent = 0; 1616 int i; 1617 1618 INIT_LIST_HEAD(&bf_q); 1619 for (i = 0; tids && nframes; i++, tids >>= 1) { 1620 struct ath_atx_tid *tid; 1621 1622 if (!(tids & 1)) 1623 continue; 1624 1625 tid = ATH_AN_2_TID(an, i); 1626 1627 ath_txq_lock(sc, tid->txq); 1628 while (nframes > 0) { 1629 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q); 1630 if (!bf) 1631 break; 1632 1633 __skb_unlink(bf->bf_mpdu, tid_q); 1634 list_add_tail(&bf->list, &bf_q); 1635 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1636 if (bf_isampdu(bf)) { 1637 ath_tx_addto_baw(sc, tid, bf); 1638 bf->bf_state.bf_type &= ~BUF_AGGR; 1639 } 1640 if (bf_tail) 1641 bf_tail->bf_next = bf; 1642 1643 bf_tail = bf; 1644 nframes--; 1645 sent++; 1646 TX_STAT_INC(txq->axq_qnum, a_queued_hw); 1647 1648 if (an->sta && !ath_tid_has_buffered(tid)) 1649 ieee80211_sta_set_buffered(an->sta, i, false); 1650 } 1651 ath_txq_unlock_complete(sc, tid->txq); 1652 } 1653 1654 if (list_empty(&bf_q)) 1655 return; 1656 1657 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu); 1658 info->flags |= IEEE80211_TX_STATUS_EOSP; 1659 1660 bf = list_first_entry(&bf_q, struct ath_buf, list); 1661 ath_txq_lock(sc, txq); 1662 ath_tx_fill_desc(sc, bf, txq, 0); 1663 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1664 ath_txq_unlock(sc, txq); 1665} 1666 1667/********************/ 1668/* Queue Management */ 1669/********************/ 1670 1671struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 1672{ 1673 struct ath_hw *ah = sc->sc_ah; 1674 struct ath9k_tx_queue_info qi; 1675 static const int subtype_txq_to_hwq[] = { 1676 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE, 1677 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK, 1678 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI, 1679 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO, 1680 }; 1681 int axq_qnum, i; 1682 1683 memset(&qi, 0, sizeof(qi)); 1684 qi.tqi_subtype = subtype_txq_to_hwq[subtype]; 1685 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; 1686 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; 1687 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; 1688 qi.tqi_physCompBuf = 0; 1689 1690 /* 1691 * Enable interrupts only for EOL and DESC conditions. 1692 * We mark tx descriptors to receive a DESC interrupt 1693 * when a tx queue gets deep; otherwise waiting for the 1694 * EOL to reap descriptors. Note that this is done to 1695 * reduce interrupt load and this only defers reaping 1696 * descriptors, never transmitting frames. Aside from 1697 * reducing interrupts this also permits more concurrency. 1698 * The only potential downside is if the tx queue backs 1699 * up in which case the top half of the kernel may backup 1700 * due to a lack of tx descriptors. 1701 * 1702 * The UAPSD queue is an exception, since we take a desc- 1703 * based intr on the EOSP frames. 1704 */ 1705 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1706 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; 1707 } else { 1708 if (qtype == ATH9K_TX_QUEUE_UAPSD) 1709 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 1710 else 1711 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | 1712 TXQ_FLAG_TXDESCINT_ENABLE; 1713 } 1714 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); 1715 if (axq_qnum == -1) { 1716 /* 1717 * NB: don't print a message, this happens 1718 * normally on parts with too few tx queues 1719 */ 1720 return NULL; 1721 } 1722 if (!ATH_TXQ_SETUP(sc, axq_qnum)) { 1723 struct ath_txq *txq = &sc->tx.txq[axq_qnum]; 1724 1725 txq->axq_qnum = axq_qnum; 1726 txq->mac80211_qnum = -1; 1727 txq->axq_link = NULL; 1728 __skb_queue_head_init(&txq->complete_q); 1729 INIT_LIST_HEAD(&txq->axq_q); 1730 spin_lock_init(&txq->axq_lock); 1731 txq->axq_depth = 0; 1732 txq->axq_ampdu_depth = 0; 1733 txq->axq_tx_inprogress = false; 1734 sc->tx.txqsetup |= 1<<axq_qnum; 1735 1736 txq->txq_headidx = txq->txq_tailidx = 0; 1737 for (i = 0; i < ATH_TXFIFO_DEPTH; i++) 1738 INIT_LIST_HEAD(&txq->txq_fifo[i]); 1739 } 1740 return &sc->tx.txq[axq_qnum]; 1741} 1742 1743int ath_txq_update(struct ath_softc *sc, int qnum, 1744 struct ath9k_tx_queue_info *qinfo) 1745{ 1746 struct ath_hw *ah = sc->sc_ah; 1747 int error = 0; 1748 struct ath9k_tx_queue_info qi; 1749 1750 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); 1751 1752 ath9k_hw_get_txq_props(ah, qnum, &qi); 1753 qi.tqi_aifs = qinfo->tqi_aifs; 1754 qi.tqi_cwmin = qinfo->tqi_cwmin; 1755 qi.tqi_cwmax = qinfo->tqi_cwmax; 1756 qi.tqi_burstTime = qinfo->tqi_burstTime; 1757 qi.tqi_readyTime = qinfo->tqi_readyTime; 1758 1759 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 1760 ath_err(ath9k_hw_common(sc->sc_ah), 1761 "Unable to update hardware queue %u!\n", qnum); 1762 error = -EIO; 1763 } else { 1764 ath9k_hw_resettxqueue(ah, qnum); 1765 } 1766 1767 return error; 1768} 1769 1770int ath_cabq_update(struct ath_softc *sc) 1771{ 1772 struct ath9k_tx_queue_info qi; 1773 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon; 1774 int qnum = sc->beacon.cabq->axq_qnum; 1775 1776 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); 1777 1778 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) * 1779 ATH_CABQ_READY_TIME) / 100; 1780 ath_txq_update(sc, qnum, &qi); 1781 1782 return 0; 1783} 1784 1785static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq, 1786 struct list_head *list) 1787{ 1788 struct ath_buf *bf, *lastbf; 1789 struct list_head bf_head; 1790 struct ath_tx_status ts; 1791 1792 memset(&ts, 0, sizeof(ts)); 1793 ts.ts_status = ATH9K_TX_FLUSH; 1794 INIT_LIST_HEAD(&bf_head); 1795 1796 while (!list_empty(list)) { 1797 bf = list_first_entry(list, struct ath_buf, list); 1798 1799 if (bf->bf_state.stale) { 1800 list_del(&bf->list); 1801 1802 ath_tx_return_buffer(sc, bf); 1803 continue; 1804 } 1805 1806 lastbf = bf->bf_lastbf; 1807 list_cut_position(&bf_head, list, &lastbf->list); 1808 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 1809 } 1810} 1811 1812/* 1813 * Drain a given TX queue (could be Beacon or Data) 1814 * 1815 * This assumes output has been stopped and 1816 * we do not need to block ath_tx_tasklet. 1817 */ 1818void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq) 1819{ 1820 ath_txq_lock(sc, txq); 1821 1822 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1823 int idx = txq->txq_tailidx; 1824 1825 while (!list_empty(&txq->txq_fifo[idx])) { 1826 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]); 1827 1828 INCR(idx, ATH_TXFIFO_DEPTH); 1829 } 1830 txq->txq_tailidx = idx; 1831 } 1832 1833 txq->axq_link = NULL; 1834 txq->axq_tx_inprogress = false; 1835 ath_drain_txq_list(sc, txq, &txq->axq_q); 1836 1837 ath_txq_unlock_complete(sc, txq); 1838} 1839 1840bool ath_drain_all_txq(struct ath_softc *sc) 1841{ 1842 struct ath_hw *ah = sc->sc_ah; 1843 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1844 struct ath_txq *txq; 1845 int i; 1846 u32 npend = 0; 1847 1848 if (test_bit(ATH_OP_INVALID, &common->op_flags)) 1849 return true; 1850 1851 ath9k_hw_abort_tx_dma(ah); 1852 1853 /* Check if any queue remains active */ 1854 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1855 if (!ATH_TXQ_SETUP(sc, i)) 1856 continue; 1857 1858 if (!sc->tx.txq[i].axq_depth) 1859 continue; 1860 1861 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) 1862 npend |= BIT(i); 1863 } 1864 1865 if (npend) { 1866 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR); 1867 ath_dbg(common, RESET, 1868 "Failed to stop TX DMA, queues=0x%03x!\n", npend); 1869 } 1870 1871 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1872 if (!ATH_TXQ_SETUP(sc, i)) 1873 continue; 1874 1875 /* 1876 * The caller will resume queues with ieee80211_wake_queues. 1877 * Mark the queue as not stopped to prevent ath_tx_complete 1878 * from waking the queue too early. 1879 */ 1880 txq = &sc->tx.txq[i]; 1881 txq->stopped = false; 1882 ath_draintxq(sc, txq); 1883 } 1884 1885 return !npend; 1886} 1887 1888void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1889{ 1890 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); 1891 sc->tx.txqsetup &= ~(1<<txq->axq_qnum); 1892} 1893 1894/* For each acq entry, for each tid, try to schedule packets 1895 * for transmit until ampdu_depth has reached min Q depth. 1896 */ 1897void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) 1898{ 1899 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1900 struct ath_atx_tid *tid, *last_tid; 1901 struct list_head *tid_list; 1902 bool sent = false; 1903 1904 if (txq->mac80211_qnum < 0) 1905 return; 1906 1907 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 1908 return; 1909 1910 spin_lock_bh(&sc->chan_lock); 1911 tid_list = &sc->cur_chan->acq[txq->mac80211_qnum]; 1912 1913 if (list_empty(tid_list)) { 1914 spin_unlock_bh(&sc->chan_lock); 1915 return; 1916 } 1917 1918 rcu_read_lock(); 1919 1920 last_tid = list_entry(tid_list->prev, struct ath_atx_tid, list); 1921 while (!list_empty(tid_list)) { 1922 bool stop = false; 1923 1924 if (sc->cur_chan->stopped) 1925 break; 1926 1927 tid = list_first_entry(tid_list, struct ath_atx_tid, list); 1928 list_del_init(&tid->list); 1929 1930 if (ath_tx_sched_aggr(sc, txq, tid, &stop)) 1931 sent = true; 1932 1933 /* 1934 * add tid to round-robin queue if more frames 1935 * are pending for the tid 1936 */ 1937 if (ath_tid_has_buffered(tid)) 1938 ath_tx_queue_tid(sc, txq, tid); 1939 1940 if (stop) 1941 break; 1942 1943 if (tid == last_tid) { 1944 if (!sent) 1945 break; 1946 1947 sent = false; 1948 last_tid = list_entry(tid_list->prev, 1949 struct ath_atx_tid, list); 1950 } 1951 } 1952 1953 rcu_read_unlock(); 1954 spin_unlock_bh(&sc->chan_lock); 1955} 1956 1957void ath_txq_schedule_all(struct ath_softc *sc) 1958{ 1959 struct ath_txq *txq; 1960 int i; 1961 1962 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 1963 txq = sc->tx.txq_map[i]; 1964 1965 spin_lock_bh(&txq->axq_lock); 1966 ath_txq_schedule(sc, txq); 1967 spin_unlock_bh(&txq->axq_lock); 1968 } 1969} 1970 1971/***********/ 1972/* TX, DMA */ 1973/***********/ 1974 1975/* 1976 * Insert a chain of ath_buf (descriptors) on a txq and 1977 * assume the descriptors are already chained together by caller. 1978 */ 1979static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 1980 struct list_head *head, bool internal) 1981{ 1982 struct ath_hw *ah = sc->sc_ah; 1983 struct ath_common *common = ath9k_hw_common(ah); 1984 struct ath_buf *bf, *bf_last; 1985 bool puttxbuf = false; 1986 bool edma; 1987 1988 /* 1989 * Insert the frame on the outbound list and 1990 * pass it on to the hardware. 1991 */ 1992 1993 if (list_empty(head)) 1994 return; 1995 1996 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1997 bf = list_first_entry(head, struct ath_buf, list); 1998 bf_last = list_entry(head->prev, struct ath_buf, list); 1999 2000 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", 2001 txq->axq_qnum, txq->axq_depth); 2002 2003 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { 2004 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); 2005 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); 2006 puttxbuf = true; 2007 } else { 2008 list_splice_tail_init(head, &txq->axq_q); 2009 2010 if (txq->axq_link) { 2011 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); 2012 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", 2013 txq->axq_qnum, txq->axq_link, 2014 ito64(bf->bf_daddr), bf->bf_desc); 2015 } else if (!edma) 2016 puttxbuf = true; 2017 2018 txq->axq_link = bf_last->bf_desc; 2019 } 2020 2021 if (puttxbuf) { 2022 TX_STAT_INC(txq->axq_qnum, puttxbuf); 2023 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 2024 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", 2025 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 2026 } 2027 2028 if (!edma || sc->tx99_state) { 2029 TX_STAT_INC(txq->axq_qnum, txstart); 2030 ath9k_hw_txstart(ah, txq->axq_qnum); 2031 } 2032 2033 if (!internal) { 2034 while (bf) { 2035 txq->axq_depth++; 2036 if (bf_is_ampdu_not_probing(bf)) 2037 txq->axq_ampdu_depth++; 2038 2039 bf_last = bf->bf_lastbf; 2040 bf = bf_last->bf_next; 2041 bf_last->bf_next = NULL; 2042 } 2043 } 2044} 2045 2046static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 2047 struct ath_atx_tid *tid, struct sk_buff *skb) 2048{ 2049 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2050 struct ath_frame_info *fi = get_frame_info(skb); 2051 struct list_head bf_head; 2052 struct ath_buf *bf = fi->bf; 2053 2054 INIT_LIST_HEAD(&bf_head); 2055 list_add_tail(&bf->list, &bf_head); 2056 bf->bf_state.bf_type = 0; 2057 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 2058 bf->bf_state.bf_type = BUF_AMPDU; 2059 ath_tx_addto_baw(sc, tid, bf); 2060 } 2061 2062 bf->bf_next = NULL; 2063 bf->bf_lastbf = bf; 2064 ath_tx_fill_desc(sc, bf, txq, fi->framelen); 2065 ath_tx_txqaddbuf(sc, txq, &bf_head, false); 2066 TX_STAT_INC(txq->axq_qnum, queued); 2067} 2068 2069static void setup_frame_info(struct ieee80211_hw *hw, 2070 struct ieee80211_sta *sta, 2071 struct sk_buff *skb, 2072 int framelen) 2073{ 2074 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2075 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 2076 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2077 const struct ieee80211_rate *rate; 2078 struct ath_frame_info *fi = get_frame_info(skb); 2079 struct ath_node *an = NULL; 2080 enum ath9k_key_type keytype; 2081 bool short_preamble = false; 2082 u8 txpower; 2083 2084 /* 2085 * We check if Short Preamble is needed for the CTS rate by 2086 * checking the BSS's global flag. 2087 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 2088 */ 2089 if (tx_info->control.vif && 2090 tx_info->control.vif->bss_conf.use_short_preamble) 2091 short_preamble = true; 2092 2093 rate = ieee80211_get_rts_cts_rate(hw, tx_info); 2094 keytype = ath9k_cmn_get_hw_crypto_keytype(skb); 2095 2096 if (sta) 2097 an = (struct ath_node *) sta->drv_priv; 2098 2099 if (tx_info->control.vif) { 2100 struct ieee80211_vif *vif = tx_info->control.vif; 2101 2102 txpower = 2 * vif->bss_conf.txpower; 2103 } else { 2104 struct ath_softc *sc = hw->priv; 2105 2106 txpower = sc->cur_chan->cur_txpower; 2107 } 2108 2109 memset(fi, 0, sizeof(*fi)); 2110 fi->txq = -1; 2111 if (hw_key) 2112 fi->keyix = hw_key->hw_key_idx; 2113 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0) 2114 fi->keyix = an->ps_key; 2115 else 2116 fi->keyix = ATH9K_TXKEYIX_INVALID; 2117 fi->keytype = keytype; 2118 fi->framelen = framelen; 2119 fi->tx_power = txpower; 2120 2121 if (!rate) 2122 return; 2123 fi->rtscts_rate = rate->hw_value; 2124 if (short_preamble) 2125 fi->rtscts_rate |= rate->hw_value_short; 2126} 2127 2128u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) 2129{ 2130 struct ath_hw *ah = sc->sc_ah; 2131 struct ath9k_channel *curchan = ah->curchan; 2132 2133 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) && 2134 (chainmask == 0x7) && (rate < 0x90)) 2135 return 0x3; 2136 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) && 2137 IS_CCK_RATE(rate)) 2138 return 0x2; 2139 else 2140 return chainmask; 2141} 2142 2143/* 2144 * Assign a descriptor (and sequence number if necessary, 2145 * and map buffer for DMA. Frees skb on error 2146 */ 2147static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 2148 struct ath_txq *txq, 2149 struct ath_atx_tid *tid, 2150 struct sk_buff *skb) 2151{ 2152 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2153 struct ath_frame_info *fi = get_frame_info(skb); 2154 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2155 struct ath_buf *bf; 2156 int fragno; 2157 u16 seqno; 2158 2159 bf = ath_tx_get_buffer(sc); 2160 if (!bf) { 2161 ath_dbg(common, XMIT, "TX buffers are full\n"); 2162 return NULL; 2163 } 2164 2165 ATH_TXBUF_RESET(bf); 2166 2167 if (tid && ieee80211_is_data_present(hdr->frame_control)) { 2168 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 2169 seqno = tid->seq_next; 2170 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); 2171 2172 if (fragno) 2173 hdr->seq_ctrl |= cpu_to_le16(fragno); 2174 2175 if (!ieee80211_has_morefrags(hdr->frame_control)) 2176 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 2177 2178 bf->bf_state.seqno = seqno; 2179 } 2180 2181 bf->bf_mpdu = skb; 2182 2183 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 2184 skb->len, DMA_TO_DEVICE); 2185 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 2186 bf->bf_mpdu = NULL; 2187 bf->bf_buf_addr = 0; 2188 ath_err(ath9k_hw_common(sc->sc_ah), 2189 "dma_mapping_error() on TX\n"); 2190 ath_tx_return_buffer(sc, bf); 2191 return NULL; 2192 } 2193 2194 fi->bf = bf; 2195 2196 return bf; 2197} 2198 2199void ath_assign_seq(struct ath_common *common, struct sk_buff *skb) 2200{ 2201 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2202 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2203 struct ieee80211_vif *vif = info->control.vif; 2204 struct ath_vif *avp; 2205 2206 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) 2207 return; 2208 2209 if (!vif) 2210 return; 2211 2212 avp = (struct ath_vif *)vif->drv_priv; 2213 2214 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 2215 avp->seq_no += 0x10; 2216 2217 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 2218 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no); 2219} 2220 2221static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, 2222 struct ath_tx_control *txctl) 2223{ 2224 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2225 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2226 struct ieee80211_sta *sta = txctl->sta; 2227 struct ieee80211_vif *vif = info->control.vif; 2228 struct ath_vif *avp; 2229 struct ath_softc *sc = hw->priv; 2230 int frmlen = skb->len + FCS_LEN; 2231 int padpos, padsize; 2232 2233 /* NOTE: sta can be NULL according to net/mac80211.h */ 2234 if (sta) 2235 txctl->an = (struct ath_node *)sta->drv_priv; 2236 else if (vif && ieee80211_is_data(hdr->frame_control)) { 2237 avp = (void *)vif->drv_priv; 2238 txctl->an = &avp->mcast_node; 2239 } 2240 2241 if (info->control.hw_key) 2242 frmlen += info->control.hw_key->icv_len; 2243 2244 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb); 2245 2246 if ((vif && vif->type != NL80211_IFTYPE_AP && 2247 vif->type != NL80211_IFTYPE_AP_VLAN) || 2248 !ieee80211_is_data(hdr->frame_control)) 2249 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 2250 2251 /* Add the padding after the header if this is not already done */ 2252 padpos = ieee80211_hdrlen(hdr->frame_control); 2253 padsize = padpos & 3; 2254 if (padsize && skb->len > padpos) { 2255 if (skb_headroom(skb) < padsize) 2256 return -ENOMEM; 2257 2258 skb_push(skb, padsize); 2259 memmove(skb->data, skb->data + padsize, padpos); 2260 } 2261 2262 setup_frame_info(hw, sta, skb, frmlen); 2263 return 0; 2264} 2265 2266 2267/* Upon failure caller should free skb */ 2268int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 2269 struct ath_tx_control *txctl) 2270{ 2271 struct ieee80211_hdr *hdr; 2272 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2273 struct ieee80211_sta *sta = txctl->sta; 2274 struct ieee80211_vif *vif = info->control.vif; 2275 struct ath_frame_info *fi = get_frame_info(skb); 2276 struct ath_vif *avp = NULL; 2277 struct ath_softc *sc = hw->priv; 2278 struct ath_txq *txq = txctl->txq; 2279 struct ath_atx_tid *tid = NULL; 2280 struct ath_buf *bf; 2281 bool queue, skip_uapsd = false, ps_resp; 2282 int q, ret; 2283 2284 if (vif) 2285 avp = (void *)vif->drv_priv; 2286 2287 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) 2288 txctl->force_channel = true; 2289 2290 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE); 2291 2292 ret = ath_tx_prepare(hw, skb, txctl); 2293 if (ret) 2294 return ret; 2295 2296 hdr = (struct ieee80211_hdr *) skb->data; 2297 /* 2298 * At this point, the vif, hw_key and sta pointers in the tx control 2299 * info are no longer valid (overwritten by the ath_frame_info data. 2300 */ 2301 2302 q = skb_get_queue_mapping(skb); 2303 2304 ath_txq_lock(sc, txq); 2305 if (txq == sc->tx.txq_map[q]) { 2306 fi->txq = q; 2307 if (++txq->pending_frames > sc->tx.txq_max_pending[q] && 2308 !txq->stopped) { 2309 if (ath9k_is_chanctx_enabled()) 2310 ieee80211_stop_queue(sc->hw, info->hw_queue); 2311 else 2312 ieee80211_stop_queue(sc->hw, q); 2313 txq->stopped = true; 2314 } 2315 } 2316 2317 queue = ieee80211_is_data_present(hdr->frame_control); 2318 2319 /* Force queueing of all frames that belong to a virtual interface on 2320 * a different channel context, to ensure that they are sent on the 2321 * correct channel. 2322 */ 2323 if (((avp && avp->chanctx != sc->cur_chan) || 2324 sc->cur_chan->stopped) && !txctl->force_channel) { 2325 if (!txctl->an) 2326 txctl->an = &avp->mcast_node; 2327 queue = true; 2328 skip_uapsd = true; 2329 } 2330 2331 if (txctl->an && queue) 2332 tid = ath_get_skb_tid(sc, txctl->an, skb); 2333 2334 if (!skip_uapsd && ps_resp) { 2335 ath_txq_unlock(sc, txq); 2336 txq = sc->tx.uapsdq; 2337 ath_txq_lock(sc, txq); 2338 } else if (txctl->an && queue) { 2339 WARN_ON(tid->txq != txctl->txq); 2340 2341 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) 2342 tid->clear_ps_filter = true; 2343 2344 /* 2345 * Add this frame to software queue for scheduling later 2346 * for aggregation. 2347 */ 2348 TX_STAT_INC(txq->axq_qnum, a_queued_sw); 2349 __skb_queue_tail(&tid->buf_q, skb); 2350 if (!txctl->an->sleeping) 2351 ath_tx_queue_tid(sc, txq, tid); 2352 2353 ath_txq_schedule(sc, txq); 2354 goto out; 2355 } 2356 2357 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 2358 if (!bf) { 2359 ath_txq_skb_done(sc, txq, skb); 2360 if (txctl->paprd) 2361 dev_kfree_skb_any(skb); 2362 else 2363 ieee80211_free_txskb(sc->hw, skb); 2364 goto out; 2365 } 2366 2367 bf->bf_state.bfs_paprd = txctl->paprd; 2368 2369 if (txctl->paprd) 2370 bf->bf_state.bfs_paprd_timestamp = jiffies; 2371 2372 ath_set_rates(vif, sta, bf); 2373 ath_tx_send_normal(sc, txq, tid, skb); 2374 2375out: 2376 ath_txq_unlock(sc, txq); 2377 2378 return 0; 2379} 2380 2381void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2382 struct sk_buff *skb) 2383{ 2384 struct ath_softc *sc = hw->priv; 2385 struct ath_tx_control txctl = { 2386 .txq = sc->beacon.cabq 2387 }; 2388 struct ath_tx_info info = {}; 2389 struct ieee80211_hdr *hdr; 2390 struct ath_buf *bf_tail = NULL; 2391 struct ath_buf *bf; 2392 LIST_HEAD(bf_q); 2393 int duration = 0; 2394 int max_duration; 2395 2396 max_duration = 2397 sc->cur_chan->beacon.beacon_interval * 1000 * 2398 sc->cur_chan->beacon.dtim_period / ATH_BCBUF; 2399 2400 do { 2401 struct ath_frame_info *fi = get_frame_info(skb); 2402 2403 if (ath_tx_prepare(hw, skb, &txctl)) 2404 break; 2405 2406 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb); 2407 if (!bf) 2408 break; 2409 2410 bf->bf_lastbf = bf; 2411 ath_set_rates(vif, NULL, bf); 2412 ath_buf_set_rate(sc, bf, &info, fi->framelen, false); 2413 duration += info.rates[0].PktDuration; 2414 if (bf_tail) 2415 bf_tail->bf_next = bf; 2416 2417 list_add_tail(&bf->list, &bf_q); 2418 bf_tail = bf; 2419 skb = NULL; 2420 2421 if (duration > max_duration) 2422 break; 2423 2424 skb = ieee80211_get_buffered_bc(hw, vif); 2425 } while(skb); 2426 2427 if (skb) 2428 ieee80211_free_txskb(hw, skb); 2429 2430 if (list_empty(&bf_q)) 2431 return; 2432 2433 bf = list_first_entry(&bf_q, struct ath_buf, list); 2434 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; 2435 2436 if (hdr->frame_control & cpu_to_le16(IEEE80211_FCTL_MOREDATA)) { 2437 hdr->frame_control &= ~cpu_to_le16(IEEE80211_FCTL_MOREDATA); 2438 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 2439 sizeof(*hdr), DMA_TO_DEVICE); 2440 } 2441 2442 ath_txq_lock(sc, txctl.txq); 2443 ath_tx_fill_desc(sc, bf, txctl.txq, 0); 2444 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false); 2445 TX_STAT_INC(txctl.txq->axq_qnum, queued); 2446 ath_txq_unlock(sc, txctl.txq); 2447} 2448 2449/*****************/ 2450/* TX Completion */ 2451/*****************/ 2452 2453static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 2454 int tx_flags, struct ath_txq *txq) 2455{ 2456 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2457 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2458 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 2459 int padpos, padsize; 2460 unsigned long flags; 2461 2462 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); 2463 2464 if (sc->sc_ah->caldata) 2465 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags); 2466 2467 if (!(tx_flags & ATH_TX_ERROR)) { 2468 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 2469 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 2470 else 2471 tx_info->flags |= IEEE80211_TX_STAT_ACK; 2472 } 2473 2474 padpos = ieee80211_hdrlen(hdr->frame_control); 2475 padsize = padpos & 3; 2476 if (padsize && skb->len>padpos+padsize) { 2477 /* 2478 * Remove MAC header padding before giving the frame back to 2479 * mac80211. 2480 */ 2481 memmove(skb->data + padsize, skb->data, padpos); 2482 skb_pull(skb, padsize); 2483 } 2484 2485 spin_lock_irqsave(&sc->sc_pm_lock, flags); 2486 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { 2487 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; 2488 ath_dbg(common, PS, 2489 "Going back to sleep after having received TX status (0x%lx)\n", 2490 sc->ps_flags & (PS_WAIT_FOR_BEACON | 2491 PS_WAIT_FOR_CAB | 2492 PS_WAIT_FOR_PSPOLL_DATA | 2493 PS_WAIT_FOR_TX_ACK)); 2494 } 2495 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 2496 2497 __skb_queue_tail(&txq->complete_q, skb); 2498 ath_txq_skb_done(sc, txq, skb); 2499} 2500 2501static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 2502 struct ath_txq *txq, struct list_head *bf_q, 2503 struct ath_tx_status *ts, int txok) 2504{ 2505 struct sk_buff *skb = bf->bf_mpdu; 2506 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2507 unsigned long flags; 2508 int tx_flags = 0; 2509 2510 if (!txok) 2511 tx_flags |= ATH_TX_ERROR; 2512 2513 if (ts->ts_status & ATH9K_TXERR_FILT) 2514 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 2515 2516 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); 2517 bf->bf_buf_addr = 0; 2518 if (sc->tx99_state) 2519 goto skip_tx_complete; 2520 2521 if (bf->bf_state.bfs_paprd) { 2522 if (time_after(jiffies, 2523 bf->bf_state.bfs_paprd_timestamp + 2524 msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) 2525 dev_kfree_skb_any(skb); 2526 else 2527 complete(&sc->paprd_complete); 2528 } else { 2529 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); 2530 ath_tx_complete(sc, skb, tx_flags, txq); 2531 } 2532skip_tx_complete: 2533 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't 2534 * accidentally reference it later. 2535 */ 2536 bf->bf_mpdu = NULL; 2537 2538 /* 2539 * Return the list of ath_buf of this mpdu to free queue 2540 */ 2541 spin_lock_irqsave(&sc->tx.txbuflock, flags); 2542 list_splice_tail_init(bf_q, &sc->tx.txbuf); 2543 spin_unlock_irqrestore(&sc->tx.txbuflock, flags); 2544} 2545 2546static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 2547 struct ath_tx_status *ts, int nframes, int nbad, 2548 int txok) 2549{ 2550 struct sk_buff *skb = bf->bf_mpdu; 2551 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2552 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2553 struct ieee80211_hw *hw = sc->hw; 2554 struct ath_hw *ah = sc->sc_ah; 2555 u8 i, tx_rateindex; 2556 2557 if (txok) 2558 tx_info->status.ack_signal = ts->ts_rssi; 2559 2560 tx_rateindex = ts->ts_rateindex; 2561 WARN_ON(tx_rateindex >= hw->max_rates); 2562 2563 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 2564 tx_info->flags |= IEEE80211_TX_STAT_AMPDU; 2565 2566 BUG_ON(nbad > nframes); 2567 } 2568 tx_info->status.ampdu_len = nframes; 2569 tx_info->status.ampdu_ack_len = nframes - nbad; 2570 2571 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && 2572 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { 2573 /* 2574 * If an underrun error is seen assume it as an excessive 2575 * retry only if max frame trigger level has been reached 2576 * (2 KB for single stream, and 4 KB for dual stream). 2577 * Adjust the long retry as if the frame was tried 2578 * hw->max_rate_tries times to affect how rate control updates 2579 * PER for the failed rate. 2580 * In case of congestion on the bus penalizing this type of 2581 * underruns should help hardware actually transmit new frames 2582 * successfully by eventually preferring slower rates. 2583 * This itself should also alleviate congestion on the bus. 2584 */ 2585 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | 2586 ATH9K_TX_DELIM_UNDERRUN)) && 2587 ieee80211_is_data(hdr->frame_control) && 2588 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) 2589 tx_info->status.rates[tx_rateindex].count = 2590 hw->max_rate_tries; 2591 } 2592 2593 for (i = tx_rateindex + 1; i < hw->max_rates; i++) { 2594 tx_info->status.rates[i].count = 0; 2595 tx_info->status.rates[i].idx = -1; 2596 } 2597 2598 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; 2599} 2600 2601static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 2602{ 2603 struct ath_hw *ah = sc->sc_ah; 2604 struct ath_common *common = ath9k_hw_common(ah); 2605 struct ath_buf *bf, *lastbf, *bf_held = NULL; 2606 struct list_head bf_head; 2607 struct ath_desc *ds; 2608 struct ath_tx_status ts; 2609 int status; 2610 2611 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", 2612 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 2613 txq->axq_link); 2614 2615 ath_txq_lock(sc, txq); 2616 for (;;) { 2617 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2618 break; 2619 2620 if (list_empty(&txq->axq_q)) { 2621 txq->axq_link = NULL; 2622 ath_txq_schedule(sc, txq); 2623 break; 2624 } 2625 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 2626 2627 /* 2628 * There is a race condition that a BH gets scheduled 2629 * after sw writes TxE and before hw re-load the last 2630 * descriptor to get the newly chained one. 2631 * Software must keep the last DONE descriptor as a 2632 * holding descriptor - software does so by marking 2633 * it with the STALE flag. 2634 */ 2635 bf_held = NULL; 2636 if (bf->bf_state.stale) { 2637 bf_held = bf; 2638 if (list_is_last(&bf_held->list, &txq->axq_q)) 2639 break; 2640 2641 bf = list_entry(bf_held->list.next, struct ath_buf, 2642 list); 2643 } 2644 2645 lastbf = bf->bf_lastbf; 2646 ds = lastbf->bf_desc; 2647 2648 memset(&ts, 0, sizeof(ts)); 2649 status = ath9k_hw_txprocdesc(ah, ds, &ts); 2650 if (status == -EINPROGRESS) 2651 break; 2652 2653 TX_STAT_INC(txq->axq_qnum, txprocdesc); 2654 2655 /* 2656 * Remove ath_buf's of the same transmit unit from txq, 2657 * however leave the last descriptor back as the holding 2658 * descriptor for hw. 2659 */ 2660 lastbf->bf_state.stale = true; 2661 INIT_LIST_HEAD(&bf_head); 2662 if (!list_is_singular(&lastbf->list)) 2663 list_cut_position(&bf_head, 2664 &txq->axq_q, lastbf->list.prev); 2665 2666 if (bf_held) { 2667 list_del(&bf_held->list); 2668 ath_tx_return_buffer(sc, bf_held); 2669 } 2670 2671 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2672 } 2673 ath_txq_unlock_complete(sc, txq); 2674} 2675 2676void ath_tx_tasklet(struct ath_softc *sc) 2677{ 2678 struct ath_hw *ah = sc->sc_ah; 2679 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs; 2680 int i; 2681 2682 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2683 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) 2684 ath_tx_processq(sc, &sc->tx.txq[i]); 2685 } 2686} 2687 2688void ath_tx_edma_tasklet(struct ath_softc *sc) 2689{ 2690 struct ath_tx_status ts; 2691 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2692 struct ath_hw *ah = sc->sc_ah; 2693 struct ath_txq *txq; 2694 struct ath_buf *bf, *lastbf; 2695 struct list_head bf_head; 2696 struct list_head *fifo_list; 2697 int status; 2698 2699 for (;;) { 2700 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2701 break; 2702 2703 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); 2704 if (status == -EINPROGRESS) 2705 break; 2706 if (status == -EIO) { 2707 ath_dbg(common, XMIT, "Error processing tx status\n"); 2708 break; 2709 } 2710 2711 /* Process beacon completions separately */ 2712 if (ts.qid == sc->beacon.beaconq) { 2713 sc->beacon.tx_processed = true; 2714 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2715 2716 if (ath9k_is_chanctx_enabled()) { 2717 ath_chanctx_event(sc, NULL, 2718 ATH_CHANCTX_EVENT_BEACON_SENT); 2719 } 2720 2721 ath9k_csa_update(sc); 2722 continue; 2723 } 2724 2725 txq = &sc->tx.txq[ts.qid]; 2726 2727 ath_txq_lock(sc, txq); 2728 2729 TX_STAT_INC(txq->axq_qnum, txprocdesc); 2730 2731 fifo_list = &txq->txq_fifo[txq->txq_tailidx]; 2732 if (list_empty(fifo_list)) { 2733 ath_txq_unlock(sc, txq); 2734 return; 2735 } 2736 2737 bf = list_first_entry(fifo_list, struct ath_buf, list); 2738 if (bf->bf_state.stale) { 2739 list_del(&bf->list); 2740 ath_tx_return_buffer(sc, bf); 2741 bf = list_first_entry(fifo_list, struct ath_buf, list); 2742 } 2743 2744 lastbf = bf->bf_lastbf; 2745 2746 INIT_LIST_HEAD(&bf_head); 2747 if (list_is_last(&lastbf->list, fifo_list)) { 2748 list_splice_tail_init(fifo_list, &bf_head); 2749 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); 2750 2751 if (!list_empty(&txq->axq_q)) { 2752 struct list_head bf_q; 2753 2754 INIT_LIST_HEAD(&bf_q); 2755 txq->axq_link = NULL; 2756 list_splice_tail_init(&txq->axq_q, &bf_q); 2757 ath_tx_txqaddbuf(sc, txq, &bf_q, true); 2758 } 2759 } else { 2760 lastbf->bf_state.stale = true; 2761 if (bf != lastbf) 2762 list_cut_position(&bf_head, fifo_list, 2763 lastbf->list.prev); 2764 } 2765 2766 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2767 ath_txq_unlock_complete(sc, txq); 2768 } 2769} 2770 2771/*****************/ 2772/* Init, Cleanup */ 2773/*****************/ 2774 2775static int ath_txstatus_setup(struct ath_softc *sc, int size) 2776{ 2777 struct ath_descdma *dd = &sc->txsdma; 2778 u8 txs_len = sc->sc_ah->caps.txs_len; 2779 2780 dd->dd_desc_len = size * txs_len; 2781 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 2782 &dd->dd_desc_paddr, GFP_KERNEL); 2783 if (!dd->dd_desc) 2784 return -ENOMEM; 2785 2786 return 0; 2787} 2788 2789static int ath_tx_edma_init(struct ath_softc *sc) 2790{ 2791 int err; 2792 2793 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); 2794 if (!err) 2795 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, 2796 sc->txsdma.dd_desc_paddr, 2797 ATH_TXSTATUS_RING_SIZE); 2798 2799 return err; 2800} 2801 2802int ath_tx_init(struct ath_softc *sc, int nbufs) 2803{ 2804 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2805 int error = 0; 2806 2807 spin_lock_init(&sc->tx.txbuflock); 2808 2809 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2810 "tx", nbufs, 1, 1); 2811 if (error != 0) { 2812 ath_err(common, 2813 "Failed to allocate tx descriptors: %d\n", error); 2814 return error; 2815 } 2816 2817 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2818 "beacon", ATH_BCBUF, 1, 1); 2819 if (error != 0) { 2820 ath_err(common, 2821 "Failed to allocate beacon descriptors: %d\n", error); 2822 return error; 2823 } 2824 2825 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); 2826 2827 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 2828 error = ath_tx_edma_init(sc); 2829 2830 return error; 2831} 2832 2833void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) 2834{ 2835 struct ath_atx_tid *tid; 2836 int tidno, acno; 2837 2838 for (tidno = 0, tid = &an->tid[tidno]; 2839 tidno < IEEE80211_NUM_TIDS; 2840 tidno++, tid++) { 2841 tid->an = an; 2842 tid->tidno = tidno; 2843 tid->seq_start = tid->seq_next = 0; 2844 tid->baw_size = WME_MAX_BA; 2845 tid->baw_head = tid->baw_tail = 0; 2846 tid->active = false; 2847 tid->clear_ps_filter = true; 2848 __skb_queue_head_init(&tid->buf_q); 2849 __skb_queue_head_init(&tid->retry_q); 2850 INIT_LIST_HEAD(&tid->list); 2851 acno = TID_TO_WME_AC(tidno); 2852 tid->txq = sc->tx.txq_map[acno]; 2853 } 2854} 2855 2856void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) 2857{ 2858 struct ath_atx_tid *tid; 2859 struct ath_txq *txq; 2860 int tidno; 2861 2862 for (tidno = 0, tid = &an->tid[tidno]; 2863 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { 2864 2865 txq = tid->txq; 2866 2867 ath_txq_lock(sc, txq); 2868 2869 if (!list_empty(&tid->list)) 2870 list_del_init(&tid->list); 2871 2872 ath_tid_drain(sc, txq, tid); 2873 tid->active = false; 2874 2875 ath_txq_unlock(sc, txq); 2876 } 2877} 2878 2879#ifdef CONFIG_ATH9K_TX99 2880 2881int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, 2882 struct ath_tx_control *txctl) 2883{ 2884 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2885 struct ath_frame_info *fi = get_frame_info(skb); 2886 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2887 struct ath_buf *bf; 2888 int padpos, padsize; 2889 2890 padpos = ieee80211_hdrlen(hdr->frame_control); 2891 padsize = padpos & 3; 2892 2893 if (padsize && skb->len > padpos) { 2894 if (skb_headroom(skb) < padsize) { 2895 ath_dbg(common, XMIT, 2896 "tx99 padding failed\n"); 2897 return -EINVAL; 2898 } 2899 2900 skb_push(skb, padsize); 2901 memmove(skb->data, skb->data + padsize, padpos); 2902 } 2903 2904 fi->keyix = ATH9K_TXKEYIX_INVALID; 2905 fi->framelen = skb->len + FCS_LEN; 2906 fi->keytype = ATH9K_KEY_TYPE_CLEAR; 2907 2908 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb); 2909 if (!bf) { 2910 ath_dbg(common, XMIT, "tx99 buffer setup failed\n"); 2911 return -EINVAL; 2912 } 2913 2914 ath_set_rates(sc->tx99_vif, NULL, bf); 2915 2916 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr); 2917 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum); 2918 2919 ath_tx_send_normal(sc, txctl->txq, NULL, skb); 2920 2921 return 0; 2922} 2923 2924#endif /* CONFIG_ATH9K_TX99 */ 2925