1/*
2 * Copyright (c) 2014-2015 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/types.h>
18#include "core.h"
19#include "hw.h"
20
21const struct ath10k_hw_regs qca988x_regs = {
22	.rtc_state_cold_reset_mask	= 0x00000400,
23	.rtc_soc_base_address		= 0x00004000,
24	.rtc_wmac_base_address		= 0x00005000,
25	.soc_core_base_address		= 0x00009000,
26	.ce_wrapper_base_address	= 0x00057000,
27	.ce0_base_address		= 0x00057400,
28	.ce1_base_address		= 0x00057800,
29	.ce2_base_address		= 0x00057c00,
30	.ce3_base_address		= 0x00058000,
31	.ce4_base_address		= 0x00058400,
32	.ce5_base_address		= 0x00058800,
33	.ce6_base_address		= 0x00058c00,
34	.ce7_base_address		= 0x00059000,
35	.soc_reset_control_si0_rst_mask	= 0x00000001,
36	.soc_reset_control_ce_rst_mask	= 0x00040000,
37	.soc_chip_id_address		= 0x000000ec,
38	.scratch_3_address		= 0x00000030,
39	.fw_indicator_address		= 0x00009030,
40	.pcie_local_base_address	= 0x00080000,
41	.ce_wrap_intr_sum_host_msi_lsb	= 0x00000008,
42	.ce_wrap_intr_sum_host_msi_mask	= 0x0000ff00,
43	.pcie_intr_fw_mask		= 0x00000400,
44	.pcie_intr_ce_mask_all		= 0x0007f800,
45	.pcie_intr_clr_address		= 0x00000014,
46};
47
48const struct ath10k_hw_regs qca6174_regs = {
49	.rtc_state_cold_reset_mask		= 0x00002000,
50	.rtc_soc_base_address			= 0x00000800,
51	.rtc_wmac_base_address			= 0x00001000,
52	.soc_core_base_address			= 0x0003a000,
53	.ce_wrapper_base_address		= 0x00034000,
54	.ce0_base_address			= 0x00034400,
55	.ce1_base_address			= 0x00034800,
56	.ce2_base_address			= 0x00034c00,
57	.ce3_base_address			= 0x00035000,
58	.ce4_base_address			= 0x00035400,
59	.ce5_base_address			= 0x00035800,
60	.ce6_base_address			= 0x00035c00,
61	.ce7_base_address			= 0x00036000,
62	.soc_reset_control_si0_rst_mask		= 0x00000000,
63	.soc_reset_control_ce_rst_mask		= 0x00000001,
64	.soc_chip_id_address			= 0x000000f0,
65	.scratch_3_address			= 0x00000028,
66	.fw_indicator_address			= 0x0003a028,
67	.pcie_local_base_address		= 0x00080000,
68	.ce_wrap_intr_sum_host_msi_lsb		= 0x00000008,
69	.ce_wrap_intr_sum_host_msi_mask		= 0x0000ff00,
70	.pcie_intr_fw_mask			= 0x00000400,
71	.pcie_intr_ce_mask_all			= 0x0007f800,
72	.pcie_intr_clr_address			= 0x00000014,
73};
74
75const struct ath10k_hw_regs qca99x0_regs = {
76	.rtc_state_cold_reset_mask		= 0x00000400,
77	.rtc_soc_base_address			= 0x00080000,
78	.rtc_wmac_base_address			= 0x00000000,
79	.soc_core_base_address			= 0x00082000,
80	.ce_wrapper_base_address		= 0x0004d000,
81	.ce0_base_address			= 0x0004a000,
82	.ce1_base_address			= 0x0004a400,
83	.ce2_base_address			= 0x0004a800,
84	.ce3_base_address			= 0x0004ac00,
85	.ce4_base_address			= 0x0004b000,
86	.ce5_base_address			= 0x0004b400,
87	.ce6_base_address			= 0x0004b800,
88	.ce7_base_address			= 0x0004bc00,
89	/* Note: qca99x0 supports upto 12 Copy Engines. Other than address of
90	 * CE0 and CE1 no other copy engine is directly referred in the code.
91	 * It is not really neccessary to assign address for newly supported
92	 * CEs in this address table.
93	 *	Copy Engine		Address
94	 *	CE8			0x0004c000
95	 *	CE9			0x0004c400
96	 *	CE10			0x0004c800
97	 *	CE11			0x0004cc00
98	 */
99	.soc_reset_control_si0_rst_mask		= 0x00000001,
100	.soc_reset_control_ce_rst_mask		= 0x00000100,
101	.soc_chip_id_address			= 0x000000ec,
102	.scratch_3_address			= 0x00040050,
103	.fw_indicator_address			= 0x00040050,
104	.pcie_local_base_address		= 0x00000000,
105	.ce_wrap_intr_sum_host_msi_lsb		= 0x0000000c,
106	.ce_wrap_intr_sum_host_msi_mask		= 0x00fff000,
107	.pcie_intr_fw_mask			= 0x00100000,
108	.pcie_intr_ce_mask_all			= 0x000fff00,
109	.pcie_intr_clr_address			= 0x00000010,
110};
111
112const struct ath10k_hw_values qca988x_values = {
113	.rtc_state_val_on		= 3,
114	.ce_count			= 8,
115	.msi_assign_ce_max		= 7,
116	.num_target_ce_config_wlan	= 7,
117	.ce_desc_meta_data_mask		= 0xFFFC,
118	.ce_desc_meta_data_lsb		= 2,
119};
120
121const struct ath10k_hw_values qca6174_values = {
122	.rtc_state_val_on		= 3,
123	.ce_count			= 8,
124	.msi_assign_ce_max		= 7,
125	.num_target_ce_config_wlan	= 7,
126	.ce_desc_meta_data_mask		= 0xFFFC,
127	.ce_desc_meta_data_lsb		= 2,
128};
129
130const struct ath10k_hw_values qca99x0_values = {
131	.rtc_state_val_on		= 5,
132	.ce_count			= 12,
133	.msi_assign_ce_max		= 12,
134	.num_target_ce_config_wlan	= 10,
135	.ce_desc_meta_data_mask		= 0xFFF0,
136	.ce_desc_meta_data_lsb		= 4,
137};
138
139void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
140				u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
141{
142	u32 cc_fix = 0;
143
144	survey->filled |= SURVEY_INFO_TIME |
145			  SURVEY_INFO_TIME_BUSY;
146
147	if (ar->hw_params.has_shifted_cc_wraparound && cc < cc_prev) {
148		cc_fix = 0x7fffffff;
149		survey->filled &= ~SURVEY_INFO_TIME_BUSY;
150	}
151
152	cc -= cc_prev - cc_fix;
153	rcc -= rcc_prev;
154
155	survey->time = CCNT_TO_MSEC(ar, cc);
156	survey->time_busy = CCNT_TO_MSEC(ar, rcc);
157}
158