1/* 2 * linux/drivers/net/irda/pxaficp_ir.c 3 * 4 * Based on sa1100_ir.c by Russell King 5 * 6 * Changes copyright (C) 2003-2005 MontaVista Software, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Infra-red driver (SIR/FIR) for the PXA2xx embedded microprocessor 13 * 14 */ 15#include <linux/dma-mapping.h> 16#include <linux/interrupt.h> 17#include <linux/module.h> 18#include <linux/netdevice.h> 19#include <linux/etherdevice.h> 20#include <linux/platform_device.h> 21#include <linux/clk.h> 22#include <linux/dmaengine.h> 23#include <linux/dma-mapping.h> 24#include <linux/dma/pxa-dma.h> 25#include <linux/gpio.h> 26#include <linux/slab.h> 27 28#include <net/irda/irda.h> 29#include <net/irda/irmod.h> 30#include <net/irda/wrapper.h> 31#include <net/irda/irda_device.h> 32 33#include <linux/platform_data/irda-pxaficp.h> 34#undef __REG 35#define __REG(x) ((x) & 0xffff) 36#include <mach/regs-uart.h> 37 38#define ICCR0 0x0000 /* ICP Control Register 0 */ 39#define ICCR1 0x0004 /* ICP Control Register 1 */ 40#define ICCR2 0x0008 /* ICP Control Register 2 */ 41#define ICDR 0x000c /* ICP Data Register */ 42#define ICSR0 0x0014 /* ICP Status Register 0 */ 43#define ICSR1 0x0018 /* ICP Status Register 1 */ 44 45#define ICCR0_AME (1 << 7) /* Address match enable */ 46#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ 47#define ICCR0_RIE (1 << 5) /* Receive FIFO interrupt enable */ 48#define ICCR0_RXE (1 << 4) /* Receive enable */ 49#define ICCR0_TXE (1 << 3) /* Transmit enable */ 50#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ 51#define ICCR0_LBM (1 << 1) /* Loopback mode */ 52#define ICCR0_ITR (1 << 0) /* IrDA transmission */ 53 54#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ 55#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ 56#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ 57#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ 58#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ 59#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ 60 61#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ 62#define ICSR0_FRE (1 << 5) /* Framing error */ 63#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ 64#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ 65#define ICSR0_RAB (1 << 2) /* Receiver abort */ 66#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ 67#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ 68 69#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ 70#define ICSR1_CRE (1 << 5) /* CRC error */ 71#define ICSR1_EOF (1 << 4) /* End of frame */ 72#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ 73#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ 74#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ 75#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ 76 77#define IrSR_RXPL_NEG_IS_ZERO (1<<4) 78#define IrSR_RXPL_POS_IS_ZERO 0x0 79#define IrSR_TXPL_NEG_IS_ZERO (1<<3) 80#define IrSR_TXPL_POS_IS_ZERO 0x0 81#define IrSR_XMODE_PULSE_1_6 (1<<2) 82#define IrSR_XMODE_PULSE_3_16 0x0 83#define IrSR_RCVEIR_IR_MODE (1<<1) 84#define IrSR_RCVEIR_UART_MODE 0x0 85#define IrSR_XMITIR_IR_MODE (1<<0) 86#define IrSR_XMITIR_UART_MODE 0x0 87 88#define IrSR_IR_RECEIVE_ON (\ 89 IrSR_RXPL_NEG_IS_ZERO | \ 90 IrSR_TXPL_POS_IS_ZERO | \ 91 IrSR_XMODE_PULSE_3_16 | \ 92 IrSR_RCVEIR_IR_MODE | \ 93 IrSR_XMITIR_UART_MODE) 94 95#define IrSR_IR_TRANSMIT_ON (\ 96 IrSR_RXPL_NEG_IS_ZERO | \ 97 IrSR_TXPL_POS_IS_ZERO | \ 98 IrSR_XMODE_PULSE_3_16 | \ 99 IrSR_RCVEIR_UART_MODE | \ 100 IrSR_XMITIR_IR_MODE) 101 102/* macros for registers read/write */ 103#define ficp_writel(irda, val, off) \ 104 do { \ 105 dev_vdbg(irda->dev, \ 106 "%s():%d ficp_writel(0x%x, %s)\n", \ 107 __func__, __LINE__, (val), #off); \ 108 writel_relaxed((val), (irda)->irda_base + (off)); \ 109 } while (0) 110 111#define ficp_readl(irda, off) \ 112 ({ \ 113 unsigned int _v; \ 114 _v = readl_relaxed((irda)->irda_base + (off)); \ 115 dev_vdbg(irda->dev, \ 116 "%s():%d ficp_readl(%s): 0x%x\n", \ 117 __func__, __LINE__, #off, _v); \ 118 _v; \ 119 }) 120 121#define stuart_writel(irda, val, off) \ 122 do { \ 123 dev_vdbg(irda->dev, \ 124 "%s():%d stuart_writel(0x%x, %s)\n", \ 125 __func__, __LINE__, (val), #off); \ 126 writel_relaxed((val), (irda)->stuart_base + (off)); \ 127 } while (0) 128 129#define stuart_readl(irda, off) \ 130 ({ \ 131 unsigned int _v; \ 132 _v = readl_relaxed((irda)->stuart_base + (off)); \ 133 dev_vdbg(irda->dev, \ 134 "%s():%d stuart_readl(%s): 0x%x\n", \ 135 __func__, __LINE__, #off, _v); \ 136 _v; \ 137 }) 138 139struct pxa_irda { 140 int speed; 141 int newspeed; 142 unsigned long long last_clk; 143 144 void __iomem *stuart_base; 145 void __iomem *irda_base; 146 unsigned char *dma_rx_buff; 147 unsigned char *dma_tx_buff; 148 dma_addr_t dma_rx_buff_phy; 149 dma_addr_t dma_tx_buff_phy; 150 unsigned int dma_tx_buff_len; 151 struct dma_chan *txdma; 152 struct dma_chan *rxdma; 153 dma_cookie_t rx_cookie; 154 dma_cookie_t tx_cookie; 155 int drcmr_rx; 156 int drcmr_tx; 157 158 int uart_irq; 159 int icp_irq; 160 161 struct irlap_cb *irlap; 162 struct qos_info qos; 163 164 iobuff_t tx_buff; 165 iobuff_t rx_buff; 166 167 struct device *dev; 168 struct pxaficp_platform_data *pdata; 169 struct clk *fir_clk; 170 struct clk *sir_clk; 171 struct clk *cur_clk; 172}; 173 174static int pxa_irda_set_speed(struct pxa_irda *si, int speed); 175 176static inline void pxa_irda_disable_clk(struct pxa_irda *si) 177{ 178 if (si->cur_clk) 179 clk_disable_unprepare(si->cur_clk); 180 si->cur_clk = NULL; 181} 182 183static inline void pxa_irda_enable_firclk(struct pxa_irda *si) 184{ 185 si->cur_clk = si->fir_clk; 186 clk_prepare_enable(si->fir_clk); 187} 188 189static inline void pxa_irda_enable_sirclk(struct pxa_irda *si) 190{ 191 si->cur_clk = si->sir_clk; 192 clk_prepare_enable(si->sir_clk); 193} 194 195 196#define IS_FIR(si) ((si)->speed >= 4000000) 197#define IRDA_FRAME_SIZE_LIMIT 2047 198 199static void pxa_irda_fir_dma_rx_irq(void *data); 200static void pxa_irda_fir_dma_tx_irq(void *data); 201 202inline static void pxa_irda_fir_dma_rx_start(struct pxa_irda *si) 203{ 204 struct dma_async_tx_descriptor *tx; 205 206 tx = dmaengine_prep_slave_single(si->rxdma, si->dma_rx_buff_phy, 207 IRDA_FRAME_SIZE_LIMIT, DMA_FROM_DEVICE, 208 DMA_PREP_INTERRUPT); 209 if (!tx) { 210 dev_err(si->dev, "prep_slave_sg() failed\n"); 211 return; 212 } 213 tx->callback = pxa_irda_fir_dma_rx_irq; 214 tx->callback_param = si; 215 si->rx_cookie = dmaengine_submit(tx); 216 dma_async_issue_pending(si->rxdma); 217} 218 219inline static void pxa_irda_fir_dma_tx_start(struct pxa_irda *si) 220{ 221 struct dma_async_tx_descriptor *tx; 222 223 tx = dmaengine_prep_slave_single(si->txdma, si->dma_tx_buff_phy, 224 si->dma_tx_buff_len, DMA_TO_DEVICE, 225 DMA_PREP_INTERRUPT); 226 if (!tx) { 227 dev_err(si->dev, "prep_slave_sg() failed\n"); 228 return; 229 } 230 tx->callback = pxa_irda_fir_dma_tx_irq; 231 tx->callback_param = si; 232 si->tx_cookie = dmaengine_submit(tx); 233 dma_async_issue_pending(si->rxdma); 234} 235 236/* 237 * Set the IrDA communications mode. 238 */ 239static void pxa_irda_set_mode(struct pxa_irda *si, int mode) 240{ 241 if (si->pdata->transceiver_mode) 242 si->pdata->transceiver_mode(si->dev, mode); 243 else { 244 if (gpio_is_valid(si->pdata->gpio_pwdown)) 245 gpio_set_value(si->pdata->gpio_pwdown, 246 !(mode & IR_OFF) ^ 247 !si->pdata->gpio_pwdown_inverted); 248 pxa2xx_transceiver_mode(si->dev, mode); 249 } 250} 251 252/* 253 * Set the IrDA communications speed. 254 */ 255static int pxa_irda_set_speed(struct pxa_irda *si, int speed) 256{ 257 unsigned long flags; 258 unsigned int divisor; 259 260 switch (speed) { 261 case 9600: case 19200: case 38400: 262 case 57600: case 115200: 263 264 /* refer to PXA250/210 Developer's Manual 10-7 */ 265 /* BaudRate = 14.7456 MHz / (16*Divisor) */ 266 divisor = 14745600 / (16 * speed); 267 268 local_irq_save(flags); 269 270 if (IS_FIR(si)) { 271 /* stop RX DMA */ 272 dmaengine_terminate_all(si->rxdma); 273 /* disable FICP */ 274 ficp_writel(si, 0, ICCR0); 275 pxa_irda_disable_clk(si); 276 277 /* set board transceiver to SIR mode */ 278 pxa_irda_set_mode(si, IR_SIRMODE); 279 280 /* enable the STUART clock */ 281 pxa_irda_enable_sirclk(si); 282 } 283 284 /* disable STUART first */ 285 stuart_writel(si, 0, STIER); 286 287 /* access DLL & DLH */ 288 stuart_writel(si, stuart_readl(si, STLCR) | LCR_DLAB, STLCR); 289 stuart_writel(si, divisor & 0xff, STDLL); 290 stuart_writel(si, divisor >> 8, STDLH); 291 stuart_writel(si, stuart_readl(si, STLCR) & ~LCR_DLAB, STLCR); 292 293 si->speed = speed; 294 stuart_writel(si, IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6, 295 STISR); 296 stuart_writel(si, IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE, 297 STIER); 298 299 local_irq_restore(flags); 300 break; 301 302 case 4000000: 303 local_irq_save(flags); 304 305 /* disable STUART */ 306 stuart_writel(si, 0, STIER); 307 stuart_writel(si, 0, STISR); 308 pxa_irda_disable_clk(si); 309 310 /* disable FICP first */ 311 ficp_writel(si, 0, ICCR0); 312 313 /* set board transceiver to FIR mode */ 314 pxa_irda_set_mode(si, IR_FIRMODE); 315 316 /* enable the FICP clock */ 317 pxa_irda_enable_firclk(si); 318 319 si->speed = speed; 320 pxa_irda_fir_dma_rx_start(si); 321 ficp_writel(si, ICCR0_ITR | ICCR0_RXE, ICCR0); 322 323 local_irq_restore(flags); 324 break; 325 326 default: 327 return -EINVAL; 328 } 329 330 return 0; 331} 332 333/* SIR interrupt service routine. */ 334static irqreturn_t pxa_irda_sir_irq(int irq, void *dev_id) 335{ 336 struct net_device *dev = dev_id; 337 struct pxa_irda *si = netdev_priv(dev); 338 int iir, lsr, data; 339 340 iir = stuart_readl(si, STIIR); 341 342 switch (iir & 0x0F) { 343 case 0x06: /* Receiver Line Status */ 344 lsr = stuart_readl(si, STLSR); 345 while (lsr & LSR_FIFOE) { 346 data = stuart_readl(si, STRBR); 347 if (lsr & (LSR_OE | LSR_PE | LSR_FE | LSR_BI)) { 348 printk(KERN_DEBUG "pxa_ir: sir receiving error\n"); 349 dev->stats.rx_errors++; 350 if (lsr & LSR_FE) 351 dev->stats.rx_frame_errors++; 352 if (lsr & LSR_OE) 353 dev->stats.rx_fifo_errors++; 354 } else { 355 dev->stats.rx_bytes++; 356 async_unwrap_char(dev, &dev->stats, 357 &si->rx_buff, data); 358 } 359 lsr = stuart_readl(si, STLSR); 360 } 361 si->last_clk = sched_clock(); 362 break; 363 364 case 0x04: /* Received Data Available */ 365 /* forth through */ 366 367 case 0x0C: /* Character Timeout Indication */ 368 do { 369 dev->stats.rx_bytes++; 370 async_unwrap_char(dev, &dev->stats, &si->rx_buff, 371 stuart_readl(si, STRBR)); 372 } while (stuart_readl(si, STLSR) & LSR_DR); 373 si->last_clk = sched_clock(); 374 break; 375 376 case 0x02: /* Transmit FIFO Data Request */ 377 while ((si->tx_buff.len) && 378 (stuart_readl(si, STLSR) & LSR_TDRQ)) { 379 stuart_writel(si, *si->tx_buff.data++, STTHR); 380 si->tx_buff.len -= 1; 381 } 382 383 if (si->tx_buff.len == 0) { 384 dev->stats.tx_packets++; 385 dev->stats.tx_bytes += si->tx_buff.data - si->tx_buff.head; 386 387 /* We need to ensure that the transmitter has finished. */ 388 while ((stuart_readl(si, STLSR) & LSR_TEMT) == 0) 389 cpu_relax(); 390 si->last_clk = sched_clock(); 391 392 /* 393 * Ok, we've finished transmitting. Now enable 394 * the receiver. Sometimes we get a receive IRQ 395 * immediately after a transmit... 396 */ 397 if (si->newspeed) { 398 pxa_irda_set_speed(si, si->newspeed); 399 si->newspeed = 0; 400 } else { 401 /* enable IR Receiver, disable IR Transmitter */ 402 stuart_writel(si, IrSR_IR_RECEIVE_ON | 403 IrSR_XMODE_PULSE_1_6, STISR); 404 /* enable STUART and receive interrupts */ 405 stuart_writel(si, IER_UUE | IER_RLSE | 406 IER_RAVIE | IER_RTIOE, STIER); 407 } 408 /* I'm hungry! */ 409 netif_wake_queue(dev); 410 } 411 break; 412 } 413 414 return IRQ_HANDLED; 415} 416 417/* FIR Receive DMA interrupt handler */ 418static void pxa_irda_fir_dma_rx_irq(void *data) 419{ 420 struct net_device *dev = data; 421 struct pxa_irda *si = netdev_priv(dev); 422 423 dmaengine_terminate_all(si->rxdma); 424 netdev_dbg(dev, "pxa_ir: fir rx dma bus error\n"); 425} 426 427/* FIR Transmit DMA interrupt handler */ 428static void pxa_irda_fir_dma_tx_irq(void *data) 429{ 430 struct net_device *dev = data; 431 struct pxa_irda *si = netdev_priv(dev); 432 433 dmaengine_terminate_all(si->txdma); 434 if (dmaengine_tx_status(si->txdma, si->tx_cookie, NULL) == DMA_ERROR) { 435 dev->stats.tx_errors++; 436 } else { 437 dev->stats.tx_packets++; 438 dev->stats.tx_bytes += si->dma_tx_buff_len; 439 } 440 441 while (ficp_readl(si, ICSR1) & ICSR1_TBY) 442 cpu_relax(); 443 si->last_clk = sched_clock(); 444 445 /* 446 * HACK: It looks like the TBY bit is dropped too soon. 447 * Without this delay things break. 448 */ 449 udelay(120); 450 451 if (si->newspeed) { 452 pxa_irda_set_speed(si, si->newspeed); 453 si->newspeed = 0; 454 } else { 455 int i = 64; 456 457 ficp_writel(si, 0, ICCR0); 458 pxa_irda_fir_dma_rx_start(si); 459 while ((ficp_readl(si, ICSR1) & ICSR1_RNE) && i--) 460 ficp_readl(si, ICDR); 461 ficp_writel(si, ICCR0_ITR | ICCR0_RXE, ICCR0); 462 463 if (i < 0) 464 printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n"); 465 } 466 netif_wake_queue(dev); 467} 468 469/* EIF(Error in FIFO/End in Frame) handler for FIR */ 470static void pxa_irda_fir_irq_eif(struct pxa_irda *si, struct net_device *dev, int icsr0) 471{ 472 unsigned int len, stat, data; 473 struct dma_tx_state state; 474 475 /* Get the current data position. */ 476 477 dmaengine_tx_status(si->rxdma, si->rx_cookie, &state); 478 len = IRDA_FRAME_SIZE_LIMIT - state.residue; 479 480 do { 481 /* Read Status, and then Data. */ 482 stat = ficp_readl(si, ICSR1); 483 rmb(); 484 data = ficp_readl(si, ICDR); 485 486 if (stat & (ICSR1_CRE | ICSR1_ROR)) { 487 dev->stats.rx_errors++; 488 if (stat & ICSR1_CRE) { 489 printk(KERN_DEBUG "pxa_ir: fir receive CRC error\n"); 490 dev->stats.rx_crc_errors++; 491 } 492 if (stat & ICSR1_ROR) { 493 printk(KERN_DEBUG "pxa_ir: fir receive overrun\n"); 494 dev->stats.rx_over_errors++; 495 } 496 } else { 497 si->dma_rx_buff[len++] = data; 498 } 499 /* If we hit the end of frame, there's no point in continuing. */ 500 if (stat & ICSR1_EOF) 501 break; 502 } while (ficp_readl(si, ICSR0) & ICSR0_EIF); 503 504 if (stat & ICSR1_EOF) { 505 /* end of frame. */ 506 struct sk_buff *skb; 507 508 if (icsr0 & ICSR0_FRE) { 509 printk(KERN_ERR "pxa_ir: dropping erroneous frame\n"); 510 dev->stats.rx_dropped++; 511 return; 512 } 513 514 skb = alloc_skb(len+1,GFP_ATOMIC); 515 if (!skb) { 516 printk(KERN_ERR "pxa_ir: fir out of memory for receive skb\n"); 517 dev->stats.rx_dropped++; 518 return; 519 } 520 521 /* Align IP header to 20 bytes */ 522 skb_reserve(skb, 1); 523 skb_copy_to_linear_data(skb, si->dma_rx_buff, len); 524 skb_put(skb, len); 525 526 /* Feed it to IrLAP */ 527 skb->dev = dev; 528 skb_reset_mac_header(skb); 529 skb->protocol = htons(ETH_P_IRDA); 530 netif_rx(skb); 531 532 dev->stats.rx_packets++; 533 dev->stats.rx_bytes += len; 534 } 535} 536 537/* FIR interrupt handler */ 538static irqreturn_t pxa_irda_fir_irq(int irq, void *dev_id) 539{ 540 struct net_device *dev = dev_id; 541 struct pxa_irda *si = netdev_priv(dev); 542 int icsr0, i = 64; 543 544 /* stop RX DMA */ 545 dmaengine_terminate_all(si->rxdma); 546 si->last_clk = sched_clock(); 547 icsr0 = ficp_readl(si, ICSR0); 548 549 if (icsr0 & (ICSR0_FRE | ICSR0_RAB)) { 550 if (icsr0 & ICSR0_FRE) { 551 printk(KERN_DEBUG "pxa_ir: fir receive frame error\n"); 552 dev->stats.rx_frame_errors++; 553 } else { 554 printk(KERN_DEBUG "pxa_ir: fir receive abort\n"); 555 dev->stats.rx_errors++; 556 } 557 ficp_writel(si, icsr0 & (ICSR0_FRE | ICSR0_RAB), ICSR0); 558 } 559 560 if (icsr0 & ICSR0_EIF) { 561 /* An error in FIFO occurred, or there is a end of frame */ 562 pxa_irda_fir_irq_eif(si, dev, icsr0); 563 } 564 565 ficp_writel(si, 0, ICCR0); 566 pxa_irda_fir_dma_rx_start(si); 567 while ((ficp_readl(si, ICSR1) & ICSR1_RNE) && i--) 568 ficp_readl(si, ICDR); 569 ficp_writel(si, ICCR0_ITR | ICCR0_RXE, ICCR0); 570 571 if (i < 0) 572 printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n"); 573 574 return IRQ_HANDLED; 575} 576 577/* hard_xmit interface of irda device */ 578static int pxa_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) 579{ 580 struct pxa_irda *si = netdev_priv(dev); 581 int speed = irda_get_next_speed(skb); 582 583 /* 584 * Does this packet contain a request to change the interface 585 * speed? If so, remember it until we complete the transmission 586 * of this frame. 587 */ 588 if (speed != si->speed && speed != -1) 589 si->newspeed = speed; 590 591 /* 592 * If this is an empty frame, we can bypass a lot. 593 */ 594 if (skb->len == 0) { 595 if (si->newspeed) { 596 si->newspeed = 0; 597 pxa_irda_set_speed(si, speed); 598 } 599 dev_kfree_skb(skb); 600 return NETDEV_TX_OK; 601 } 602 603 netif_stop_queue(dev); 604 605 if (!IS_FIR(si)) { 606 si->tx_buff.data = si->tx_buff.head; 607 si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data, si->tx_buff.truesize); 608 609 /* Disable STUART interrupts and switch to transmit mode. */ 610 stuart_writel(si, 0, STIER); 611 stuart_writel(si, IrSR_IR_TRANSMIT_ON | IrSR_XMODE_PULSE_1_6, 612 STISR); 613 614 /* enable STUART and transmit interrupts */ 615 stuart_writel(si, IER_UUE | IER_TIE, STIER); 616 } else { 617 unsigned long mtt = irda_get_mtt(skb); 618 619 si->dma_tx_buff_len = skb->len; 620 skb_copy_from_linear_data(skb, si->dma_tx_buff, skb->len); 621 622 if (mtt) 623 while ((sched_clock() - si->last_clk) * 1000 < mtt) 624 cpu_relax(); 625 626 /* stop RX DMA, disable FICP */ 627 dmaengine_terminate_all(si->rxdma); 628 ficp_writel(si, 0, ICCR0); 629 630 pxa_irda_fir_dma_tx_start(si); 631 ficp_writel(si, ICCR0_ITR | ICCR0_TXE, ICCR0); 632 } 633 634 dev_kfree_skb(skb); 635 return NETDEV_TX_OK; 636} 637 638static int pxa_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) 639{ 640 struct if_irda_req *rq = (struct if_irda_req *)ifreq; 641 struct pxa_irda *si = netdev_priv(dev); 642 int ret; 643 644 switch (cmd) { 645 case SIOCSBANDWIDTH: 646 ret = -EPERM; 647 if (capable(CAP_NET_ADMIN)) { 648 /* 649 * We are unable to set the speed if the 650 * device is not running. 651 */ 652 if (netif_running(dev)) { 653 ret = pxa_irda_set_speed(si, 654 rq->ifr_baudrate); 655 } else { 656 printk(KERN_INFO "pxa_ir: SIOCSBANDWIDTH: !netif_running\n"); 657 ret = 0; 658 } 659 } 660 break; 661 662 case SIOCSMEDIABUSY: 663 ret = -EPERM; 664 if (capable(CAP_NET_ADMIN)) { 665 irda_device_set_media_busy(dev, TRUE); 666 ret = 0; 667 } 668 break; 669 670 case SIOCGRECEIVING: 671 ret = 0; 672 rq->ifr_receiving = IS_FIR(si) ? 0 673 : si->rx_buff.state != OUTSIDE_FRAME; 674 break; 675 676 default: 677 ret = -EOPNOTSUPP; 678 break; 679 } 680 681 return ret; 682} 683 684static void pxa_irda_startup(struct pxa_irda *si) 685{ 686 /* Disable STUART interrupts */ 687 stuart_writel(si, 0, STIER); 688 /* enable STUART interrupt to the processor */ 689 stuart_writel(si, MCR_OUT2, STMCR); 690 /* configure SIR frame format: StartBit - Data 7 ... Data 0 - Stop Bit */ 691 stuart_writel(si, LCR_WLS0 | LCR_WLS1, STLCR); 692 /* enable FIFO, we use FIFO to improve performance */ 693 stuart_writel(si, FCR_TRFIFOE | FCR_ITL_32, STFCR); 694 695 /* disable FICP */ 696 ficp_writel(si, 0, ICCR0); 697 /* configure FICP ICCR2 */ 698 ficp_writel(si, ICCR2_TXP | ICCR2_TRIG_32, ICCR2); 699 700 /* force SIR reinitialization */ 701 si->speed = 4000000; 702 pxa_irda_set_speed(si, 9600); 703 704 printk(KERN_DEBUG "pxa_ir: irda startup\n"); 705} 706 707static void pxa_irda_shutdown(struct pxa_irda *si) 708{ 709 unsigned long flags; 710 711 local_irq_save(flags); 712 713 /* disable STUART and interrupt */ 714 stuart_writel(si, 0, STIER); 715 /* disable STUART SIR mode */ 716 stuart_writel(si, 0, STISR); 717 718 /* disable DMA */ 719 dmaengine_terminate_all(si->rxdma); 720 dmaengine_terminate_all(si->txdma); 721 /* disable FICP */ 722 ficp_writel(si, 0, ICCR0); 723 724 /* disable the STUART or FICP clocks */ 725 pxa_irda_disable_clk(si); 726 727 local_irq_restore(flags); 728 729 /* power off board transceiver */ 730 pxa_irda_set_mode(si, IR_OFF); 731 732 printk(KERN_DEBUG "pxa_ir: irda shutdown\n"); 733} 734 735static int pxa_irda_start(struct net_device *dev) 736{ 737 struct pxa_irda *si = netdev_priv(dev); 738 dma_cap_mask_t mask; 739 struct dma_slave_config config; 740 struct pxad_param param; 741 int err; 742 743 si->speed = 9600; 744 745 err = request_irq(si->uart_irq, pxa_irda_sir_irq, 0, dev->name, dev); 746 if (err) 747 goto err_irq1; 748 749 err = request_irq(si->icp_irq, pxa_irda_fir_irq, 0, dev->name, dev); 750 if (err) 751 goto err_irq2; 752 753 /* 754 * The interrupt must remain disabled for now. 755 */ 756 disable_irq(si->uart_irq); 757 disable_irq(si->icp_irq); 758 759 err = -EBUSY; 760 dma_cap_zero(mask); 761 dma_cap_set(DMA_SLAVE, mask); 762 param.prio = PXAD_PRIO_LOWEST; 763 764 memset(&config, 0, sizeof(config)); 765 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 766 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 767 config.src_addr = (dma_addr_t)si->irda_base + ICDR; 768 config.dst_addr = (dma_addr_t)si->irda_base + ICDR; 769 config.src_maxburst = 32; 770 config.dst_maxburst = 32; 771 772 param.drcmr = si->drcmr_rx; 773 si->rxdma = dma_request_slave_channel_compat(mask, pxad_filter_fn, 774 ¶m, &dev->dev, "rx"); 775 if (!si->rxdma) 776 goto err_rx_dma; 777 778 param.drcmr = si->drcmr_tx; 779 si->txdma = dma_request_slave_channel_compat(mask, pxad_filter_fn, 780 ¶m, &dev->dev, "tx"); 781 if (!si->txdma) 782 goto err_tx_dma; 783 784 err = dmaengine_slave_config(si->rxdma, &config); 785 if (err) 786 goto err_dma_rx_buff; 787 err = dmaengine_slave_config(si->txdma, &config); 788 if (err) 789 goto err_dma_rx_buff; 790 791 err = -ENOMEM; 792 si->dma_rx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, 793 &si->dma_rx_buff_phy, GFP_KERNEL); 794 if (!si->dma_rx_buff) 795 goto err_dma_rx_buff; 796 797 si->dma_tx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, 798 &si->dma_tx_buff_phy, GFP_KERNEL); 799 if (!si->dma_tx_buff) 800 goto err_dma_tx_buff; 801 802 /* Setup the serial port for the initial speed. */ 803 pxa_irda_startup(si); 804 805 /* 806 * Open a new IrLAP layer instance. 807 */ 808 si->irlap = irlap_open(dev, &si->qos, "pxa"); 809 err = -ENOMEM; 810 if (!si->irlap) 811 goto err_irlap; 812 813 /* 814 * Now enable the interrupt and start the queue 815 */ 816 enable_irq(si->uart_irq); 817 enable_irq(si->icp_irq); 818 netif_start_queue(dev); 819 820 printk(KERN_DEBUG "pxa_ir: irda driver opened\n"); 821 822 return 0; 823 824err_irlap: 825 pxa_irda_shutdown(si); 826 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy); 827err_dma_tx_buff: 828 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy); 829err_dma_rx_buff: 830 dma_release_channel(si->txdma); 831err_tx_dma: 832 dma_release_channel(si->rxdma); 833err_rx_dma: 834 free_irq(si->icp_irq, dev); 835err_irq2: 836 free_irq(si->uart_irq, dev); 837err_irq1: 838 839 return err; 840} 841 842static int pxa_irda_stop(struct net_device *dev) 843{ 844 struct pxa_irda *si = netdev_priv(dev); 845 846 netif_stop_queue(dev); 847 848 pxa_irda_shutdown(si); 849 850 /* Stop IrLAP */ 851 if (si->irlap) { 852 irlap_close(si->irlap); 853 si->irlap = NULL; 854 } 855 856 free_irq(si->uart_irq, dev); 857 free_irq(si->icp_irq, dev); 858 859 dmaengine_terminate_all(si->rxdma); 860 dmaengine_terminate_all(si->txdma); 861 dma_release_channel(si->rxdma); 862 dma_release_channel(si->txdma); 863 864 if (si->dma_rx_buff) 865 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy); 866 if (si->dma_tx_buff) 867 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy); 868 869 printk(KERN_DEBUG "pxa_ir: irda driver closed\n"); 870 return 0; 871} 872 873static int pxa_irda_suspend(struct platform_device *_dev, pm_message_t state) 874{ 875 struct net_device *dev = platform_get_drvdata(_dev); 876 struct pxa_irda *si; 877 878 if (dev && netif_running(dev)) { 879 si = netdev_priv(dev); 880 netif_device_detach(dev); 881 pxa_irda_shutdown(si); 882 } 883 884 return 0; 885} 886 887static int pxa_irda_resume(struct platform_device *_dev) 888{ 889 struct net_device *dev = platform_get_drvdata(_dev); 890 struct pxa_irda *si; 891 892 if (dev && netif_running(dev)) { 893 si = netdev_priv(dev); 894 pxa_irda_startup(si); 895 netif_device_attach(dev); 896 netif_wake_queue(dev); 897 } 898 899 return 0; 900} 901 902 903static int pxa_irda_init_iobuf(iobuff_t *io, int size) 904{ 905 io->head = kmalloc(size, GFP_KERNEL | GFP_DMA); 906 if (io->head != NULL) { 907 io->truesize = size; 908 io->in_frame = FALSE; 909 io->state = OUTSIDE_FRAME; 910 io->data = io->head; 911 } 912 return io->head ? 0 : -ENOMEM; 913} 914 915static const struct net_device_ops pxa_irda_netdev_ops = { 916 .ndo_open = pxa_irda_start, 917 .ndo_stop = pxa_irda_stop, 918 .ndo_start_xmit = pxa_irda_hard_xmit, 919 .ndo_do_ioctl = pxa_irda_ioctl, 920}; 921 922static int pxa_irda_probe(struct platform_device *pdev) 923{ 924 struct net_device *dev; 925 struct resource *res; 926 struct pxa_irda *si; 927 void __iomem *ficp, *stuart; 928 unsigned int baudrate_mask; 929 int err; 930 931 if (!pdev->dev.platform_data) 932 return -ENODEV; 933 934 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 935 ficp = devm_ioremap_resource(&pdev->dev, res); 936 if (IS_ERR(ficp)) { 937 dev_err(&pdev->dev, "resource ficp not defined\n"); 938 return PTR_ERR(ficp); 939 } 940 941 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 942 stuart = devm_ioremap_resource(&pdev->dev, res); 943 if (IS_ERR(stuart)) { 944 dev_err(&pdev->dev, "resource stuart not defined\n"); 945 return PTR_ERR(stuart); 946 } 947 948 dev = alloc_irdadev(sizeof(struct pxa_irda)); 949 if (!dev) { 950 err = -ENOMEM; 951 goto err_mem_1; 952 } 953 954 SET_NETDEV_DEV(dev, &pdev->dev); 955 si = netdev_priv(dev); 956 si->dev = &pdev->dev; 957 si->pdata = pdev->dev.platform_data; 958 959 si->irda_base = ficp; 960 si->stuart_base = stuart; 961 si->uart_irq = platform_get_irq(pdev, 0); 962 si->icp_irq = platform_get_irq(pdev, 1); 963 964 si->sir_clk = devm_clk_get(&pdev->dev, "UARTCLK"); 965 si->fir_clk = devm_clk_get(&pdev->dev, "FICPCLK"); 966 if (IS_ERR(si->sir_clk) || IS_ERR(si->fir_clk)) { 967 err = PTR_ERR(IS_ERR(si->sir_clk) ? si->sir_clk : si->fir_clk); 968 goto err_mem_4; 969 } 970 971 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 972 if (res) 973 si->drcmr_rx = res->start; 974 res = platform_get_resource(pdev, IORESOURCE_DMA, 1); 975 if (res) 976 si->drcmr_tx = res->start; 977 978 /* 979 * Initialise the SIR buffers 980 */ 981 err = pxa_irda_init_iobuf(&si->rx_buff, 14384); 982 if (err) 983 goto err_mem_4; 984 err = pxa_irda_init_iobuf(&si->tx_buff, 4000); 985 if (err) 986 goto err_mem_5; 987 988 if (gpio_is_valid(si->pdata->gpio_pwdown)) { 989 err = gpio_request(si->pdata->gpio_pwdown, "IrDA switch"); 990 if (err) 991 goto err_startup; 992 err = gpio_direction_output(si->pdata->gpio_pwdown, 993 !si->pdata->gpio_pwdown_inverted); 994 if (err) { 995 gpio_free(si->pdata->gpio_pwdown); 996 goto err_startup; 997 } 998 } 999 1000 if (si->pdata->startup) { 1001 err = si->pdata->startup(si->dev); 1002 if (err) 1003 goto err_startup; 1004 } 1005 1006 if (gpio_is_valid(si->pdata->gpio_pwdown) && si->pdata->startup) 1007 dev_warn(si->dev, "gpio_pwdown and startup() both defined!\n"); 1008 1009 dev->netdev_ops = &pxa_irda_netdev_ops; 1010 1011 irda_init_max_qos_capabilies(&si->qos); 1012 1013 baudrate_mask = 0; 1014 if (si->pdata->transceiver_cap & IR_SIRMODE) 1015 baudrate_mask |= IR_9600|IR_19200|IR_38400|IR_57600|IR_115200; 1016 if (si->pdata->transceiver_cap & IR_FIRMODE) 1017 baudrate_mask |= IR_4000000 << 8; 1018 1019 si->qos.baud_rate.bits &= baudrate_mask; 1020 si->qos.min_turn_time.bits = 7; /* 1ms or more */ 1021 1022 irda_qos_bits_to_value(&si->qos); 1023 1024 err = register_netdev(dev); 1025 1026 if (err == 0) 1027 platform_set_drvdata(pdev, dev); 1028 1029 if (err) { 1030 if (si->pdata->shutdown) 1031 si->pdata->shutdown(si->dev); 1032err_startup: 1033 kfree(si->tx_buff.head); 1034err_mem_5: 1035 kfree(si->rx_buff.head); 1036err_mem_4: 1037 free_netdev(dev); 1038 } 1039err_mem_1: 1040 return err; 1041} 1042 1043static int pxa_irda_remove(struct platform_device *_dev) 1044{ 1045 struct net_device *dev = platform_get_drvdata(_dev); 1046 1047 if (dev) { 1048 struct pxa_irda *si = netdev_priv(dev); 1049 unregister_netdev(dev); 1050 if (gpio_is_valid(si->pdata->gpio_pwdown)) 1051 gpio_free(si->pdata->gpio_pwdown); 1052 if (si->pdata->shutdown) 1053 si->pdata->shutdown(si->dev); 1054 kfree(si->tx_buff.head); 1055 kfree(si->rx_buff.head); 1056 free_netdev(dev); 1057 } 1058 1059 return 0; 1060} 1061 1062static struct platform_driver pxa_ir_driver = { 1063 .driver = { 1064 .name = "pxa2xx-ir", 1065 }, 1066 .probe = pxa_irda_probe, 1067 .remove = pxa_irda_remove, 1068 .suspend = pxa_irda_suspend, 1069 .resume = pxa_irda_resume, 1070}; 1071 1072module_platform_driver(pxa_ir_driver); 1073 1074MODULE_LICENSE("GPL"); 1075MODULE_ALIAS("platform:pxa2xx-ir"); 1076