1/******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2015 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27#include "i40e_type.h" 28#include "i40e_adminq.h" 29#include "i40e_prototype.h" 30#include "i40e_virtchnl.h" 31 32/** 33 * i40e_set_mac_type - Sets MAC type 34 * @hw: pointer to the HW structure 35 * 36 * This function sets the mac type of the adapter based on the 37 * vendor ID and device ID stored in the hw structure. 38 **/ 39static i40e_status i40e_set_mac_type(struct i40e_hw *hw) 40{ 41 i40e_status status = 0; 42 43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 44 switch (hw->device_id) { 45 case I40E_DEV_ID_SFP_XL710: 46 case I40E_DEV_ID_QEMU: 47 case I40E_DEV_ID_KX_A: 48 case I40E_DEV_ID_KX_B: 49 case I40E_DEV_ID_KX_C: 50 case I40E_DEV_ID_QSFP_A: 51 case I40E_DEV_ID_QSFP_B: 52 case I40E_DEV_ID_QSFP_C: 53 case I40E_DEV_ID_10G_BASE_T: 54 case I40E_DEV_ID_10G_BASE_T4: 55 case I40E_DEV_ID_20G_KR2: 56 case I40E_DEV_ID_20G_KR2_A: 57 hw->mac.type = I40E_MAC_XL710; 58 break; 59 case I40E_DEV_ID_SFP_X722: 60 case I40E_DEV_ID_1G_BASE_T_X722: 61 case I40E_DEV_ID_10G_BASE_T_X722: 62 hw->mac.type = I40E_MAC_X722; 63 break; 64 case I40E_DEV_ID_X722_VF: 65 case I40E_DEV_ID_X722_VF_HV: 66 hw->mac.type = I40E_MAC_X722_VF; 67 break; 68 case I40E_DEV_ID_VF: 69 case I40E_DEV_ID_VF_HV: 70 hw->mac.type = I40E_MAC_VF; 71 break; 72 default: 73 hw->mac.type = I40E_MAC_GENERIC; 74 break; 75 } 76 } else { 77 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 78 } 79 80 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 81 hw->mac.type, status); 82 return status; 83} 84 85/** 86 * i40e_aq_str - convert AQ err code to a string 87 * @hw: pointer to the HW structure 88 * @aq_err: the AQ error code to convert 89 **/ 90const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 91{ 92 switch (aq_err) { 93 case I40E_AQ_RC_OK: 94 return "OK"; 95 case I40E_AQ_RC_EPERM: 96 return "I40E_AQ_RC_EPERM"; 97 case I40E_AQ_RC_ENOENT: 98 return "I40E_AQ_RC_ENOENT"; 99 case I40E_AQ_RC_ESRCH: 100 return "I40E_AQ_RC_ESRCH"; 101 case I40E_AQ_RC_EINTR: 102 return "I40E_AQ_RC_EINTR"; 103 case I40E_AQ_RC_EIO: 104 return "I40E_AQ_RC_EIO"; 105 case I40E_AQ_RC_ENXIO: 106 return "I40E_AQ_RC_ENXIO"; 107 case I40E_AQ_RC_E2BIG: 108 return "I40E_AQ_RC_E2BIG"; 109 case I40E_AQ_RC_EAGAIN: 110 return "I40E_AQ_RC_EAGAIN"; 111 case I40E_AQ_RC_ENOMEM: 112 return "I40E_AQ_RC_ENOMEM"; 113 case I40E_AQ_RC_EACCES: 114 return "I40E_AQ_RC_EACCES"; 115 case I40E_AQ_RC_EFAULT: 116 return "I40E_AQ_RC_EFAULT"; 117 case I40E_AQ_RC_EBUSY: 118 return "I40E_AQ_RC_EBUSY"; 119 case I40E_AQ_RC_EEXIST: 120 return "I40E_AQ_RC_EEXIST"; 121 case I40E_AQ_RC_EINVAL: 122 return "I40E_AQ_RC_EINVAL"; 123 case I40E_AQ_RC_ENOTTY: 124 return "I40E_AQ_RC_ENOTTY"; 125 case I40E_AQ_RC_ENOSPC: 126 return "I40E_AQ_RC_ENOSPC"; 127 case I40E_AQ_RC_ENOSYS: 128 return "I40E_AQ_RC_ENOSYS"; 129 case I40E_AQ_RC_ERANGE: 130 return "I40E_AQ_RC_ERANGE"; 131 case I40E_AQ_RC_EFLUSHED: 132 return "I40E_AQ_RC_EFLUSHED"; 133 case I40E_AQ_RC_BAD_ADDR: 134 return "I40E_AQ_RC_BAD_ADDR"; 135 case I40E_AQ_RC_EMODE: 136 return "I40E_AQ_RC_EMODE"; 137 case I40E_AQ_RC_EFBIG: 138 return "I40E_AQ_RC_EFBIG"; 139 } 140 141 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 142 return hw->err_str; 143} 144 145/** 146 * i40e_stat_str - convert status err code to a string 147 * @hw: pointer to the HW structure 148 * @stat_err: the status error code to convert 149 **/ 150const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err) 151{ 152 switch (stat_err) { 153 case 0: 154 return "OK"; 155 case I40E_ERR_NVM: 156 return "I40E_ERR_NVM"; 157 case I40E_ERR_NVM_CHECKSUM: 158 return "I40E_ERR_NVM_CHECKSUM"; 159 case I40E_ERR_PHY: 160 return "I40E_ERR_PHY"; 161 case I40E_ERR_CONFIG: 162 return "I40E_ERR_CONFIG"; 163 case I40E_ERR_PARAM: 164 return "I40E_ERR_PARAM"; 165 case I40E_ERR_MAC_TYPE: 166 return "I40E_ERR_MAC_TYPE"; 167 case I40E_ERR_UNKNOWN_PHY: 168 return "I40E_ERR_UNKNOWN_PHY"; 169 case I40E_ERR_LINK_SETUP: 170 return "I40E_ERR_LINK_SETUP"; 171 case I40E_ERR_ADAPTER_STOPPED: 172 return "I40E_ERR_ADAPTER_STOPPED"; 173 case I40E_ERR_INVALID_MAC_ADDR: 174 return "I40E_ERR_INVALID_MAC_ADDR"; 175 case I40E_ERR_DEVICE_NOT_SUPPORTED: 176 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 177 case I40E_ERR_MASTER_REQUESTS_PENDING: 178 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 179 case I40E_ERR_INVALID_LINK_SETTINGS: 180 return "I40E_ERR_INVALID_LINK_SETTINGS"; 181 case I40E_ERR_AUTONEG_NOT_COMPLETE: 182 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 183 case I40E_ERR_RESET_FAILED: 184 return "I40E_ERR_RESET_FAILED"; 185 case I40E_ERR_SWFW_SYNC: 186 return "I40E_ERR_SWFW_SYNC"; 187 case I40E_ERR_NO_AVAILABLE_VSI: 188 return "I40E_ERR_NO_AVAILABLE_VSI"; 189 case I40E_ERR_NO_MEMORY: 190 return "I40E_ERR_NO_MEMORY"; 191 case I40E_ERR_BAD_PTR: 192 return "I40E_ERR_BAD_PTR"; 193 case I40E_ERR_RING_FULL: 194 return "I40E_ERR_RING_FULL"; 195 case I40E_ERR_INVALID_PD_ID: 196 return "I40E_ERR_INVALID_PD_ID"; 197 case I40E_ERR_INVALID_QP_ID: 198 return "I40E_ERR_INVALID_QP_ID"; 199 case I40E_ERR_INVALID_CQ_ID: 200 return "I40E_ERR_INVALID_CQ_ID"; 201 case I40E_ERR_INVALID_CEQ_ID: 202 return "I40E_ERR_INVALID_CEQ_ID"; 203 case I40E_ERR_INVALID_AEQ_ID: 204 return "I40E_ERR_INVALID_AEQ_ID"; 205 case I40E_ERR_INVALID_SIZE: 206 return "I40E_ERR_INVALID_SIZE"; 207 case I40E_ERR_INVALID_ARP_INDEX: 208 return "I40E_ERR_INVALID_ARP_INDEX"; 209 case I40E_ERR_INVALID_FPM_FUNC_ID: 210 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 211 case I40E_ERR_QP_INVALID_MSG_SIZE: 212 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 213 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 214 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 215 case I40E_ERR_INVALID_FRAG_COUNT: 216 return "I40E_ERR_INVALID_FRAG_COUNT"; 217 case I40E_ERR_QUEUE_EMPTY: 218 return "I40E_ERR_QUEUE_EMPTY"; 219 case I40E_ERR_INVALID_ALIGNMENT: 220 return "I40E_ERR_INVALID_ALIGNMENT"; 221 case I40E_ERR_FLUSHED_QUEUE: 222 return "I40E_ERR_FLUSHED_QUEUE"; 223 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 224 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 225 case I40E_ERR_INVALID_IMM_DATA_SIZE: 226 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 227 case I40E_ERR_TIMEOUT: 228 return "I40E_ERR_TIMEOUT"; 229 case I40E_ERR_OPCODE_MISMATCH: 230 return "I40E_ERR_OPCODE_MISMATCH"; 231 case I40E_ERR_CQP_COMPL_ERROR: 232 return "I40E_ERR_CQP_COMPL_ERROR"; 233 case I40E_ERR_INVALID_VF_ID: 234 return "I40E_ERR_INVALID_VF_ID"; 235 case I40E_ERR_INVALID_HMCFN_ID: 236 return "I40E_ERR_INVALID_HMCFN_ID"; 237 case I40E_ERR_BACKING_PAGE_ERROR: 238 return "I40E_ERR_BACKING_PAGE_ERROR"; 239 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 240 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 241 case I40E_ERR_INVALID_PBLE_INDEX: 242 return "I40E_ERR_INVALID_PBLE_INDEX"; 243 case I40E_ERR_INVALID_SD_INDEX: 244 return "I40E_ERR_INVALID_SD_INDEX"; 245 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 246 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 247 case I40E_ERR_INVALID_SD_TYPE: 248 return "I40E_ERR_INVALID_SD_TYPE"; 249 case I40E_ERR_MEMCPY_FAILED: 250 return "I40E_ERR_MEMCPY_FAILED"; 251 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 252 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 253 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 254 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 255 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 256 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 257 case I40E_ERR_SRQ_ENABLED: 258 return "I40E_ERR_SRQ_ENABLED"; 259 case I40E_ERR_ADMIN_QUEUE_ERROR: 260 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 261 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 262 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 263 case I40E_ERR_BUF_TOO_SHORT: 264 return "I40E_ERR_BUF_TOO_SHORT"; 265 case I40E_ERR_ADMIN_QUEUE_FULL: 266 return "I40E_ERR_ADMIN_QUEUE_FULL"; 267 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 268 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 269 case I40E_ERR_BAD_IWARP_CQE: 270 return "I40E_ERR_BAD_IWARP_CQE"; 271 case I40E_ERR_NVM_BLANK_MODE: 272 return "I40E_ERR_NVM_BLANK_MODE"; 273 case I40E_ERR_NOT_IMPLEMENTED: 274 return "I40E_ERR_NOT_IMPLEMENTED"; 275 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 276 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 277 case I40E_ERR_DIAG_TEST_FAILED: 278 return "I40E_ERR_DIAG_TEST_FAILED"; 279 case I40E_ERR_NOT_READY: 280 return "I40E_ERR_NOT_READY"; 281 case I40E_NOT_SUPPORTED: 282 return "I40E_NOT_SUPPORTED"; 283 case I40E_ERR_FIRMWARE_API_VERSION: 284 return "I40E_ERR_FIRMWARE_API_VERSION"; 285 } 286 287 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 288 return hw->err_str; 289} 290 291/** 292 * i40e_debug_aq 293 * @hw: debug mask related to admin queue 294 * @mask: debug mask 295 * @desc: pointer to admin queue descriptor 296 * @buffer: pointer to command buffer 297 * @buf_len: max length of buffer 298 * 299 * Dumps debug log about adminq command with descriptor contents. 300 **/ 301void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 302 void *buffer, u16 buf_len) 303{ 304 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 305 u16 len = le16_to_cpu(aq_desc->datalen); 306 u8 *buf = (u8 *)buffer; 307 u16 i = 0; 308 309 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 310 return; 311 312 i40e_debug(hw, mask, 313 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 314 le16_to_cpu(aq_desc->opcode), 315 le16_to_cpu(aq_desc->flags), 316 le16_to_cpu(aq_desc->datalen), 317 le16_to_cpu(aq_desc->retval)); 318 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 319 le32_to_cpu(aq_desc->cookie_high), 320 le32_to_cpu(aq_desc->cookie_low)); 321 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 322 le32_to_cpu(aq_desc->params.internal.param0), 323 le32_to_cpu(aq_desc->params.internal.param1)); 324 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 325 le32_to_cpu(aq_desc->params.external.addr_high), 326 le32_to_cpu(aq_desc->params.external.addr_low)); 327 328 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 329 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 330 if (buf_len < len) 331 len = buf_len; 332 /* write the full 16-byte chunks */ 333 for (i = 0; i < (len - 16); i += 16) 334 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i); 335 /* write whatever's left over without overrunning the buffer */ 336 if (i < len) 337 i40e_debug(hw, mask, "\t0x%04X %*ph\n", 338 i, len - i, buf + i); 339 } 340} 341 342/** 343 * i40e_check_asq_alive 344 * @hw: pointer to the hw struct 345 * 346 * Returns true if Queue is enabled else false. 347 **/ 348bool i40e_check_asq_alive(struct i40e_hw *hw) 349{ 350 if (hw->aq.asq.len) 351 return !!(rd32(hw, hw->aq.asq.len) & 352 I40E_PF_ATQLEN_ATQENABLE_MASK); 353 else 354 return false; 355} 356 357/** 358 * i40e_aq_queue_shutdown 359 * @hw: pointer to the hw struct 360 * @unloading: is the driver unloading itself 361 * 362 * Tell the Firmware that we're shutting down the AdminQ and whether 363 * or not the driver is unloading as well. 364 **/ 365i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 366 bool unloading) 367{ 368 struct i40e_aq_desc desc; 369 struct i40e_aqc_queue_shutdown *cmd = 370 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 371 i40e_status status; 372 373 i40e_fill_default_direct_cmd_desc(&desc, 374 i40e_aqc_opc_queue_shutdown); 375 376 if (unloading) 377 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 378 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 379 380 return status; 381} 382 383/** 384 * i40e_aq_get_set_rss_lut 385 * @hw: pointer to the hardware structure 386 * @vsi_id: vsi fw index 387 * @pf_lut: for PF table set true, for VSI table set false 388 * @lut: pointer to the lut buffer provided by the caller 389 * @lut_size: size of the lut buffer 390 * @set: set true to set the table, false to get the table 391 * 392 * Internal function to get or set RSS look up table 393 **/ 394static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 395 u16 vsi_id, bool pf_lut, 396 u8 *lut, u16 lut_size, 397 bool set) 398{ 399 i40e_status status; 400 struct i40e_aq_desc desc; 401 struct i40e_aqc_get_set_rss_lut *cmd_resp = 402 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 403 404 if (set) 405 i40e_fill_default_direct_cmd_desc(&desc, 406 i40e_aqc_opc_set_rss_lut); 407 else 408 i40e_fill_default_direct_cmd_desc(&desc, 409 i40e_aqc_opc_get_rss_lut); 410 411 /* Indirect command */ 412 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 413 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 414 415 cmd_resp->vsi_id = 416 cpu_to_le16((u16)((vsi_id << 417 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 418 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 419 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 420 421 if (pf_lut) 422 cmd_resp->flags |= cpu_to_le16((u16) 423 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 424 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 425 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 426 else 427 cmd_resp->flags |= cpu_to_le16((u16) 428 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 429 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 430 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 431 432 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 433 434 return status; 435} 436 437/** 438 * i40e_aq_get_rss_lut 439 * @hw: pointer to the hardware structure 440 * @vsi_id: vsi fw index 441 * @pf_lut: for PF table set true, for VSI table set false 442 * @lut: pointer to the lut buffer provided by the caller 443 * @lut_size: size of the lut buffer 444 * 445 * get the RSS lookup table, PF or VSI type 446 **/ 447i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 448 bool pf_lut, u8 *lut, u16 lut_size) 449{ 450 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 451 false); 452} 453 454/** 455 * i40e_aq_set_rss_lut 456 * @hw: pointer to the hardware structure 457 * @vsi_id: vsi fw index 458 * @pf_lut: for PF table set true, for VSI table set false 459 * @lut: pointer to the lut buffer provided by the caller 460 * @lut_size: size of the lut buffer 461 * 462 * set the RSS lookup table, PF or VSI type 463 **/ 464i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 465 bool pf_lut, u8 *lut, u16 lut_size) 466{ 467 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 468} 469 470/** 471 * i40e_aq_get_set_rss_key 472 * @hw: pointer to the hw struct 473 * @vsi_id: vsi fw index 474 * @key: pointer to key info struct 475 * @set: set true to set the key, false to get the key 476 * 477 * get the RSS key per VSI 478 **/ 479static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw, 480 u16 vsi_id, 481 struct i40e_aqc_get_set_rss_key_data *key, 482 bool set) 483{ 484 i40e_status status; 485 struct i40e_aq_desc desc; 486 struct i40e_aqc_get_set_rss_key *cmd_resp = 487 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 488 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 489 490 if (set) 491 i40e_fill_default_direct_cmd_desc(&desc, 492 i40e_aqc_opc_set_rss_key); 493 else 494 i40e_fill_default_direct_cmd_desc(&desc, 495 i40e_aqc_opc_get_rss_key); 496 497 /* Indirect command */ 498 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 499 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 500 501 cmd_resp->vsi_id = 502 cpu_to_le16((u16)((vsi_id << 503 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 504 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 505 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 506 507 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 508 509 return status; 510} 511 512/** 513 * i40e_aq_get_rss_key 514 * @hw: pointer to the hw struct 515 * @vsi_id: vsi fw index 516 * @key: pointer to key info struct 517 * 518 **/ 519i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw, 520 u16 vsi_id, 521 struct i40e_aqc_get_set_rss_key_data *key) 522{ 523 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 524} 525 526/** 527 * i40e_aq_set_rss_key 528 * @hw: pointer to the hw struct 529 * @vsi_id: vsi fw index 530 * @key: pointer to key info struct 531 * 532 * set the RSS key per VSI 533 **/ 534i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw, 535 u16 vsi_id, 536 struct i40e_aqc_get_set_rss_key_data *key) 537{ 538 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 539} 540 541/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 542 * hardware to a bit-field that can be used by SW to more easily determine the 543 * packet type. 544 * 545 * Macros are used to shorten the table lines and make this table human 546 * readable. 547 * 548 * We store the PTYPE in the top byte of the bit field - this is just so that 549 * we can check that the table doesn't have a row missing, as the index into 550 * the table should be the PTYPE. 551 * 552 * Typical work flow: 553 * 554 * IF NOT i40e_ptype_lookup[ptype].known 555 * THEN 556 * Packet is unknown 557 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 558 * Use the rest of the fields to look at the tunnels, inner protocols, etc 559 * ELSE 560 * Use the enum i40e_rx_l2_ptype to decode the packet type 561 * ENDIF 562 */ 563 564/* macro to make the table lines short */ 565#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 566 { PTYPE, \ 567 1, \ 568 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 569 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 570 I40E_RX_PTYPE_##OUTER_FRAG, \ 571 I40E_RX_PTYPE_TUNNEL_##T, \ 572 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 573 I40E_RX_PTYPE_##TEF, \ 574 I40E_RX_PTYPE_INNER_PROT_##I, \ 575 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 576 577#define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 578 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 579 580/* shorter macros makes the table fit but are terse */ 581#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 582#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 583#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 584 585/* Lookup table mapping the HW PTYPE to the bit field for decoding */ 586struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 587 /* L2 Packet types */ 588 I40E_PTT_UNUSED_ENTRY(0), 589 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 590 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 591 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 592 I40E_PTT_UNUSED_ENTRY(4), 593 I40E_PTT_UNUSED_ENTRY(5), 594 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 595 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 596 I40E_PTT_UNUSED_ENTRY(8), 597 I40E_PTT_UNUSED_ENTRY(9), 598 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 599 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 600 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 601 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 602 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 603 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 604 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 605 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 606 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 607 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 608 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 609 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 610 611 /* Non Tunneled IPv4 */ 612 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 613 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 614 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 615 I40E_PTT_UNUSED_ENTRY(25), 616 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 617 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 618 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 619 620 /* IPv4 --> IPv4 */ 621 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 622 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 623 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 624 I40E_PTT_UNUSED_ENTRY(32), 625 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 626 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 627 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 628 629 /* IPv4 --> IPv6 */ 630 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 631 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 632 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 633 I40E_PTT_UNUSED_ENTRY(39), 634 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 635 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 636 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 637 638 /* IPv4 --> GRE/NAT */ 639 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 640 641 /* IPv4 --> GRE/NAT --> IPv4 */ 642 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 643 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 644 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 645 I40E_PTT_UNUSED_ENTRY(47), 646 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 647 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 648 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 649 650 /* IPv4 --> GRE/NAT --> IPv6 */ 651 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 652 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 653 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 654 I40E_PTT_UNUSED_ENTRY(54), 655 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 656 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 657 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 658 659 /* IPv4 --> GRE/NAT --> MAC */ 660 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 661 662 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 663 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 664 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 665 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 666 I40E_PTT_UNUSED_ENTRY(62), 667 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 668 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 669 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 670 671 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 672 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 673 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 674 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 675 I40E_PTT_UNUSED_ENTRY(69), 676 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 677 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 678 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 679 680 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 681 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 682 683 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 684 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 685 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 686 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 687 I40E_PTT_UNUSED_ENTRY(77), 688 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 689 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 690 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 691 692 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 693 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 694 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 695 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 696 I40E_PTT_UNUSED_ENTRY(84), 697 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 698 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 699 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 700 701 /* Non Tunneled IPv6 */ 702 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 703 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 704 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3), 705 I40E_PTT_UNUSED_ENTRY(91), 706 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 707 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 708 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 709 710 /* IPv6 --> IPv4 */ 711 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 712 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 713 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 714 I40E_PTT_UNUSED_ENTRY(98), 715 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 716 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 717 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 718 719 /* IPv6 --> IPv6 */ 720 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 721 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 722 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 723 I40E_PTT_UNUSED_ENTRY(105), 724 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 725 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 726 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 727 728 /* IPv6 --> GRE/NAT */ 729 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 730 731 /* IPv6 --> GRE/NAT -> IPv4 */ 732 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 733 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 734 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 735 I40E_PTT_UNUSED_ENTRY(113), 736 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 737 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 738 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 739 740 /* IPv6 --> GRE/NAT -> IPv6 */ 741 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 742 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 743 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 744 I40E_PTT_UNUSED_ENTRY(120), 745 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 746 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 747 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 748 749 /* IPv6 --> GRE/NAT -> MAC */ 750 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 751 752 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 753 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 754 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 755 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 756 I40E_PTT_UNUSED_ENTRY(128), 757 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 758 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 759 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 760 761 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 762 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 763 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 764 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 765 I40E_PTT_UNUSED_ENTRY(135), 766 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 767 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 768 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 769 770 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 771 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 772 773 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 774 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 775 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 776 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 777 I40E_PTT_UNUSED_ENTRY(143), 778 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 779 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 780 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 781 782 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 783 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 784 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 785 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 786 I40E_PTT_UNUSED_ENTRY(150), 787 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 788 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 789 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 790 791 /* unused entries */ 792 I40E_PTT_UNUSED_ENTRY(154), 793 I40E_PTT_UNUSED_ENTRY(155), 794 I40E_PTT_UNUSED_ENTRY(156), 795 I40E_PTT_UNUSED_ENTRY(157), 796 I40E_PTT_UNUSED_ENTRY(158), 797 I40E_PTT_UNUSED_ENTRY(159), 798 799 I40E_PTT_UNUSED_ENTRY(160), 800 I40E_PTT_UNUSED_ENTRY(161), 801 I40E_PTT_UNUSED_ENTRY(162), 802 I40E_PTT_UNUSED_ENTRY(163), 803 I40E_PTT_UNUSED_ENTRY(164), 804 I40E_PTT_UNUSED_ENTRY(165), 805 I40E_PTT_UNUSED_ENTRY(166), 806 I40E_PTT_UNUSED_ENTRY(167), 807 I40E_PTT_UNUSED_ENTRY(168), 808 I40E_PTT_UNUSED_ENTRY(169), 809 810 I40E_PTT_UNUSED_ENTRY(170), 811 I40E_PTT_UNUSED_ENTRY(171), 812 I40E_PTT_UNUSED_ENTRY(172), 813 I40E_PTT_UNUSED_ENTRY(173), 814 I40E_PTT_UNUSED_ENTRY(174), 815 I40E_PTT_UNUSED_ENTRY(175), 816 I40E_PTT_UNUSED_ENTRY(176), 817 I40E_PTT_UNUSED_ENTRY(177), 818 I40E_PTT_UNUSED_ENTRY(178), 819 I40E_PTT_UNUSED_ENTRY(179), 820 821 I40E_PTT_UNUSED_ENTRY(180), 822 I40E_PTT_UNUSED_ENTRY(181), 823 I40E_PTT_UNUSED_ENTRY(182), 824 I40E_PTT_UNUSED_ENTRY(183), 825 I40E_PTT_UNUSED_ENTRY(184), 826 I40E_PTT_UNUSED_ENTRY(185), 827 I40E_PTT_UNUSED_ENTRY(186), 828 I40E_PTT_UNUSED_ENTRY(187), 829 I40E_PTT_UNUSED_ENTRY(188), 830 I40E_PTT_UNUSED_ENTRY(189), 831 832 I40E_PTT_UNUSED_ENTRY(190), 833 I40E_PTT_UNUSED_ENTRY(191), 834 I40E_PTT_UNUSED_ENTRY(192), 835 I40E_PTT_UNUSED_ENTRY(193), 836 I40E_PTT_UNUSED_ENTRY(194), 837 I40E_PTT_UNUSED_ENTRY(195), 838 I40E_PTT_UNUSED_ENTRY(196), 839 I40E_PTT_UNUSED_ENTRY(197), 840 I40E_PTT_UNUSED_ENTRY(198), 841 I40E_PTT_UNUSED_ENTRY(199), 842 843 I40E_PTT_UNUSED_ENTRY(200), 844 I40E_PTT_UNUSED_ENTRY(201), 845 I40E_PTT_UNUSED_ENTRY(202), 846 I40E_PTT_UNUSED_ENTRY(203), 847 I40E_PTT_UNUSED_ENTRY(204), 848 I40E_PTT_UNUSED_ENTRY(205), 849 I40E_PTT_UNUSED_ENTRY(206), 850 I40E_PTT_UNUSED_ENTRY(207), 851 I40E_PTT_UNUSED_ENTRY(208), 852 I40E_PTT_UNUSED_ENTRY(209), 853 854 I40E_PTT_UNUSED_ENTRY(210), 855 I40E_PTT_UNUSED_ENTRY(211), 856 I40E_PTT_UNUSED_ENTRY(212), 857 I40E_PTT_UNUSED_ENTRY(213), 858 I40E_PTT_UNUSED_ENTRY(214), 859 I40E_PTT_UNUSED_ENTRY(215), 860 I40E_PTT_UNUSED_ENTRY(216), 861 I40E_PTT_UNUSED_ENTRY(217), 862 I40E_PTT_UNUSED_ENTRY(218), 863 I40E_PTT_UNUSED_ENTRY(219), 864 865 I40E_PTT_UNUSED_ENTRY(220), 866 I40E_PTT_UNUSED_ENTRY(221), 867 I40E_PTT_UNUSED_ENTRY(222), 868 I40E_PTT_UNUSED_ENTRY(223), 869 I40E_PTT_UNUSED_ENTRY(224), 870 I40E_PTT_UNUSED_ENTRY(225), 871 I40E_PTT_UNUSED_ENTRY(226), 872 I40E_PTT_UNUSED_ENTRY(227), 873 I40E_PTT_UNUSED_ENTRY(228), 874 I40E_PTT_UNUSED_ENTRY(229), 875 876 I40E_PTT_UNUSED_ENTRY(230), 877 I40E_PTT_UNUSED_ENTRY(231), 878 I40E_PTT_UNUSED_ENTRY(232), 879 I40E_PTT_UNUSED_ENTRY(233), 880 I40E_PTT_UNUSED_ENTRY(234), 881 I40E_PTT_UNUSED_ENTRY(235), 882 I40E_PTT_UNUSED_ENTRY(236), 883 I40E_PTT_UNUSED_ENTRY(237), 884 I40E_PTT_UNUSED_ENTRY(238), 885 I40E_PTT_UNUSED_ENTRY(239), 886 887 I40E_PTT_UNUSED_ENTRY(240), 888 I40E_PTT_UNUSED_ENTRY(241), 889 I40E_PTT_UNUSED_ENTRY(242), 890 I40E_PTT_UNUSED_ENTRY(243), 891 I40E_PTT_UNUSED_ENTRY(244), 892 I40E_PTT_UNUSED_ENTRY(245), 893 I40E_PTT_UNUSED_ENTRY(246), 894 I40E_PTT_UNUSED_ENTRY(247), 895 I40E_PTT_UNUSED_ENTRY(248), 896 I40E_PTT_UNUSED_ENTRY(249), 897 898 I40E_PTT_UNUSED_ENTRY(250), 899 I40E_PTT_UNUSED_ENTRY(251), 900 I40E_PTT_UNUSED_ENTRY(252), 901 I40E_PTT_UNUSED_ENTRY(253), 902 I40E_PTT_UNUSED_ENTRY(254), 903 I40E_PTT_UNUSED_ENTRY(255) 904}; 905 906/** 907 * i40e_init_shared_code - Initialize the shared code 908 * @hw: pointer to hardware structure 909 * 910 * This assigns the MAC type and PHY code and inits the NVM. 911 * Does not touch the hardware. This function must be called prior to any 912 * other function in the shared code. The i40e_hw structure should be 913 * memset to 0 prior to calling this function. The following fields in 914 * hw structure should be filled in prior to calling this function: 915 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 916 * subsystem_vendor_id, and revision_id 917 **/ 918i40e_status i40e_init_shared_code(struct i40e_hw *hw) 919{ 920 i40e_status status = 0; 921 u32 port, ari, func_rid; 922 923 i40e_set_mac_type(hw); 924 925 switch (hw->mac.type) { 926 case I40E_MAC_XL710: 927 case I40E_MAC_X722: 928 break; 929 default: 930 return I40E_ERR_DEVICE_NOT_SUPPORTED; 931 } 932 933 hw->phy.get_link_info = true; 934 935 /* Determine port number and PF number*/ 936 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 937 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 938 hw->port = (u8)port; 939 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 940 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 941 func_rid = rd32(hw, I40E_PF_FUNC_RID); 942 if (ari) 943 hw->pf_id = (u8)(func_rid & 0xff); 944 else 945 hw->pf_id = (u8)(func_rid & 0x7); 946 947 if (hw->mac.type == I40E_MAC_X722) 948 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE; 949 950 status = i40e_init_nvm(hw); 951 return status; 952} 953 954/** 955 * i40e_aq_mac_address_read - Retrieve the MAC addresses 956 * @hw: pointer to the hw struct 957 * @flags: a return indicator of what addresses were added to the addr store 958 * @addrs: the requestor's mac addr store 959 * @cmd_details: pointer to command details structure or NULL 960 **/ 961static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 962 u16 *flags, 963 struct i40e_aqc_mac_address_read_data *addrs, 964 struct i40e_asq_cmd_details *cmd_details) 965{ 966 struct i40e_aq_desc desc; 967 struct i40e_aqc_mac_address_read *cmd_data = 968 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 969 i40e_status status; 970 971 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 972 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 973 974 status = i40e_asq_send_command(hw, &desc, addrs, 975 sizeof(*addrs), cmd_details); 976 *flags = le16_to_cpu(cmd_data->command_flags); 977 978 return status; 979} 980 981/** 982 * i40e_aq_mac_address_write - Change the MAC addresses 983 * @hw: pointer to the hw struct 984 * @flags: indicates which MAC to be written 985 * @mac_addr: address to write 986 * @cmd_details: pointer to command details structure or NULL 987 **/ 988i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 989 u16 flags, u8 *mac_addr, 990 struct i40e_asq_cmd_details *cmd_details) 991{ 992 struct i40e_aq_desc desc; 993 struct i40e_aqc_mac_address_write *cmd_data = 994 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 995 i40e_status status; 996 997 i40e_fill_default_direct_cmd_desc(&desc, 998 i40e_aqc_opc_mac_address_write); 999 cmd_data->command_flags = cpu_to_le16(flags); 1000 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 1001 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 1002 ((u32)mac_addr[3] << 16) | 1003 ((u32)mac_addr[4] << 8) | 1004 mac_addr[5]); 1005 1006 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1007 1008 return status; 1009} 1010 1011/** 1012 * i40e_get_mac_addr - get MAC address 1013 * @hw: pointer to the HW structure 1014 * @mac_addr: pointer to MAC address 1015 * 1016 * Reads the adapter's MAC address from register 1017 **/ 1018i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1019{ 1020 struct i40e_aqc_mac_address_read_data addrs; 1021 i40e_status status; 1022 u16 flags = 0; 1023 1024 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1025 1026 if (flags & I40E_AQC_LAN_ADDR_VALID) 1027 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 1028 1029 return status; 1030} 1031 1032/** 1033 * i40e_get_port_mac_addr - get Port MAC address 1034 * @hw: pointer to the HW structure 1035 * @mac_addr: pointer to Port MAC address 1036 * 1037 * Reads the adapter's Port MAC address 1038 **/ 1039i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1040{ 1041 struct i40e_aqc_mac_address_read_data addrs; 1042 i40e_status status; 1043 u16 flags = 0; 1044 1045 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1046 if (status) 1047 return status; 1048 1049 if (flags & I40E_AQC_PORT_ADDR_VALID) 1050 ether_addr_copy(mac_addr, addrs.port_mac); 1051 else 1052 status = I40E_ERR_INVALID_MAC_ADDR; 1053 1054 return status; 1055} 1056 1057/** 1058 * i40e_pre_tx_queue_cfg - pre tx queue configure 1059 * @hw: pointer to the HW structure 1060 * @queue: target PF queue index 1061 * @enable: state change request 1062 * 1063 * Handles hw requirement to indicate intention to enable 1064 * or disable target queue. 1065 **/ 1066void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1067{ 1068 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1069 u32 reg_block = 0; 1070 u32 reg_val; 1071 1072 if (abs_queue_idx >= 128) { 1073 reg_block = abs_queue_idx / 128; 1074 abs_queue_idx %= 128; 1075 } 1076 1077 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1078 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1079 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1080 1081 if (enable) 1082 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1083 else 1084 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1085 1086 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1087} 1088#ifdef I40E_FCOE 1089 1090/** 1091 * i40e_get_san_mac_addr - get SAN MAC address 1092 * @hw: pointer to the HW structure 1093 * @mac_addr: pointer to SAN MAC address 1094 * 1095 * Reads the adapter's SAN MAC address from NVM 1096 **/ 1097i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1098{ 1099 struct i40e_aqc_mac_address_read_data addrs; 1100 i40e_status status; 1101 u16 flags = 0; 1102 1103 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1104 if (status) 1105 return status; 1106 1107 if (flags & I40E_AQC_SAN_ADDR_VALID) 1108 ether_addr_copy(mac_addr, addrs.pf_san_mac); 1109 else 1110 status = I40E_ERR_INVALID_MAC_ADDR; 1111 1112 return status; 1113} 1114#endif 1115 1116/** 1117 * i40e_read_pba_string - Reads part number string from EEPROM 1118 * @hw: pointer to hardware structure 1119 * @pba_num: stores the part number string from the EEPROM 1120 * @pba_num_size: part number string buffer length 1121 * 1122 * Reads the part number string from the EEPROM. 1123 **/ 1124i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1125 u32 pba_num_size) 1126{ 1127 i40e_status status = 0; 1128 u16 pba_word = 0; 1129 u16 pba_size = 0; 1130 u16 pba_ptr = 0; 1131 u16 i = 0; 1132 1133 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1134 if (status || (pba_word != 0xFAFA)) { 1135 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); 1136 return status; 1137 } 1138 1139 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1140 if (status) { 1141 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 1142 return status; 1143 } 1144 1145 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1146 if (status) { 1147 hw_dbg(hw, "Failed to read PBA Block size.\n"); 1148 return status; 1149 } 1150 1151 /* Subtract one to get PBA word count (PBA Size word is included in 1152 * total size) 1153 */ 1154 pba_size--; 1155 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1156 hw_dbg(hw, "Buffer to small for PBA data.\n"); 1157 return I40E_ERR_PARAM; 1158 } 1159 1160 for (i = 0; i < pba_size; i++) { 1161 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1162 if (status) { 1163 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 1164 return status; 1165 } 1166 1167 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1168 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1169 } 1170 pba_num[(pba_size * 2)] = '\0'; 1171 1172 return status; 1173} 1174 1175/** 1176 * i40e_get_media_type - Gets media type 1177 * @hw: pointer to the hardware structure 1178 **/ 1179static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1180{ 1181 enum i40e_media_type media; 1182 1183 switch (hw->phy.link_info.phy_type) { 1184 case I40E_PHY_TYPE_10GBASE_SR: 1185 case I40E_PHY_TYPE_10GBASE_LR: 1186 case I40E_PHY_TYPE_1000BASE_SX: 1187 case I40E_PHY_TYPE_1000BASE_LX: 1188 case I40E_PHY_TYPE_40GBASE_SR4: 1189 case I40E_PHY_TYPE_40GBASE_LR4: 1190 media = I40E_MEDIA_TYPE_FIBER; 1191 break; 1192 case I40E_PHY_TYPE_100BASE_TX: 1193 case I40E_PHY_TYPE_1000BASE_T: 1194 case I40E_PHY_TYPE_10GBASE_T: 1195 media = I40E_MEDIA_TYPE_BASET; 1196 break; 1197 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1198 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1199 case I40E_PHY_TYPE_10GBASE_CR1: 1200 case I40E_PHY_TYPE_40GBASE_CR4: 1201 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1202 case I40E_PHY_TYPE_40GBASE_AOC: 1203 case I40E_PHY_TYPE_10GBASE_AOC: 1204 media = I40E_MEDIA_TYPE_DA; 1205 break; 1206 case I40E_PHY_TYPE_1000BASE_KX: 1207 case I40E_PHY_TYPE_10GBASE_KX4: 1208 case I40E_PHY_TYPE_10GBASE_KR: 1209 case I40E_PHY_TYPE_40GBASE_KR4: 1210 case I40E_PHY_TYPE_20GBASE_KR2: 1211 media = I40E_MEDIA_TYPE_BACKPLANE; 1212 break; 1213 case I40E_PHY_TYPE_SGMII: 1214 case I40E_PHY_TYPE_XAUI: 1215 case I40E_PHY_TYPE_XFI: 1216 case I40E_PHY_TYPE_XLAUI: 1217 case I40E_PHY_TYPE_XLPPI: 1218 default: 1219 media = I40E_MEDIA_TYPE_UNKNOWN; 1220 break; 1221 } 1222 1223 return media; 1224} 1225 1226#define I40E_PF_RESET_WAIT_COUNT_A0 200 1227#define I40E_PF_RESET_WAIT_COUNT 200 1228/** 1229 * i40e_pf_reset - Reset the PF 1230 * @hw: pointer to the hardware structure 1231 * 1232 * Assuming someone else has triggered a global reset, 1233 * assure the global reset is complete and then reset the PF 1234 **/ 1235i40e_status i40e_pf_reset(struct i40e_hw *hw) 1236{ 1237 u32 cnt = 0; 1238 u32 cnt1 = 0; 1239 u32 reg = 0; 1240 u32 grst_del; 1241 1242 /* Poll for Global Reset steady state in case of recent GRST. 1243 * The grst delay value is in 100ms units, and we'll wait a 1244 * couple counts longer to be sure we don't just miss the end. 1245 */ 1246 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1247 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1248 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1249 for (cnt = 0; cnt < grst_del + 10; cnt++) { 1250 reg = rd32(hw, I40E_GLGEN_RSTAT); 1251 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1252 break; 1253 msleep(100); 1254 } 1255 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1256 hw_dbg(hw, "Global reset polling failed to complete.\n"); 1257 return I40E_ERR_RESET_FAILED; 1258 } 1259 1260 /* Now Wait for the FW to be ready */ 1261 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1262 reg = rd32(hw, I40E_GLNVM_ULD); 1263 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1264 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1265 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1266 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1267 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 1268 break; 1269 } 1270 usleep_range(10000, 20000); 1271 } 1272 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1273 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1274 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 1275 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 1276 return I40E_ERR_RESET_FAILED; 1277 } 1278 1279 /* If there was a Global Reset in progress when we got here, 1280 * we don't need to do the PF Reset 1281 */ 1282 if (!cnt) { 1283 if (hw->revision_id == 0) 1284 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 1285 else 1286 cnt = I40E_PF_RESET_WAIT_COUNT; 1287 reg = rd32(hw, I40E_PFGEN_CTRL); 1288 wr32(hw, I40E_PFGEN_CTRL, 1289 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1290 for (; cnt; cnt--) { 1291 reg = rd32(hw, I40E_PFGEN_CTRL); 1292 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1293 break; 1294 usleep_range(1000, 2000); 1295 } 1296 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1297 hw_dbg(hw, "PF reset polling failed to complete.\n"); 1298 return I40E_ERR_RESET_FAILED; 1299 } 1300 } 1301 1302 i40e_clear_pxe_mode(hw); 1303 1304 return 0; 1305} 1306 1307/** 1308 * i40e_clear_hw - clear out any left over hw state 1309 * @hw: pointer to the hw struct 1310 * 1311 * Clear queues and interrupts, typically called at init time, 1312 * but after the capabilities have been found so we know how many 1313 * queues and msix vectors have been allocated. 1314 **/ 1315void i40e_clear_hw(struct i40e_hw *hw) 1316{ 1317 u32 num_queues, base_queue; 1318 u32 num_pf_int; 1319 u32 num_vf_int; 1320 u32 num_vfs; 1321 u32 i, j; 1322 u32 val; 1323 u32 eol = 0x7ff; 1324 1325 /* get number of interrupts, queues, and VFs */ 1326 val = rd32(hw, I40E_GLPCI_CNF2); 1327 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1328 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1329 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1330 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1331 1332 val = rd32(hw, I40E_PFLAN_QALLOC); 1333 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1334 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1335 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1336 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1337 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1338 num_queues = (j - base_queue) + 1; 1339 else 1340 num_queues = 0; 1341 1342 val = rd32(hw, I40E_PF_VT_PFALLOC); 1343 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1344 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1345 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1346 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1347 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1348 num_vfs = (j - i) + 1; 1349 else 1350 num_vfs = 0; 1351 1352 /* stop all the interrupts */ 1353 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1354 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1355 for (i = 0; i < num_pf_int - 2; i++) 1356 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1357 1358 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1359 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1360 wr32(hw, I40E_PFINT_LNKLST0, val); 1361 for (i = 0; i < num_pf_int - 2; i++) 1362 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1363 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1364 for (i = 0; i < num_vfs; i++) 1365 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1366 for (i = 0; i < num_vf_int - 2; i++) 1367 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1368 1369 /* warn the HW of the coming Tx disables */ 1370 for (i = 0; i < num_queues; i++) { 1371 u32 abs_queue_idx = base_queue + i; 1372 u32 reg_block = 0; 1373 1374 if (abs_queue_idx >= 128) { 1375 reg_block = abs_queue_idx / 128; 1376 abs_queue_idx %= 128; 1377 } 1378 1379 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1380 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1381 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1382 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1383 1384 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1385 } 1386 udelay(400); 1387 1388 /* stop all the queues */ 1389 for (i = 0; i < num_queues; i++) { 1390 wr32(hw, I40E_QINT_TQCTL(i), 0); 1391 wr32(hw, I40E_QTX_ENA(i), 0); 1392 wr32(hw, I40E_QINT_RQCTL(i), 0); 1393 wr32(hw, I40E_QRX_ENA(i), 0); 1394 } 1395 1396 /* short wait for all queue disables to settle */ 1397 udelay(50); 1398} 1399 1400/** 1401 * i40e_clear_pxe_mode - clear pxe operations mode 1402 * @hw: pointer to the hw struct 1403 * 1404 * Make sure all PXE mode settings are cleared, including things 1405 * like descriptor fetch/write-back mode. 1406 **/ 1407void i40e_clear_pxe_mode(struct i40e_hw *hw) 1408{ 1409 u32 reg; 1410 1411 if (i40e_check_asq_alive(hw)) 1412 i40e_aq_clear_pxe_mode(hw, NULL); 1413 1414 /* Clear single descriptor fetch/write-back mode */ 1415 reg = rd32(hw, I40E_GLLAN_RCTL_0); 1416 1417 if (hw->revision_id == 0) { 1418 /* As a work around clear PXE_MODE instead of setting it */ 1419 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 1420 } else { 1421 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 1422 } 1423} 1424 1425/** 1426 * i40e_led_is_mine - helper to find matching led 1427 * @hw: pointer to the hw struct 1428 * @idx: index into GPIO registers 1429 * 1430 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1431 */ 1432static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1433{ 1434 u32 gpio_val = 0; 1435 u32 port; 1436 1437 if (!hw->func_caps.led[idx]) 1438 return 0; 1439 1440 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1441 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1442 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1443 1444 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1445 * if it is not our port then ignore 1446 */ 1447 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1448 (port != hw->port)) 1449 return 0; 1450 1451 return gpio_val; 1452} 1453 1454#define I40E_COMBINED_ACTIVITY 0xA 1455#define I40E_FILTER_ACTIVITY 0xE 1456#define I40E_LINK_ACTIVITY 0xC 1457#define I40E_MAC_ACTIVITY 0xD 1458#define I40E_LED0 22 1459 1460/** 1461 * i40e_led_get - return current on/off mode 1462 * @hw: pointer to the hw struct 1463 * 1464 * The value returned is the 'mode' field as defined in the 1465 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1466 * values are variations of possible behaviors relating to 1467 * blink, link, and wire. 1468 **/ 1469u32 i40e_led_get(struct i40e_hw *hw) 1470{ 1471 u32 current_mode = 0; 1472 u32 mode = 0; 1473 int i; 1474 1475 /* as per the documentation GPIO 22-29 are the LED 1476 * GPIO pins named LED0..LED7 1477 */ 1478 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1479 u32 gpio_val = i40e_led_is_mine(hw, i); 1480 1481 if (!gpio_val) 1482 continue; 1483 1484 /* ignore gpio LED src mode entries related to the activity 1485 * LEDs 1486 */ 1487 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1488 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1489 switch (current_mode) { 1490 case I40E_COMBINED_ACTIVITY: 1491 case I40E_FILTER_ACTIVITY: 1492 case I40E_MAC_ACTIVITY: 1493 continue; 1494 default: 1495 break; 1496 } 1497 1498 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1499 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1500 break; 1501 } 1502 1503 return mode; 1504} 1505 1506/** 1507 * i40e_led_set - set new on/off mode 1508 * @hw: pointer to the hw struct 1509 * @mode: 0=off, 0xf=on (else see manual for mode details) 1510 * @blink: true if the LED should blink when on, false if steady 1511 * 1512 * if this function is used to turn on the blink it should 1513 * be used to disable the blink when restoring the original state. 1514 **/ 1515void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1516{ 1517 u32 current_mode = 0; 1518 int i; 1519 1520 if (mode & 0xfffffff0) 1521 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1522 1523 /* as per the documentation GPIO 22-29 are the LED 1524 * GPIO pins named LED0..LED7 1525 */ 1526 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1527 u32 gpio_val = i40e_led_is_mine(hw, i); 1528 1529 if (!gpio_val) 1530 continue; 1531 1532 /* ignore gpio LED src mode entries related to the activity 1533 * LEDs 1534 */ 1535 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1536 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1537 switch (current_mode) { 1538 case I40E_COMBINED_ACTIVITY: 1539 case I40E_FILTER_ACTIVITY: 1540 case I40E_MAC_ACTIVITY: 1541 continue; 1542 default: 1543 break; 1544 } 1545 1546 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1547 /* this & is a bit of paranoia, but serves as a range check */ 1548 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1549 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1550 1551 if (mode == I40E_LINK_ACTIVITY) 1552 blink = false; 1553 1554 if (blink) 1555 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1556 else 1557 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1558 1559 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1560 break; 1561 } 1562} 1563 1564/* Admin command wrappers */ 1565 1566/** 1567 * i40e_aq_get_phy_capabilities 1568 * @hw: pointer to the hw struct 1569 * @abilities: structure for PHY capabilities to be filled 1570 * @qualified_modules: report Qualified Modules 1571 * @report_init: report init capabilities (active are default) 1572 * @cmd_details: pointer to command details structure or NULL 1573 * 1574 * Returns the various PHY abilities supported on the Port. 1575 **/ 1576i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1577 bool qualified_modules, bool report_init, 1578 struct i40e_aq_get_phy_abilities_resp *abilities, 1579 struct i40e_asq_cmd_details *cmd_details) 1580{ 1581 struct i40e_aq_desc desc; 1582 i40e_status status; 1583 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1584 1585 if (!abilities) 1586 return I40E_ERR_PARAM; 1587 1588 i40e_fill_default_direct_cmd_desc(&desc, 1589 i40e_aqc_opc_get_phy_abilities); 1590 1591 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1592 if (abilities_size > I40E_AQ_LARGE_BUF) 1593 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1594 1595 if (qualified_modules) 1596 desc.params.external.param0 |= 1597 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1598 1599 if (report_init) 1600 desc.params.external.param0 |= 1601 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1602 1603 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1604 cmd_details); 1605 1606 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1607 status = I40E_ERR_UNKNOWN_PHY; 1608 1609 if (report_init) 1610 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1611 1612 return status; 1613} 1614 1615/** 1616 * i40e_aq_set_phy_config 1617 * @hw: pointer to the hw struct 1618 * @config: structure with PHY configuration to be set 1619 * @cmd_details: pointer to command details structure or NULL 1620 * 1621 * Set the various PHY configuration parameters 1622 * supported on the Port.One or more of the Set PHY config parameters may be 1623 * ignored in an MFP mode as the PF may not have the privilege to set some 1624 * of the PHY Config parameters. This status will be indicated by the 1625 * command response. 1626 **/ 1627enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1628 struct i40e_aq_set_phy_config *config, 1629 struct i40e_asq_cmd_details *cmd_details) 1630{ 1631 struct i40e_aq_desc desc; 1632 struct i40e_aq_set_phy_config *cmd = 1633 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1634 enum i40e_status_code status; 1635 1636 if (!config) 1637 return I40E_ERR_PARAM; 1638 1639 i40e_fill_default_direct_cmd_desc(&desc, 1640 i40e_aqc_opc_set_phy_config); 1641 1642 *cmd = *config; 1643 1644 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1645 1646 return status; 1647} 1648 1649/** 1650 * i40e_set_fc 1651 * @hw: pointer to the hw struct 1652 * 1653 * Set the requested flow control mode using set_phy_config. 1654 **/ 1655enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1656 bool atomic_restart) 1657{ 1658 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1659 struct i40e_aq_get_phy_abilities_resp abilities; 1660 struct i40e_aq_set_phy_config config; 1661 enum i40e_status_code status; 1662 u8 pause_mask = 0x0; 1663 1664 *aq_failures = 0x0; 1665 1666 switch (fc_mode) { 1667 case I40E_FC_FULL: 1668 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1669 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1670 break; 1671 case I40E_FC_RX_PAUSE: 1672 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1673 break; 1674 case I40E_FC_TX_PAUSE: 1675 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1676 break; 1677 default: 1678 break; 1679 } 1680 1681 /* Get the current phy config */ 1682 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1683 NULL); 1684 if (status) { 1685 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1686 return status; 1687 } 1688 1689 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1690 /* clear the old pause settings */ 1691 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1692 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1693 /* set the new abilities */ 1694 config.abilities |= pause_mask; 1695 /* If the abilities have changed, then set the new config */ 1696 if (config.abilities != abilities.abilities) { 1697 /* Auto restart link so settings take effect */ 1698 if (atomic_restart) 1699 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1700 /* Copy over all the old settings */ 1701 config.phy_type = abilities.phy_type; 1702 config.link_speed = abilities.link_speed; 1703 config.eee_capability = abilities.eee_capability; 1704 config.eeer = abilities.eeer_val; 1705 config.low_power_ctrl = abilities.d3_lpan; 1706 status = i40e_aq_set_phy_config(hw, &config, NULL); 1707 1708 if (status) 1709 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1710 } 1711 /* Update the link info */ 1712 status = i40e_update_link_info(hw); 1713 if (status) { 1714 /* Wait a little bit (on 40G cards it sometimes takes a really 1715 * long time for link to come back from the atomic reset) 1716 * and try once more 1717 */ 1718 msleep(1000); 1719 status = i40e_update_link_info(hw); 1720 } 1721 if (status) 1722 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1723 1724 return status; 1725} 1726 1727/** 1728 * i40e_aq_clear_pxe_mode 1729 * @hw: pointer to the hw struct 1730 * @cmd_details: pointer to command details structure or NULL 1731 * 1732 * Tell the firmware that the driver is taking over from PXE 1733 **/ 1734i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1735 struct i40e_asq_cmd_details *cmd_details) 1736{ 1737 i40e_status status; 1738 struct i40e_aq_desc desc; 1739 struct i40e_aqc_clear_pxe *cmd = 1740 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1741 1742 i40e_fill_default_direct_cmd_desc(&desc, 1743 i40e_aqc_opc_clear_pxe_mode); 1744 1745 cmd->rx_cnt = 0x2; 1746 1747 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1748 1749 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1750 1751 return status; 1752} 1753 1754/** 1755 * i40e_aq_set_link_restart_an 1756 * @hw: pointer to the hw struct 1757 * @enable_link: if true: enable link, if false: disable link 1758 * @cmd_details: pointer to command details structure or NULL 1759 * 1760 * Sets up the link and restarts the Auto-Negotiation over the link. 1761 **/ 1762i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1763 bool enable_link, 1764 struct i40e_asq_cmd_details *cmd_details) 1765{ 1766 struct i40e_aq_desc desc; 1767 struct i40e_aqc_set_link_restart_an *cmd = 1768 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1769 i40e_status status; 1770 1771 i40e_fill_default_direct_cmd_desc(&desc, 1772 i40e_aqc_opc_set_link_restart_an); 1773 1774 cmd->command = I40E_AQ_PHY_RESTART_AN; 1775 if (enable_link) 1776 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1777 else 1778 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1779 1780 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1781 1782 return status; 1783} 1784 1785/** 1786 * i40e_aq_get_link_info 1787 * @hw: pointer to the hw struct 1788 * @enable_lse: enable/disable LinkStatusEvent reporting 1789 * @link: pointer to link status structure - optional 1790 * @cmd_details: pointer to command details structure or NULL 1791 * 1792 * Returns the link status of the adapter. 1793 **/ 1794i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1795 bool enable_lse, struct i40e_link_status *link, 1796 struct i40e_asq_cmd_details *cmd_details) 1797{ 1798 struct i40e_aq_desc desc; 1799 struct i40e_aqc_get_link_status *resp = 1800 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1801 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1802 i40e_status status; 1803 bool tx_pause, rx_pause; 1804 u16 command_flags; 1805 1806 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1807 1808 if (enable_lse) 1809 command_flags = I40E_AQ_LSE_ENABLE; 1810 else 1811 command_flags = I40E_AQ_LSE_DISABLE; 1812 resp->command_flags = cpu_to_le16(command_flags); 1813 1814 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1815 1816 if (status) 1817 goto aq_get_link_info_exit; 1818 1819 /* save off old link status information */ 1820 hw->phy.link_info_old = *hw_link_info; 1821 1822 /* update link status */ 1823 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1824 hw->phy.media_type = i40e_get_media_type(hw); 1825 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1826 hw_link_info->link_info = resp->link_info; 1827 hw_link_info->an_info = resp->an_info; 1828 hw_link_info->ext_info = resp->ext_info; 1829 hw_link_info->loopback = resp->loopback; 1830 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1831 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1832 1833 /* update fc info */ 1834 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1835 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1836 if (tx_pause & rx_pause) 1837 hw->fc.current_mode = I40E_FC_FULL; 1838 else if (tx_pause) 1839 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1840 else if (rx_pause) 1841 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1842 else 1843 hw->fc.current_mode = I40E_FC_NONE; 1844 1845 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1846 hw_link_info->crc_enable = true; 1847 else 1848 hw_link_info->crc_enable = false; 1849 1850 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE)) 1851 hw_link_info->lse_enable = true; 1852 else 1853 hw_link_info->lse_enable = false; 1854 1855 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1856 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1857 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1858 1859 /* save link status information */ 1860 if (link) 1861 *link = *hw_link_info; 1862 1863 /* flag cleared so helper functions don't call AQ again */ 1864 hw->phy.get_link_info = false; 1865 1866aq_get_link_info_exit: 1867 return status; 1868} 1869 1870/** 1871 * i40e_aq_set_phy_int_mask 1872 * @hw: pointer to the hw struct 1873 * @mask: interrupt mask to be set 1874 * @cmd_details: pointer to command details structure or NULL 1875 * 1876 * Set link interrupt mask. 1877 **/ 1878i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1879 u16 mask, 1880 struct i40e_asq_cmd_details *cmd_details) 1881{ 1882 struct i40e_aq_desc desc; 1883 struct i40e_aqc_set_phy_int_mask *cmd = 1884 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1885 i40e_status status; 1886 1887 i40e_fill_default_direct_cmd_desc(&desc, 1888 i40e_aqc_opc_set_phy_int_mask); 1889 1890 cmd->event_mask = cpu_to_le16(mask); 1891 1892 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1893 1894 return status; 1895} 1896 1897/** 1898 * i40e_aq_add_vsi 1899 * @hw: pointer to the hw struct 1900 * @vsi_ctx: pointer to a vsi context struct 1901 * @cmd_details: pointer to command details structure or NULL 1902 * 1903 * Add a VSI context to the hardware. 1904**/ 1905i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1906 struct i40e_vsi_context *vsi_ctx, 1907 struct i40e_asq_cmd_details *cmd_details) 1908{ 1909 struct i40e_aq_desc desc; 1910 struct i40e_aqc_add_get_update_vsi *cmd = 1911 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1912 struct i40e_aqc_add_get_update_vsi_completion *resp = 1913 (struct i40e_aqc_add_get_update_vsi_completion *) 1914 &desc.params.raw; 1915 i40e_status status; 1916 1917 i40e_fill_default_direct_cmd_desc(&desc, 1918 i40e_aqc_opc_add_vsi); 1919 1920 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1921 cmd->connection_type = vsi_ctx->connection_type; 1922 cmd->vf_id = vsi_ctx->vf_num; 1923 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1924 1925 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1926 1927 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1928 sizeof(vsi_ctx->info), cmd_details); 1929 1930 if (status) 1931 goto aq_add_vsi_exit; 1932 1933 vsi_ctx->seid = le16_to_cpu(resp->seid); 1934 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1935 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1936 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1937 1938aq_add_vsi_exit: 1939 return status; 1940} 1941 1942/** 1943 * i40e_aq_set_vsi_unicast_promiscuous 1944 * @hw: pointer to the hw struct 1945 * @seid: vsi number 1946 * @set: set unicast promiscuous enable/disable 1947 * @cmd_details: pointer to command details structure or NULL 1948 **/ 1949i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 1950 u16 seid, bool set, 1951 struct i40e_asq_cmd_details *cmd_details) 1952{ 1953 struct i40e_aq_desc desc; 1954 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1955 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1956 i40e_status status; 1957 u16 flags = 0; 1958 1959 i40e_fill_default_direct_cmd_desc(&desc, 1960 i40e_aqc_opc_set_vsi_promiscuous_modes); 1961 1962 if (set) 1963 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1964 1965 cmd->promiscuous_flags = cpu_to_le16(flags); 1966 1967 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1968 1969 cmd->seid = cpu_to_le16(seid); 1970 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1971 1972 return status; 1973} 1974 1975/** 1976 * i40e_aq_set_vsi_multicast_promiscuous 1977 * @hw: pointer to the hw struct 1978 * @seid: vsi number 1979 * @set: set multicast promiscuous enable/disable 1980 * @cmd_details: pointer to command details structure or NULL 1981 **/ 1982i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 1983 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 1984{ 1985 struct i40e_aq_desc desc; 1986 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1987 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1988 i40e_status status; 1989 u16 flags = 0; 1990 1991 i40e_fill_default_direct_cmd_desc(&desc, 1992 i40e_aqc_opc_set_vsi_promiscuous_modes); 1993 1994 if (set) 1995 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1996 1997 cmd->promiscuous_flags = cpu_to_le16(flags); 1998 1999 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2000 2001 cmd->seid = cpu_to_le16(seid); 2002 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2003 2004 return status; 2005} 2006 2007/** 2008 * i40e_aq_set_vsi_broadcast 2009 * @hw: pointer to the hw struct 2010 * @seid: vsi number 2011 * @set_filter: true to set filter, false to clear filter 2012 * @cmd_details: pointer to command details structure or NULL 2013 * 2014 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2015 **/ 2016i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2017 u16 seid, bool set_filter, 2018 struct i40e_asq_cmd_details *cmd_details) 2019{ 2020 struct i40e_aq_desc desc; 2021 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2022 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2023 i40e_status status; 2024 2025 i40e_fill_default_direct_cmd_desc(&desc, 2026 i40e_aqc_opc_set_vsi_promiscuous_modes); 2027 2028 if (set_filter) 2029 cmd->promiscuous_flags 2030 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2031 else 2032 cmd->promiscuous_flags 2033 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2034 2035 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2036 cmd->seid = cpu_to_le16(seid); 2037 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2038 2039 return status; 2040} 2041 2042/** 2043 * i40e_get_vsi_params - get VSI configuration info 2044 * @hw: pointer to the hw struct 2045 * @vsi_ctx: pointer to a vsi context struct 2046 * @cmd_details: pointer to command details structure or NULL 2047 **/ 2048i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 2049 struct i40e_vsi_context *vsi_ctx, 2050 struct i40e_asq_cmd_details *cmd_details) 2051{ 2052 struct i40e_aq_desc desc; 2053 struct i40e_aqc_add_get_update_vsi *cmd = 2054 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2055 struct i40e_aqc_add_get_update_vsi_completion *resp = 2056 (struct i40e_aqc_add_get_update_vsi_completion *) 2057 &desc.params.raw; 2058 i40e_status status; 2059 2060 i40e_fill_default_direct_cmd_desc(&desc, 2061 i40e_aqc_opc_get_vsi_parameters); 2062 2063 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2064 2065 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2066 2067 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2068 sizeof(vsi_ctx->info), NULL); 2069 2070 if (status) 2071 goto aq_get_vsi_params_exit; 2072 2073 vsi_ctx->seid = le16_to_cpu(resp->seid); 2074 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2075 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2076 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2077 2078aq_get_vsi_params_exit: 2079 return status; 2080} 2081 2082/** 2083 * i40e_aq_update_vsi_params 2084 * @hw: pointer to the hw struct 2085 * @vsi_ctx: pointer to a vsi context struct 2086 * @cmd_details: pointer to command details structure or NULL 2087 * 2088 * Update a VSI context. 2089 **/ 2090i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 2091 struct i40e_vsi_context *vsi_ctx, 2092 struct i40e_asq_cmd_details *cmd_details) 2093{ 2094 struct i40e_aq_desc desc; 2095 struct i40e_aqc_add_get_update_vsi *cmd = 2096 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2097 i40e_status status; 2098 2099 i40e_fill_default_direct_cmd_desc(&desc, 2100 i40e_aqc_opc_update_vsi_parameters); 2101 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2102 2103 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2104 2105 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2106 sizeof(vsi_ctx->info), cmd_details); 2107 2108 return status; 2109} 2110 2111/** 2112 * i40e_aq_get_switch_config 2113 * @hw: pointer to the hardware structure 2114 * @buf: pointer to the result buffer 2115 * @buf_size: length of input buffer 2116 * @start_seid: seid to start for the report, 0 == beginning 2117 * @cmd_details: pointer to command details structure or NULL 2118 * 2119 * Fill the buf with switch configuration returned from AdminQ command 2120 **/ 2121i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 2122 struct i40e_aqc_get_switch_config_resp *buf, 2123 u16 buf_size, u16 *start_seid, 2124 struct i40e_asq_cmd_details *cmd_details) 2125{ 2126 struct i40e_aq_desc desc; 2127 struct i40e_aqc_switch_seid *scfg = 2128 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2129 i40e_status status; 2130 2131 i40e_fill_default_direct_cmd_desc(&desc, 2132 i40e_aqc_opc_get_switch_config); 2133 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2134 if (buf_size > I40E_AQ_LARGE_BUF) 2135 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2136 scfg->seid = cpu_to_le16(*start_seid); 2137 2138 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2139 *start_seid = le16_to_cpu(scfg->seid); 2140 2141 return status; 2142} 2143 2144/** 2145 * i40e_aq_get_firmware_version 2146 * @hw: pointer to the hw struct 2147 * @fw_major_version: firmware major version 2148 * @fw_minor_version: firmware minor version 2149 * @fw_build: firmware build number 2150 * @api_major_version: major queue version 2151 * @api_minor_version: minor queue version 2152 * @cmd_details: pointer to command details structure or NULL 2153 * 2154 * Get the firmware version from the admin queue commands 2155 **/ 2156i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 2157 u16 *fw_major_version, u16 *fw_minor_version, 2158 u32 *fw_build, 2159 u16 *api_major_version, u16 *api_minor_version, 2160 struct i40e_asq_cmd_details *cmd_details) 2161{ 2162 struct i40e_aq_desc desc; 2163 struct i40e_aqc_get_version *resp = 2164 (struct i40e_aqc_get_version *)&desc.params.raw; 2165 i40e_status status; 2166 2167 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2168 2169 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2170 2171 if (!status) { 2172 if (fw_major_version) 2173 *fw_major_version = le16_to_cpu(resp->fw_major); 2174 if (fw_minor_version) 2175 *fw_minor_version = le16_to_cpu(resp->fw_minor); 2176 if (fw_build) 2177 *fw_build = le32_to_cpu(resp->fw_build); 2178 if (api_major_version) 2179 *api_major_version = le16_to_cpu(resp->api_major); 2180 if (api_minor_version) 2181 *api_minor_version = le16_to_cpu(resp->api_minor); 2182 } 2183 2184 return status; 2185} 2186 2187/** 2188 * i40e_aq_send_driver_version 2189 * @hw: pointer to the hw struct 2190 * @dv: driver's major, minor version 2191 * @cmd_details: pointer to command details structure or NULL 2192 * 2193 * Send the driver version to the firmware 2194 **/ 2195i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 2196 struct i40e_driver_version *dv, 2197 struct i40e_asq_cmd_details *cmd_details) 2198{ 2199 struct i40e_aq_desc desc; 2200 struct i40e_aqc_driver_version *cmd = 2201 (struct i40e_aqc_driver_version *)&desc.params.raw; 2202 i40e_status status; 2203 u16 len; 2204 2205 if (dv == NULL) 2206 return I40E_ERR_PARAM; 2207 2208 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2209 2210 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2211 cmd->driver_major_ver = dv->major_version; 2212 cmd->driver_minor_ver = dv->minor_version; 2213 cmd->driver_build_ver = dv->build_version; 2214 cmd->driver_subbuild_ver = dv->subbuild_version; 2215 2216 len = 0; 2217 while (len < sizeof(dv->driver_string) && 2218 (dv->driver_string[len] < 0x80) && 2219 dv->driver_string[len]) 2220 len++; 2221 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2222 len, cmd_details); 2223 2224 return status; 2225} 2226 2227/** 2228 * i40e_get_link_status - get status of the HW network link 2229 * @hw: pointer to the hw struct 2230 * @link_up: pointer to bool (true/false = linkup/linkdown) 2231 * 2232 * Variable link_up true if link is up, false if link is down. 2233 * The variable link_up is invalid if returned value of status != 0 2234 * 2235 * Side effect: LinkStatusEvent reporting becomes enabled 2236 **/ 2237i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2238{ 2239 i40e_status status = 0; 2240 2241 if (hw->phy.get_link_info) { 2242 status = i40e_update_link_info(hw); 2243 2244 if (status) 2245 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2246 status); 2247 } 2248 2249 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2250 2251 return status; 2252} 2253 2254/** 2255 * i40e_updatelink_status - update status of the HW network link 2256 * @hw: pointer to the hw struct 2257 **/ 2258i40e_status i40e_update_link_info(struct i40e_hw *hw) 2259{ 2260 struct i40e_aq_get_phy_abilities_resp abilities; 2261 i40e_status status = 0; 2262 2263 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2264 if (status) 2265 return status; 2266 2267 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) { 2268 status = i40e_aq_get_phy_capabilities(hw, false, false, 2269 &abilities, NULL); 2270 if (status) 2271 return status; 2272 2273 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2274 sizeof(hw->phy.link_info.module_type)); 2275 } 2276 2277 return status; 2278} 2279 2280/** 2281 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2282 * @hw: pointer to the hw struct 2283 * @uplink_seid: the MAC or other gizmo SEID 2284 * @downlink_seid: the VSI SEID 2285 * @enabled_tc: bitmap of TCs to be enabled 2286 * @default_port: true for default port VSI, false for control port 2287 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support 2288 * @veb_seid: pointer to where to put the resulting VEB SEID 2289 * @cmd_details: pointer to command details structure or NULL 2290 * 2291 * This asks the FW to add a VEB between the uplink and downlink 2292 * elements. If the uplink SEID is 0, this will be a floating VEB. 2293 **/ 2294i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2295 u16 downlink_seid, u8 enabled_tc, 2296 bool default_port, bool enable_l2_filtering, 2297 u16 *veb_seid, 2298 struct i40e_asq_cmd_details *cmd_details) 2299{ 2300 struct i40e_aq_desc desc; 2301 struct i40e_aqc_add_veb *cmd = 2302 (struct i40e_aqc_add_veb *)&desc.params.raw; 2303 struct i40e_aqc_add_veb_completion *resp = 2304 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2305 i40e_status status; 2306 u16 veb_flags = 0; 2307 2308 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2309 if (!!uplink_seid != !!downlink_seid) 2310 return I40E_ERR_PARAM; 2311 2312 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2313 2314 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2315 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2316 cmd->enable_tcs = enabled_tc; 2317 if (!uplink_seid) 2318 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2319 if (default_port) 2320 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2321 else 2322 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2323 2324 if (enable_l2_filtering) 2325 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER; 2326 2327 cmd->veb_flags = cpu_to_le16(veb_flags); 2328 2329 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2330 2331 if (!status && veb_seid) 2332 *veb_seid = le16_to_cpu(resp->veb_seid); 2333 2334 return status; 2335} 2336 2337/** 2338 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2339 * @hw: pointer to the hw struct 2340 * @veb_seid: the SEID of the VEB to query 2341 * @switch_id: the uplink switch id 2342 * @floating: set to true if the VEB is floating 2343 * @statistic_index: index of the stats counter block for this VEB 2344 * @vebs_used: number of VEB's used by function 2345 * @vebs_free: total VEB's not reserved by any function 2346 * @cmd_details: pointer to command details structure or NULL 2347 * 2348 * This retrieves the parameters for a particular VEB, specified by 2349 * uplink_seid, and returns them to the caller. 2350 **/ 2351i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2352 u16 veb_seid, u16 *switch_id, 2353 bool *floating, u16 *statistic_index, 2354 u16 *vebs_used, u16 *vebs_free, 2355 struct i40e_asq_cmd_details *cmd_details) 2356{ 2357 struct i40e_aq_desc desc; 2358 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2359 (struct i40e_aqc_get_veb_parameters_completion *) 2360 &desc.params.raw; 2361 i40e_status status; 2362 2363 if (veb_seid == 0) 2364 return I40E_ERR_PARAM; 2365 2366 i40e_fill_default_direct_cmd_desc(&desc, 2367 i40e_aqc_opc_get_veb_parameters); 2368 cmd_resp->seid = cpu_to_le16(veb_seid); 2369 2370 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2371 if (status) 2372 goto get_veb_exit; 2373 2374 if (switch_id) 2375 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2376 if (statistic_index) 2377 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2378 if (vebs_used) 2379 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2380 if (vebs_free) 2381 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2382 if (floating) { 2383 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2384 2385 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2386 *floating = true; 2387 else 2388 *floating = false; 2389 } 2390 2391get_veb_exit: 2392 return status; 2393} 2394 2395/** 2396 * i40e_aq_add_macvlan 2397 * @hw: pointer to the hw struct 2398 * @seid: VSI for the mac address 2399 * @mv_list: list of macvlans to be added 2400 * @count: length of the list 2401 * @cmd_details: pointer to command details structure or NULL 2402 * 2403 * Add MAC/VLAN addresses to the HW filtering 2404 **/ 2405i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2406 struct i40e_aqc_add_macvlan_element_data *mv_list, 2407 u16 count, struct i40e_asq_cmd_details *cmd_details) 2408{ 2409 struct i40e_aq_desc desc; 2410 struct i40e_aqc_macvlan *cmd = 2411 (struct i40e_aqc_macvlan *)&desc.params.raw; 2412 i40e_status status; 2413 u16 buf_size; 2414 2415 if (count == 0 || !mv_list || !hw) 2416 return I40E_ERR_PARAM; 2417 2418 buf_size = count * sizeof(*mv_list); 2419 2420 /* prep the rest of the request */ 2421 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2422 cmd->num_addresses = cpu_to_le16(count); 2423 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2424 cmd->seid[1] = 0; 2425 cmd->seid[2] = 0; 2426 2427 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2428 if (buf_size > I40E_AQ_LARGE_BUF) 2429 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2430 2431 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2432 cmd_details); 2433 2434 return status; 2435} 2436 2437/** 2438 * i40e_aq_remove_macvlan 2439 * @hw: pointer to the hw struct 2440 * @seid: VSI for the mac address 2441 * @mv_list: list of macvlans to be removed 2442 * @count: length of the list 2443 * @cmd_details: pointer to command details structure or NULL 2444 * 2445 * Remove MAC/VLAN addresses from the HW filtering 2446 **/ 2447i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2448 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2449 u16 count, struct i40e_asq_cmd_details *cmd_details) 2450{ 2451 struct i40e_aq_desc desc; 2452 struct i40e_aqc_macvlan *cmd = 2453 (struct i40e_aqc_macvlan *)&desc.params.raw; 2454 i40e_status status; 2455 u16 buf_size; 2456 2457 if (count == 0 || !mv_list || !hw) 2458 return I40E_ERR_PARAM; 2459 2460 buf_size = count * sizeof(*mv_list); 2461 2462 /* prep the rest of the request */ 2463 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2464 cmd->num_addresses = cpu_to_le16(count); 2465 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2466 cmd->seid[1] = 0; 2467 cmd->seid[2] = 0; 2468 2469 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2470 if (buf_size > I40E_AQ_LARGE_BUF) 2471 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2472 2473 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2474 cmd_details); 2475 2476 return status; 2477} 2478 2479/** 2480 * i40e_aq_send_msg_to_vf 2481 * @hw: pointer to the hardware structure 2482 * @vfid: VF id to send msg 2483 * @v_opcode: opcodes for VF-PF communication 2484 * @v_retval: return error code 2485 * @msg: pointer to the msg buffer 2486 * @msglen: msg length 2487 * @cmd_details: pointer to command details 2488 * 2489 * send msg to vf 2490 **/ 2491i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2492 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2493 struct i40e_asq_cmd_details *cmd_details) 2494{ 2495 struct i40e_aq_desc desc; 2496 struct i40e_aqc_pf_vf_message *cmd = 2497 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2498 i40e_status status; 2499 2500 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2501 cmd->id = cpu_to_le32(vfid); 2502 desc.cookie_high = cpu_to_le32(v_opcode); 2503 desc.cookie_low = cpu_to_le32(v_retval); 2504 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2505 if (msglen) { 2506 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2507 I40E_AQ_FLAG_RD)); 2508 if (msglen > I40E_AQ_LARGE_BUF) 2509 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2510 desc.datalen = cpu_to_le16(msglen); 2511 } 2512 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2513 2514 return status; 2515} 2516 2517/** 2518 * i40e_aq_debug_read_register 2519 * @hw: pointer to the hw struct 2520 * @reg_addr: register address 2521 * @reg_val: register value 2522 * @cmd_details: pointer to command details structure or NULL 2523 * 2524 * Read the register using the admin queue commands 2525 **/ 2526i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, 2527 u32 reg_addr, u64 *reg_val, 2528 struct i40e_asq_cmd_details *cmd_details) 2529{ 2530 struct i40e_aq_desc desc; 2531 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2532 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2533 i40e_status status; 2534 2535 if (reg_val == NULL) 2536 return I40E_ERR_PARAM; 2537 2538 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2539 2540 cmd_resp->address = cpu_to_le32(reg_addr); 2541 2542 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2543 2544 if (!status) { 2545 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2546 (u64)le32_to_cpu(cmd_resp->value_low); 2547 } 2548 2549 return status; 2550} 2551 2552/** 2553 * i40e_aq_debug_write_register 2554 * @hw: pointer to the hw struct 2555 * @reg_addr: register address 2556 * @reg_val: register value 2557 * @cmd_details: pointer to command details structure or NULL 2558 * 2559 * Write to a register using the admin queue commands 2560 **/ 2561i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 2562 u32 reg_addr, u64 reg_val, 2563 struct i40e_asq_cmd_details *cmd_details) 2564{ 2565 struct i40e_aq_desc desc; 2566 struct i40e_aqc_debug_reg_read_write *cmd = 2567 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2568 i40e_status status; 2569 2570 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2571 2572 cmd->address = cpu_to_le32(reg_addr); 2573 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2574 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2575 2576 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2577 2578 return status; 2579} 2580 2581/** 2582 * i40e_aq_set_hmc_resource_profile 2583 * @hw: pointer to the hw struct 2584 * @profile: type of profile the HMC is to be set as 2585 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 2586 * @cmd_details: pointer to command details structure or NULL 2587 * 2588 * set the HMC profile of the device. 2589 **/ 2590i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw, 2591 enum i40e_aq_hmc_profile profile, 2592 u8 pe_vf_enabled_count, 2593 struct i40e_asq_cmd_details *cmd_details) 2594{ 2595 struct i40e_aq_desc desc; 2596 struct i40e_aq_get_set_hmc_resource_profile *cmd = 2597 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 2598 i40e_status status; 2599 2600 i40e_fill_default_direct_cmd_desc(&desc, 2601 i40e_aqc_opc_set_hmc_resource_profile); 2602 2603 cmd->pm_profile = (u8)profile; 2604 cmd->pe_vf_enabled = pe_vf_enabled_count; 2605 2606 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2607 2608 return status; 2609} 2610 2611/** 2612 * i40e_aq_request_resource 2613 * @hw: pointer to the hw struct 2614 * @resource: resource id 2615 * @access: access type 2616 * @sdp_number: resource number 2617 * @timeout: the maximum time in ms that the driver may hold the resource 2618 * @cmd_details: pointer to command details structure or NULL 2619 * 2620 * requests common resource using the admin queue commands 2621 **/ 2622i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 2623 enum i40e_aq_resources_ids resource, 2624 enum i40e_aq_resource_access_type access, 2625 u8 sdp_number, u64 *timeout, 2626 struct i40e_asq_cmd_details *cmd_details) 2627{ 2628 struct i40e_aq_desc desc; 2629 struct i40e_aqc_request_resource *cmd_resp = 2630 (struct i40e_aqc_request_resource *)&desc.params.raw; 2631 i40e_status status; 2632 2633 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2634 2635 cmd_resp->resource_id = cpu_to_le16(resource); 2636 cmd_resp->access_type = cpu_to_le16(access); 2637 cmd_resp->resource_number = cpu_to_le32(sdp_number); 2638 2639 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2640 /* The completion specifies the maximum time in ms that the driver 2641 * may hold the resource in the Timeout field. 2642 * If the resource is held by someone else, the command completes with 2643 * busy return value and the timeout field indicates the maximum time 2644 * the current owner of the resource has to free it. 2645 */ 2646 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 2647 *timeout = le32_to_cpu(cmd_resp->timeout); 2648 2649 return status; 2650} 2651 2652/** 2653 * i40e_aq_release_resource 2654 * @hw: pointer to the hw struct 2655 * @resource: resource id 2656 * @sdp_number: resource number 2657 * @cmd_details: pointer to command details structure or NULL 2658 * 2659 * release common resource using the admin queue commands 2660 **/ 2661i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 2662 enum i40e_aq_resources_ids resource, 2663 u8 sdp_number, 2664 struct i40e_asq_cmd_details *cmd_details) 2665{ 2666 struct i40e_aq_desc desc; 2667 struct i40e_aqc_request_resource *cmd = 2668 (struct i40e_aqc_request_resource *)&desc.params.raw; 2669 i40e_status status; 2670 2671 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2672 2673 cmd->resource_id = cpu_to_le16(resource); 2674 cmd->resource_number = cpu_to_le32(sdp_number); 2675 2676 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2677 2678 return status; 2679} 2680 2681/** 2682 * i40e_aq_read_nvm 2683 * @hw: pointer to the hw struct 2684 * @module_pointer: module pointer location in words from the NVM beginning 2685 * @offset: byte offset from the module beginning 2686 * @length: length of the section to be read (in bytes from the offset) 2687 * @data: command buffer (size [bytes] = length) 2688 * @last_command: tells if this is the last command in a series 2689 * @cmd_details: pointer to command details structure or NULL 2690 * 2691 * Read the NVM using the admin queue commands 2692 **/ 2693i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 2694 u32 offset, u16 length, void *data, 2695 bool last_command, 2696 struct i40e_asq_cmd_details *cmd_details) 2697{ 2698 struct i40e_aq_desc desc; 2699 struct i40e_aqc_nvm_update *cmd = 2700 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2701 i40e_status status; 2702 2703 /* In offset the highest byte must be zeroed. */ 2704 if (offset & 0xFF000000) { 2705 status = I40E_ERR_PARAM; 2706 goto i40e_aq_read_nvm_exit; 2707 } 2708 2709 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2710 2711 /* If this is the last command in a series, set the proper flag. */ 2712 if (last_command) 2713 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2714 cmd->module_pointer = module_pointer; 2715 cmd->offset = cpu_to_le32(offset); 2716 cmd->length = cpu_to_le16(length); 2717 2718 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2719 if (length > I40E_AQ_LARGE_BUF) 2720 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2721 2722 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2723 2724i40e_aq_read_nvm_exit: 2725 return status; 2726} 2727 2728/** 2729 * i40e_aq_erase_nvm 2730 * @hw: pointer to the hw struct 2731 * @module_pointer: module pointer location in words from the NVM beginning 2732 * @offset: offset in the module (expressed in 4 KB from module's beginning) 2733 * @length: length of the section to be erased (expressed in 4 KB) 2734 * @last_command: tells if this is the last command in a series 2735 * @cmd_details: pointer to command details structure or NULL 2736 * 2737 * Erase the NVM sector using the admin queue commands 2738 **/ 2739i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 2740 u32 offset, u16 length, bool last_command, 2741 struct i40e_asq_cmd_details *cmd_details) 2742{ 2743 struct i40e_aq_desc desc; 2744 struct i40e_aqc_nvm_update *cmd = 2745 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2746 i40e_status status; 2747 2748 /* In offset the highest byte must be zeroed. */ 2749 if (offset & 0xFF000000) { 2750 status = I40E_ERR_PARAM; 2751 goto i40e_aq_erase_nvm_exit; 2752 } 2753 2754 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 2755 2756 /* If this is the last command in a series, set the proper flag. */ 2757 if (last_command) 2758 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2759 cmd->module_pointer = module_pointer; 2760 cmd->offset = cpu_to_le32(offset); 2761 cmd->length = cpu_to_le16(length); 2762 2763 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2764 2765i40e_aq_erase_nvm_exit: 2766 return status; 2767} 2768 2769#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01 2770#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02 2771#define I40E_DEV_FUNC_CAP_NPAR 0x03 2772#define I40E_DEV_FUNC_CAP_OS2BMC 0x04 2773#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05 2774#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12 2775#define I40E_DEV_FUNC_CAP_VF 0x13 2776#define I40E_DEV_FUNC_CAP_VMDQ 0x14 2777#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15 2778#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16 2779#define I40E_DEV_FUNC_CAP_VSI 0x17 2780#define I40E_DEV_FUNC_CAP_DCB 0x18 2781#define I40E_DEV_FUNC_CAP_FCOE 0x21 2782#define I40E_DEV_FUNC_CAP_ISCSI 0x22 2783#define I40E_DEV_FUNC_CAP_RSS 0x40 2784#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41 2785#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42 2786#define I40E_DEV_FUNC_CAP_MSIX 0x43 2787#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44 2788#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45 2789#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46 2790#define I40E_DEV_FUNC_CAP_FLEX10 0xF1 2791#define I40E_DEV_FUNC_CAP_CEM 0xF2 2792#define I40E_DEV_FUNC_CAP_IWARP 0x51 2793#define I40E_DEV_FUNC_CAP_LED 0x61 2794#define I40E_DEV_FUNC_CAP_SDP 0x62 2795#define I40E_DEV_FUNC_CAP_MDIO 0x63 2796#define I40E_DEV_FUNC_CAP_WR_CSR_PROT 0x64 2797 2798/** 2799 * i40e_parse_discover_capabilities 2800 * @hw: pointer to the hw struct 2801 * @buff: pointer to a buffer containing device/function capability records 2802 * @cap_count: number of capability records in the list 2803 * @list_type_opc: type of capabilities list to parse 2804 * 2805 * Parse the device/function capabilities list. 2806 **/ 2807static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 2808 u32 cap_count, 2809 enum i40e_admin_queue_opc list_type_opc) 2810{ 2811 struct i40e_aqc_list_capabilities_element_resp *cap; 2812 u32 valid_functions, num_functions; 2813 u32 number, logical_id, phys_id; 2814 struct i40e_hw_capabilities *p; 2815 u8 major_rev; 2816 u32 i = 0; 2817 u16 id; 2818 2819 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 2820 2821 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 2822 p = &hw->dev_caps; 2823 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 2824 p = &hw->func_caps; 2825 else 2826 return; 2827 2828 for (i = 0; i < cap_count; i++, cap++) { 2829 id = le16_to_cpu(cap->id); 2830 number = le32_to_cpu(cap->number); 2831 logical_id = le32_to_cpu(cap->logical_id); 2832 phys_id = le32_to_cpu(cap->phys_id); 2833 major_rev = cap->major_rev; 2834 2835 switch (id) { 2836 case I40E_DEV_FUNC_CAP_SWITCH_MODE: 2837 p->switch_mode = number; 2838 break; 2839 case I40E_DEV_FUNC_CAP_MGMT_MODE: 2840 p->management_mode = number; 2841 break; 2842 case I40E_DEV_FUNC_CAP_NPAR: 2843 p->npar_enable = number; 2844 break; 2845 case I40E_DEV_FUNC_CAP_OS2BMC: 2846 p->os2bmc = number; 2847 break; 2848 case I40E_DEV_FUNC_CAP_VALID_FUNC: 2849 p->valid_functions = number; 2850 break; 2851 case I40E_DEV_FUNC_CAP_SRIOV_1_1: 2852 if (number == 1) 2853 p->sr_iov_1_1 = true; 2854 break; 2855 case I40E_DEV_FUNC_CAP_VF: 2856 p->num_vfs = number; 2857 p->vf_base_id = logical_id; 2858 break; 2859 case I40E_DEV_FUNC_CAP_VMDQ: 2860 if (number == 1) 2861 p->vmdq = true; 2862 break; 2863 case I40E_DEV_FUNC_CAP_802_1_QBG: 2864 if (number == 1) 2865 p->evb_802_1_qbg = true; 2866 break; 2867 case I40E_DEV_FUNC_CAP_802_1_QBH: 2868 if (number == 1) 2869 p->evb_802_1_qbh = true; 2870 break; 2871 case I40E_DEV_FUNC_CAP_VSI: 2872 p->num_vsis = number; 2873 break; 2874 case I40E_DEV_FUNC_CAP_DCB: 2875 if (number == 1) { 2876 p->dcb = true; 2877 p->enabled_tcmap = logical_id; 2878 p->maxtc = phys_id; 2879 } 2880 break; 2881 case I40E_DEV_FUNC_CAP_FCOE: 2882 if (number == 1) 2883 p->fcoe = true; 2884 break; 2885 case I40E_DEV_FUNC_CAP_ISCSI: 2886 if (number == 1) 2887 p->iscsi = true; 2888 break; 2889 case I40E_DEV_FUNC_CAP_RSS: 2890 p->rss = true; 2891 p->rss_table_size = number; 2892 p->rss_table_entry_width = logical_id; 2893 break; 2894 case I40E_DEV_FUNC_CAP_RX_QUEUES: 2895 p->num_rx_qp = number; 2896 p->base_queue = phys_id; 2897 break; 2898 case I40E_DEV_FUNC_CAP_TX_QUEUES: 2899 p->num_tx_qp = number; 2900 p->base_queue = phys_id; 2901 break; 2902 case I40E_DEV_FUNC_CAP_MSIX: 2903 p->num_msix_vectors = number; 2904 break; 2905 case I40E_DEV_FUNC_CAP_MSIX_VF: 2906 p->num_msix_vectors_vf = number; 2907 break; 2908 case I40E_DEV_FUNC_CAP_FLEX10: 2909 if (major_rev == 1) { 2910 if (number == 1) { 2911 p->flex10_enable = true; 2912 p->flex10_capable = true; 2913 } 2914 } else { 2915 /* Capability revision >= 2 */ 2916 if (number & 1) 2917 p->flex10_enable = true; 2918 if (number & 2) 2919 p->flex10_capable = true; 2920 } 2921 p->flex10_mode = logical_id; 2922 p->flex10_status = phys_id; 2923 break; 2924 case I40E_DEV_FUNC_CAP_CEM: 2925 if (number == 1) 2926 p->mgmt_cem = true; 2927 break; 2928 case I40E_DEV_FUNC_CAP_IWARP: 2929 if (number == 1) 2930 p->iwarp = true; 2931 break; 2932 case I40E_DEV_FUNC_CAP_LED: 2933 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2934 p->led[phys_id] = true; 2935 break; 2936 case I40E_DEV_FUNC_CAP_SDP: 2937 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2938 p->sdp[phys_id] = true; 2939 break; 2940 case I40E_DEV_FUNC_CAP_MDIO: 2941 if (number == 1) { 2942 p->mdio_port_num = phys_id; 2943 p->mdio_port_mode = logical_id; 2944 } 2945 break; 2946 case I40E_DEV_FUNC_CAP_IEEE_1588: 2947 if (number == 1) 2948 p->ieee_1588 = true; 2949 break; 2950 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR: 2951 p->fd = true; 2952 p->fd_filters_guaranteed = number; 2953 p->fd_filters_best_effort = logical_id; 2954 break; 2955 case I40E_DEV_FUNC_CAP_WR_CSR_PROT: 2956 p->wr_csr_prot = (u64)number; 2957 p->wr_csr_prot |= (u64)logical_id << 32; 2958 break; 2959 default: 2960 break; 2961 } 2962 } 2963 2964 if (p->fcoe) 2965 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 2966 2967 /* Software override ensuring FCoE is disabled if npar or mfp 2968 * mode because it is not supported in these modes. 2969 */ 2970 if (p->npar_enable || p->flex10_enable) 2971 p->fcoe = false; 2972 2973 /* count the enabled ports (aka the "not disabled" ports) */ 2974 hw->num_ports = 0; 2975 for (i = 0; i < 4; i++) { 2976 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 2977 u64 port_cfg = 0; 2978 2979 /* use AQ read to get the physical register offset instead 2980 * of the port relative offset 2981 */ 2982 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 2983 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 2984 hw->num_ports++; 2985 } 2986 2987 valid_functions = p->valid_functions; 2988 num_functions = 0; 2989 while (valid_functions) { 2990 if (valid_functions & 1) 2991 num_functions++; 2992 valid_functions >>= 1; 2993 } 2994 2995 /* partition id is 1-based, and functions are evenly spread 2996 * across the ports as partitions 2997 */ 2998 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 2999 hw->num_partitions = num_functions / hw->num_ports; 3000 3001 /* additional HW specific goodies that might 3002 * someday be HW version specific 3003 */ 3004 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3005} 3006 3007/** 3008 * i40e_aq_discover_capabilities 3009 * @hw: pointer to the hw struct 3010 * @buff: a virtual buffer to hold the capabilities 3011 * @buff_size: Size of the virtual buffer 3012 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3013 * @list_type_opc: capabilities type to discover - pass in the command opcode 3014 * @cmd_details: pointer to command details structure or NULL 3015 * 3016 * Get the device capabilities descriptions from the firmware 3017 **/ 3018i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 3019 void *buff, u16 buff_size, u16 *data_size, 3020 enum i40e_admin_queue_opc list_type_opc, 3021 struct i40e_asq_cmd_details *cmd_details) 3022{ 3023 struct i40e_aqc_list_capabilites *cmd; 3024 struct i40e_aq_desc desc; 3025 i40e_status status = 0; 3026 3027 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3028 3029 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3030 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3031 status = I40E_ERR_PARAM; 3032 goto exit; 3033 } 3034 3035 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3036 3037 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3038 if (buff_size > I40E_AQ_LARGE_BUF) 3039 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3040 3041 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3042 *data_size = le16_to_cpu(desc.datalen); 3043 3044 if (status) 3045 goto exit; 3046 3047 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 3048 list_type_opc); 3049 3050exit: 3051 return status; 3052} 3053 3054/** 3055 * i40e_aq_update_nvm 3056 * @hw: pointer to the hw struct 3057 * @module_pointer: module pointer location in words from the NVM beginning 3058 * @offset: byte offset from the module beginning 3059 * @length: length of the section to be written (in bytes from the offset) 3060 * @data: command buffer (size [bytes] = length) 3061 * @last_command: tells if this is the last command in a series 3062 * @cmd_details: pointer to command details structure or NULL 3063 * 3064 * Update the NVM using the admin queue commands 3065 **/ 3066i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3067 u32 offset, u16 length, void *data, 3068 bool last_command, 3069 struct i40e_asq_cmd_details *cmd_details) 3070{ 3071 struct i40e_aq_desc desc; 3072 struct i40e_aqc_nvm_update *cmd = 3073 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3074 i40e_status status; 3075 3076 /* In offset the highest byte must be zeroed. */ 3077 if (offset & 0xFF000000) { 3078 status = I40E_ERR_PARAM; 3079 goto i40e_aq_update_nvm_exit; 3080 } 3081 3082 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3083 3084 /* If this is the last command in a series, set the proper flag. */ 3085 if (last_command) 3086 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3087 cmd->module_pointer = module_pointer; 3088 cmd->offset = cpu_to_le32(offset); 3089 cmd->length = cpu_to_le16(length); 3090 3091 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3092 if (length > I40E_AQ_LARGE_BUF) 3093 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3094 3095 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3096 3097i40e_aq_update_nvm_exit: 3098 return status; 3099} 3100 3101/** 3102 * i40e_aq_get_lldp_mib 3103 * @hw: pointer to the hw struct 3104 * @bridge_type: type of bridge requested 3105 * @mib_type: Local, Remote or both Local and Remote MIBs 3106 * @buff: pointer to a user supplied buffer to store the MIB block 3107 * @buff_size: size of the buffer (in bytes) 3108 * @local_len : length of the returned Local LLDP MIB 3109 * @remote_len: length of the returned Remote LLDP MIB 3110 * @cmd_details: pointer to command details structure or NULL 3111 * 3112 * Requests the complete LLDP MIB (entire packet). 3113 **/ 3114i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3115 u8 mib_type, void *buff, u16 buff_size, 3116 u16 *local_len, u16 *remote_len, 3117 struct i40e_asq_cmd_details *cmd_details) 3118{ 3119 struct i40e_aq_desc desc; 3120 struct i40e_aqc_lldp_get_mib *cmd = 3121 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3122 struct i40e_aqc_lldp_get_mib *resp = 3123 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3124 i40e_status status; 3125 3126 if (buff_size == 0 || !buff) 3127 return I40E_ERR_PARAM; 3128 3129 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3130 /* Indirect Command */ 3131 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3132 3133 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3134 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3135 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3136 3137 desc.datalen = cpu_to_le16(buff_size); 3138 3139 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3140 if (buff_size > I40E_AQ_LARGE_BUF) 3141 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3142 3143 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3144 if (!status) { 3145 if (local_len != NULL) 3146 *local_len = le16_to_cpu(resp->local_len); 3147 if (remote_len != NULL) 3148 *remote_len = le16_to_cpu(resp->remote_len); 3149 } 3150 3151 return status; 3152} 3153 3154/** 3155 * i40e_aq_cfg_lldp_mib_change_event 3156 * @hw: pointer to the hw struct 3157 * @enable_update: Enable or Disable event posting 3158 * @cmd_details: pointer to command details structure or NULL 3159 * 3160 * Enable or Disable posting of an event on ARQ when LLDP MIB 3161 * associated with the interface changes 3162 **/ 3163i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3164 bool enable_update, 3165 struct i40e_asq_cmd_details *cmd_details) 3166{ 3167 struct i40e_aq_desc desc; 3168 struct i40e_aqc_lldp_update_mib *cmd = 3169 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3170 i40e_status status; 3171 3172 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3173 3174 if (!enable_update) 3175 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3176 3177 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3178 3179 return status; 3180} 3181 3182/** 3183 * i40e_aq_stop_lldp 3184 * @hw: pointer to the hw struct 3185 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3186 * @cmd_details: pointer to command details structure or NULL 3187 * 3188 * Stop or Shutdown the embedded LLDP Agent 3189 **/ 3190i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3191 struct i40e_asq_cmd_details *cmd_details) 3192{ 3193 struct i40e_aq_desc desc; 3194 struct i40e_aqc_lldp_stop *cmd = 3195 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3196 i40e_status status; 3197 3198 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3199 3200 if (shutdown_agent) 3201 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3202 3203 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3204 3205 return status; 3206} 3207 3208/** 3209 * i40e_aq_start_lldp 3210 * @hw: pointer to the hw struct 3211 * @cmd_details: pointer to command details structure or NULL 3212 * 3213 * Start the embedded LLDP Agent on all ports. 3214 **/ 3215i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, 3216 struct i40e_asq_cmd_details *cmd_details) 3217{ 3218 struct i40e_aq_desc desc; 3219 struct i40e_aqc_lldp_start *cmd = 3220 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3221 i40e_status status; 3222 3223 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3224 3225 cmd->command = I40E_AQ_LLDP_AGENT_START; 3226 3227 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3228 3229 return status; 3230} 3231 3232/** 3233 * i40e_aq_get_cee_dcb_config 3234 * @hw: pointer to the hw struct 3235 * @buff: response buffer that stores CEE operational configuration 3236 * @buff_size: size of the buffer passed 3237 * @cmd_details: pointer to command details structure or NULL 3238 * 3239 * Get CEE DCBX mode operational configuration from firmware 3240 **/ 3241i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3242 void *buff, u16 buff_size, 3243 struct i40e_asq_cmd_details *cmd_details) 3244{ 3245 struct i40e_aq_desc desc; 3246 i40e_status status; 3247 3248 if (buff_size == 0 || !buff) 3249 return I40E_ERR_PARAM; 3250 3251 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3252 3253 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3254 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3255 cmd_details); 3256 3257 return status; 3258} 3259 3260/** 3261 * i40e_aq_add_udp_tunnel 3262 * @hw: pointer to the hw struct 3263 * @udp_port: the UDP port to add 3264 * @header_len: length of the tunneling header length in DWords 3265 * @protocol_index: protocol index type 3266 * @filter_index: pointer to filter index 3267 * @cmd_details: pointer to command details structure or NULL 3268 **/ 3269i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3270 u16 udp_port, u8 protocol_index, 3271 u8 *filter_index, 3272 struct i40e_asq_cmd_details *cmd_details) 3273{ 3274 struct i40e_aq_desc desc; 3275 struct i40e_aqc_add_udp_tunnel *cmd = 3276 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3277 struct i40e_aqc_del_udp_tunnel_completion *resp = 3278 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3279 i40e_status status; 3280 3281 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3282 3283 cmd->udp_port = cpu_to_le16(udp_port); 3284 cmd->protocol_type = protocol_index; 3285 3286 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3287 3288 if (!status && filter_index) 3289 *filter_index = resp->index; 3290 3291 return status; 3292} 3293 3294/** 3295 * i40e_aq_del_udp_tunnel 3296 * @hw: pointer to the hw struct 3297 * @index: filter index 3298 * @cmd_details: pointer to command details structure or NULL 3299 **/ 3300i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3301 struct i40e_asq_cmd_details *cmd_details) 3302{ 3303 struct i40e_aq_desc desc; 3304 struct i40e_aqc_remove_udp_tunnel *cmd = 3305 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3306 i40e_status status; 3307 3308 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3309 3310 cmd->index = index; 3311 3312 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3313 3314 return status; 3315} 3316 3317/** 3318 * i40e_aq_delete_element - Delete switch element 3319 * @hw: pointer to the hw struct 3320 * @seid: the SEID to delete from the switch 3321 * @cmd_details: pointer to command details structure or NULL 3322 * 3323 * This deletes a switch element from the switch. 3324 **/ 3325i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3326 struct i40e_asq_cmd_details *cmd_details) 3327{ 3328 struct i40e_aq_desc desc; 3329 struct i40e_aqc_switch_seid *cmd = 3330 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3331 i40e_status status; 3332 3333 if (seid == 0) 3334 return I40E_ERR_PARAM; 3335 3336 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3337 3338 cmd->seid = cpu_to_le16(seid); 3339 3340 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3341 3342 return status; 3343} 3344 3345/** 3346 * i40e_aq_dcb_updated - DCB Updated Command 3347 * @hw: pointer to the hw struct 3348 * @cmd_details: pointer to command details structure or NULL 3349 * 3350 * EMP will return when the shared RPB settings have been 3351 * recomputed and modified. The retval field in the descriptor 3352 * will be set to 0 when RPB is modified. 3353 **/ 3354i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 3355 struct i40e_asq_cmd_details *cmd_details) 3356{ 3357 struct i40e_aq_desc desc; 3358 i40e_status status; 3359 3360 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3361 3362 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3363 3364 return status; 3365} 3366 3367/** 3368 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3369 * @hw: pointer to the hw struct 3370 * @seid: seid for the physical port/switching component/vsi 3371 * @buff: Indirect buffer to hold data parameters and response 3372 * @buff_size: Indirect buffer size 3373 * @opcode: Tx scheduler AQ command opcode 3374 * @cmd_details: pointer to command details structure or NULL 3375 * 3376 * Generic command handler for Tx scheduler AQ commands 3377 **/ 3378static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3379 void *buff, u16 buff_size, 3380 enum i40e_admin_queue_opc opcode, 3381 struct i40e_asq_cmd_details *cmd_details) 3382{ 3383 struct i40e_aq_desc desc; 3384 struct i40e_aqc_tx_sched_ind *cmd = 3385 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3386 i40e_status status; 3387 bool cmd_param_flag = false; 3388 3389 switch (opcode) { 3390 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3391 case i40e_aqc_opc_configure_vsi_tc_bw: 3392 case i40e_aqc_opc_enable_switching_comp_ets: 3393 case i40e_aqc_opc_modify_switching_comp_ets: 3394 case i40e_aqc_opc_disable_switching_comp_ets: 3395 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3396 case i40e_aqc_opc_configure_switching_comp_bw_config: 3397 cmd_param_flag = true; 3398 break; 3399 case i40e_aqc_opc_query_vsi_bw_config: 3400 case i40e_aqc_opc_query_vsi_ets_sla_config: 3401 case i40e_aqc_opc_query_switching_comp_ets_config: 3402 case i40e_aqc_opc_query_port_ets_config: 3403 case i40e_aqc_opc_query_switching_comp_bw_config: 3404 cmd_param_flag = false; 3405 break; 3406 default: 3407 return I40E_ERR_PARAM; 3408 } 3409 3410 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3411 3412 /* Indirect command */ 3413 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3414 if (cmd_param_flag) 3415 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3416 if (buff_size > I40E_AQ_LARGE_BUF) 3417 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3418 3419 desc.datalen = cpu_to_le16(buff_size); 3420 3421 cmd->vsi_seid = cpu_to_le16(seid); 3422 3423 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3424 3425 return status; 3426} 3427 3428/** 3429 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3430 * @hw: pointer to the hw struct 3431 * @seid: VSI seid 3432 * @credit: BW limit credits (0 = disabled) 3433 * @max_credit: Max BW limit credits 3434 * @cmd_details: pointer to command details structure or NULL 3435 **/ 3436i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3437 u16 seid, u16 credit, u8 max_credit, 3438 struct i40e_asq_cmd_details *cmd_details) 3439{ 3440 struct i40e_aq_desc desc; 3441 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3442 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3443 i40e_status status; 3444 3445 i40e_fill_default_direct_cmd_desc(&desc, 3446 i40e_aqc_opc_configure_vsi_bw_limit); 3447 3448 cmd->vsi_seid = cpu_to_le16(seid); 3449 cmd->credit = cpu_to_le16(credit); 3450 cmd->max_credit = max_credit; 3451 3452 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3453 3454 return status; 3455} 3456 3457/** 3458 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3459 * @hw: pointer to the hw struct 3460 * @seid: VSI seid 3461 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3462 * @cmd_details: pointer to command details structure or NULL 3463 **/ 3464i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3465 u16 seid, 3466 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3467 struct i40e_asq_cmd_details *cmd_details) 3468{ 3469 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3470 i40e_aqc_opc_configure_vsi_tc_bw, 3471 cmd_details); 3472} 3473 3474/** 3475 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3476 * @hw: pointer to the hw struct 3477 * @seid: seid of the switching component connected to Physical Port 3478 * @ets_data: Buffer holding ETS parameters 3479 * @cmd_details: pointer to command details structure or NULL 3480 **/ 3481i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3482 u16 seid, 3483 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3484 enum i40e_admin_queue_opc opcode, 3485 struct i40e_asq_cmd_details *cmd_details) 3486{ 3487 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3488 sizeof(*ets_data), opcode, cmd_details); 3489} 3490 3491/** 3492 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3493 * @hw: pointer to the hw struct 3494 * @seid: seid of the switching component 3495 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3496 * @cmd_details: pointer to command details structure or NULL 3497 **/ 3498i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3499 u16 seid, 3500 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3501 struct i40e_asq_cmd_details *cmd_details) 3502{ 3503 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3504 i40e_aqc_opc_configure_switching_comp_bw_config, 3505 cmd_details); 3506} 3507 3508/** 3509 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3510 * @hw: pointer to the hw struct 3511 * @seid: seid of the VSI 3512 * @bw_data: Buffer to hold VSI BW configuration 3513 * @cmd_details: pointer to command details structure or NULL 3514 **/ 3515i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3516 u16 seid, 3517 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3518 struct i40e_asq_cmd_details *cmd_details) 3519{ 3520 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3521 i40e_aqc_opc_query_vsi_bw_config, 3522 cmd_details); 3523} 3524 3525/** 3526 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3527 * @hw: pointer to the hw struct 3528 * @seid: seid of the VSI 3529 * @bw_data: Buffer to hold VSI BW configuration per TC 3530 * @cmd_details: pointer to command details structure or NULL 3531 **/ 3532i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3533 u16 seid, 3534 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3535 struct i40e_asq_cmd_details *cmd_details) 3536{ 3537 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3538 i40e_aqc_opc_query_vsi_ets_sla_config, 3539 cmd_details); 3540} 3541 3542/** 3543 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3544 * @hw: pointer to the hw struct 3545 * @seid: seid of the switching component 3546 * @bw_data: Buffer to hold switching component's per TC BW config 3547 * @cmd_details: pointer to command details structure or NULL 3548 **/ 3549i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3550 u16 seid, 3551 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3552 struct i40e_asq_cmd_details *cmd_details) 3553{ 3554 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3555 i40e_aqc_opc_query_switching_comp_ets_config, 3556 cmd_details); 3557} 3558 3559/** 3560 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3561 * @hw: pointer to the hw struct 3562 * @seid: seid of the VSI or switching component connected to Physical Port 3563 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3564 * @cmd_details: pointer to command details structure or NULL 3565 **/ 3566i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3567 u16 seid, 3568 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3569 struct i40e_asq_cmd_details *cmd_details) 3570{ 3571 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3572 i40e_aqc_opc_query_port_ets_config, 3573 cmd_details); 3574} 3575 3576/** 3577 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3578 * @hw: pointer to the hw struct 3579 * @seid: seid of the switching component 3580 * @bw_data: Buffer to hold switching component's BW configuration 3581 * @cmd_details: pointer to command details structure or NULL 3582 **/ 3583i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3584 u16 seid, 3585 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3586 struct i40e_asq_cmd_details *cmd_details) 3587{ 3588 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3589 i40e_aqc_opc_query_switching_comp_bw_config, 3590 cmd_details); 3591} 3592 3593/** 3594 * i40e_validate_filter_settings 3595 * @hw: pointer to the hardware structure 3596 * @settings: Filter control settings 3597 * 3598 * Check and validate the filter control settings passed. 3599 * The function checks for the valid filter/context sizes being 3600 * passed for FCoE and PE. 3601 * 3602 * Returns 0 if the values passed are valid and within 3603 * range else returns an error. 3604 **/ 3605static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 3606 struct i40e_filter_control_settings *settings) 3607{ 3608 u32 fcoe_cntx_size, fcoe_filt_size; 3609 u32 pe_cntx_size, pe_filt_size; 3610 u32 fcoe_fmax; 3611 u32 val; 3612 3613 /* Validate FCoE settings passed */ 3614 switch (settings->fcoe_filt_num) { 3615 case I40E_HASH_FILTER_SIZE_1K: 3616 case I40E_HASH_FILTER_SIZE_2K: 3617 case I40E_HASH_FILTER_SIZE_4K: 3618 case I40E_HASH_FILTER_SIZE_8K: 3619 case I40E_HASH_FILTER_SIZE_16K: 3620 case I40E_HASH_FILTER_SIZE_32K: 3621 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3622 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 3623 break; 3624 default: 3625 return I40E_ERR_PARAM; 3626 } 3627 3628 switch (settings->fcoe_cntx_num) { 3629 case I40E_DMA_CNTX_SIZE_512: 3630 case I40E_DMA_CNTX_SIZE_1K: 3631 case I40E_DMA_CNTX_SIZE_2K: 3632 case I40E_DMA_CNTX_SIZE_4K: 3633 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3634 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 3635 break; 3636 default: 3637 return I40E_ERR_PARAM; 3638 } 3639 3640 /* Validate PE settings passed */ 3641 switch (settings->pe_filt_num) { 3642 case I40E_HASH_FILTER_SIZE_1K: 3643 case I40E_HASH_FILTER_SIZE_2K: 3644 case I40E_HASH_FILTER_SIZE_4K: 3645 case I40E_HASH_FILTER_SIZE_8K: 3646 case I40E_HASH_FILTER_SIZE_16K: 3647 case I40E_HASH_FILTER_SIZE_32K: 3648 case I40E_HASH_FILTER_SIZE_64K: 3649 case I40E_HASH_FILTER_SIZE_128K: 3650 case I40E_HASH_FILTER_SIZE_256K: 3651 case I40E_HASH_FILTER_SIZE_512K: 3652 case I40E_HASH_FILTER_SIZE_1M: 3653 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3654 pe_filt_size <<= (u32)settings->pe_filt_num; 3655 break; 3656 default: 3657 return I40E_ERR_PARAM; 3658 } 3659 3660 switch (settings->pe_cntx_num) { 3661 case I40E_DMA_CNTX_SIZE_512: 3662 case I40E_DMA_CNTX_SIZE_1K: 3663 case I40E_DMA_CNTX_SIZE_2K: 3664 case I40E_DMA_CNTX_SIZE_4K: 3665 case I40E_DMA_CNTX_SIZE_8K: 3666 case I40E_DMA_CNTX_SIZE_16K: 3667 case I40E_DMA_CNTX_SIZE_32K: 3668 case I40E_DMA_CNTX_SIZE_64K: 3669 case I40E_DMA_CNTX_SIZE_128K: 3670 case I40E_DMA_CNTX_SIZE_256K: 3671 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3672 pe_cntx_size <<= (u32)settings->pe_cntx_num; 3673 break; 3674 default: 3675 return I40E_ERR_PARAM; 3676 } 3677 3678 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 3679 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 3680 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 3681 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 3682 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 3683 return I40E_ERR_INVALID_SIZE; 3684 3685 return 0; 3686} 3687 3688/** 3689 * i40e_set_filter_control 3690 * @hw: pointer to the hardware structure 3691 * @settings: Filter control settings 3692 * 3693 * Set the Queue Filters for PE/FCoE and enable filters required 3694 * for a single PF. It is expected that these settings are programmed 3695 * at the driver initialization time. 3696 **/ 3697i40e_status i40e_set_filter_control(struct i40e_hw *hw, 3698 struct i40e_filter_control_settings *settings) 3699{ 3700 i40e_status ret = 0; 3701 u32 hash_lut_size = 0; 3702 u32 val; 3703 3704 if (!settings) 3705 return I40E_ERR_PARAM; 3706 3707 /* Validate the input settings */ 3708 ret = i40e_validate_filter_settings(hw, settings); 3709 if (ret) 3710 return ret; 3711 3712 /* Read the PF Queue Filter control register */ 3713 val = rd32(hw, I40E_PFQF_CTL_0); 3714 3715 /* Program required PE hash buckets for the PF */ 3716 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 3717 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 3718 I40E_PFQF_CTL_0_PEHSIZE_MASK; 3719 /* Program required PE contexts for the PF */ 3720 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 3721 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 3722 I40E_PFQF_CTL_0_PEDSIZE_MASK; 3723 3724 /* Program required FCoE hash buckets for the PF */ 3725 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3726 val |= ((u32)settings->fcoe_filt_num << 3727 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 3728 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3729 /* Program required FCoE DDP contexts for the PF */ 3730 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3731 val |= ((u32)settings->fcoe_cntx_num << 3732 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 3733 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3734 3735 /* Program Hash LUT size for the PF */ 3736 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3737 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 3738 hash_lut_size = 1; 3739 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 3740 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3741 3742 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 3743 if (settings->enable_fdir) 3744 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 3745 if (settings->enable_ethtype) 3746 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 3747 if (settings->enable_macvlan) 3748 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 3749 3750 wr32(hw, I40E_PFQF_CTL_0, val); 3751 3752 return 0; 3753} 3754 3755/** 3756 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 3757 * @hw: pointer to the hw struct 3758 * @mac_addr: MAC address to use in the filter 3759 * @ethtype: Ethertype to use in the filter 3760 * @flags: Flags that needs to be applied to the filter 3761 * @vsi_seid: seid of the control VSI 3762 * @queue: VSI queue number to send the packet to 3763 * @is_add: Add control packet filter if True else remove 3764 * @stats: Structure to hold information on control filter counts 3765 * @cmd_details: pointer to command details structure or NULL 3766 * 3767 * This command will Add or Remove control packet filter for a control VSI. 3768 * In return it will update the total number of perfect filter count in 3769 * the stats member. 3770 **/ 3771i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 3772 u8 *mac_addr, u16 ethtype, u16 flags, 3773 u16 vsi_seid, u16 queue, bool is_add, 3774 struct i40e_control_filter_stats *stats, 3775 struct i40e_asq_cmd_details *cmd_details) 3776{ 3777 struct i40e_aq_desc desc; 3778 struct i40e_aqc_add_remove_control_packet_filter *cmd = 3779 (struct i40e_aqc_add_remove_control_packet_filter *) 3780 &desc.params.raw; 3781 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 3782 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 3783 &desc.params.raw; 3784 i40e_status status; 3785 3786 if (vsi_seid == 0) 3787 return I40E_ERR_PARAM; 3788 3789 if (is_add) { 3790 i40e_fill_default_direct_cmd_desc(&desc, 3791 i40e_aqc_opc_add_control_packet_filter); 3792 cmd->queue = cpu_to_le16(queue); 3793 } else { 3794 i40e_fill_default_direct_cmd_desc(&desc, 3795 i40e_aqc_opc_remove_control_packet_filter); 3796 } 3797 3798 if (mac_addr) 3799 ether_addr_copy(cmd->mac, mac_addr); 3800 3801 cmd->etype = cpu_to_le16(ethtype); 3802 cmd->flags = cpu_to_le16(flags); 3803 cmd->seid = cpu_to_le16(vsi_seid); 3804 3805 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3806 3807 if (!status && stats) { 3808 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 3809 stats->etype_used = le16_to_cpu(resp->etype_used); 3810 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 3811 stats->etype_free = le16_to_cpu(resp->etype_free); 3812 } 3813 3814 return status; 3815} 3816 3817/** 3818 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 3819 * @hw: pointer to the hw struct 3820 * @seid: VSI seid to add ethertype filter from 3821 **/ 3822#define I40E_FLOW_CONTROL_ETHTYPE 0x8808 3823void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 3824 u16 seid) 3825{ 3826 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 3827 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 3828 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 3829 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 3830 i40e_status status; 3831 3832 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 3833 seid, 0, true, NULL, 3834 NULL); 3835 if (status) 3836 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 3837} 3838 3839/** 3840 * i40e_aq_alternate_read 3841 * @hw: pointer to the hardware structure 3842 * @reg_addr0: address of first dword to be read 3843 * @reg_val0: pointer for data read from 'reg_addr0' 3844 * @reg_addr1: address of second dword to be read 3845 * @reg_val1: pointer for data read from 'reg_addr1' 3846 * 3847 * Read one or two dwords from alternate structure. Fields are indicated 3848 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 3849 * is not passed then only register at 'reg_addr0' is read. 3850 * 3851 **/ 3852static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, 3853 u32 reg_addr0, u32 *reg_val0, 3854 u32 reg_addr1, u32 *reg_val1) 3855{ 3856 struct i40e_aq_desc desc; 3857 struct i40e_aqc_alternate_write *cmd_resp = 3858 (struct i40e_aqc_alternate_write *)&desc.params.raw; 3859 i40e_status status; 3860 3861 if (!reg_val0) 3862 return I40E_ERR_PARAM; 3863 3864 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 3865 cmd_resp->address0 = cpu_to_le32(reg_addr0); 3866 cmd_resp->address1 = cpu_to_le32(reg_addr1); 3867 3868 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 3869 3870 if (!status) { 3871 *reg_val0 = le32_to_cpu(cmd_resp->data0); 3872 3873 if (reg_val1) 3874 *reg_val1 = le32_to_cpu(cmd_resp->data1); 3875 } 3876 3877 return status; 3878} 3879 3880/** 3881 * i40e_aq_resume_port_tx 3882 * @hw: pointer to the hardware structure 3883 * @cmd_details: pointer to command details structure or NULL 3884 * 3885 * Resume port's Tx traffic 3886 **/ 3887i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 3888 struct i40e_asq_cmd_details *cmd_details) 3889{ 3890 struct i40e_aq_desc desc; 3891 i40e_status status; 3892 3893 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 3894 3895 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3896 3897 return status; 3898} 3899 3900/** 3901 * i40e_set_pci_config_data - store PCI bus info 3902 * @hw: pointer to hardware structure 3903 * @link_status: the link status word from PCI config space 3904 * 3905 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 3906 **/ 3907void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 3908{ 3909 hw->bus.type = i40e_bus_type_pci_express; 3910 3911 switch (link_status & PCI_EXP_LNKSTA_NLW) { 3912 case PCI_EXP_LNKSTA_NLW_X1: 3913 hw->bus.width = i40e_bus_width_pcie_x1; 3914 break; 3915 case PCI_EXP_LNKSTA_NLW_X2: 3916 hw->bus.width = i40e_bus_width_pcie_x2; 3917 break; 3918 case PCI_EXP_LNKSTA_NLW_X4: 3919 hw->bus.width = i40e_bus_width_pcie_x4; 3920 break; 3921 case PCI_EXP_LNKSTA_NLW_X8: 3922 hw->bus.width = i40e_bus_width_pcie_x8; 3923 break; 3924 default: 3925 hw->bus.width = i40e_bus_width_unknown; 3926 break; 3927 } 3928 3929 switch (link_status & PCI_EXP_LNKSTA_CLS) { 3930 case PCI_EXP_LNKSTA_CLS_2_5GB: 3931 hw->bus.speed = i40e_bus_speed_2500; 3932 break; 3933 case PCI_EXP_LNKSTA_CLS_5_0GB: 3934 hw->bus.speed = i40e_bus_speed_5000; 3935 break; 3936 case PCI_EXP_LNKSTA_CLS_8_0GB: 3937 hw->bus.speed = i40e_bus_speed_8000; 3938 break; 3939 default: 3940 hw->bus.speed = i40e_bus_speed_unknown; 3941 break; 3942 } 3943} 3944 3945/** 3946 * i40e_aq_debug_dump 3947 * @hw: pointer to the hardware structure 3948 * @cluster_id: specific cluster to dump 3949 * @table_id: table id within cluster 3950 * @start_index: index of line in the block to read 3951 * @buff_size: dump buffer size 3952 * @buff: dump buffer 3953 * @ret_buff_size: actual buffer size returned 3954 * @ret_next_table: next block to read 3955 * @ret_next_index: next index to read 3956 * 3957 * Dump internal FW/HW data for debug purposes. 3958 * 3959 **/ 3960i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 3961 u8 table_id, u32 start_index, u16 buff_size, 3962 void *buff, u16 *ret_buff_size, 3963 u8 *ret_next_table, u32 *ret_next_index, 3964 struct i40e_asq_cmd_details *cmd_details) 3965{ 3966 struct i40e_aq_desc desc; 3967 struct i40e_aqc_debug_dump_internals *cmd = 3968 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 3969 struct i40e_aqc_debug_dump_internals *resp = 3970 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 3971 i40e_status status; 3972 3973 if (buff_size == 0 || !buff) 3974 return I40E_ERR_PARAM; 3975 3976 i40e_fill_default_direct_cmd_desc(&desc, 3977 i40e_aqc_opc_debug_dump_internals); 3978 /* Indirect Command */ 3979 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3980 if (buff_size > I40E_AQ_LARGE_BUF) 3981 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3982 3983 cmd->cluster_id = cluster_id; 3984 cmd->table_id = table_id; 3985 cmd->idx = cpu_to_le32(start_index); 3986 3987 desc.datalen = cpu_to_le16(buff_size); 3988 3989 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3990 if (!status) { 3991 if (ret_buff_size) 3992 *ret_buff_size = le16_to_cpu(desc.datalen); 3993 if (ret_next_table) 3994 *ret_next_table = resp->table_id; 3995 if (ret_next_index) 3996 *ret_next_index = le32_to_cpu(resp->idx); 3997 } 3998 3999 return status; 4000} 4001 4002/** 4003 * i40e_read_bw_from_alt_ram 4004 * @hw: pointer to the hardware structure 4005 * @max_bw: pointer for max_bw read 4006 * @min_bw: pointer for min_bw read 4007 * @min_valid: pointer for bool that is true if min_bw is a valid value 4008 * @max_valid: pointer for bool that is true if max_bw is a valid value 4009 * 4010 * Read bw from the alternate ram for the given pf 4011 **/ 4012i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4013 u32 *max_bw, u32 *min_bw, 4014 bool *min_valid, bool *max_valid) 4015{ 4016 i40e_status status; 4017 u32 max_bw_addr, min_bw_addr; 4018 4019 /* Calculate the address of the min/max bw registers */ 4020 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4021 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4022 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4023 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4024 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4025 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4026 4027 /* Read the bandwidths from alt ram */ 4028 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4029 min_bw_addr, min_bw); 4030 4031 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4032 *min_valid = true; 4033 else 4034 *min_valid = false; 4035 4036 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4037 *max_valid = true; 4038 else 4039 *max_valid = false; 4040 4041 return status; 4042} 4043 4044/** 4045 * i40e_aq_configure_partition_bw 4046 * @hw: pointer to the hardware structure 4047 * @bw_data: Buffer holding valid pfs and bw limits 4048 * @cmd_details: pointer to command details 4049 * 4050 * Configure partitions guaranteed/max bw 4051 **/ 4052i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4053 struct i40e_aqc_configure_partition_bw_data *bw_data, 4054 struct i40e_asq_cmd_details *cmd_details) 4055{ 4056 i40e_status status; 4057 struct i40e_aq_desc desc; 4058 u16 bwd_size = sizeof(*bw_data); 4059 4060 i40e_fill_default_direct_cmd_desc(&desc, 4061 i40e_aqc_opc_configure_partition_bw); 4062 4063 /* Indirect command */ 4064 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4065 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4066 4067 if (bwd_size > I40E_AQ_LARGE_BUF) 4068 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4069 4070 desc.datalen = cpu_to_le16(bwd_size); 4071 4072 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4073 cmd_details); 4074 4075 return status; 4076} 4077