1/*
2 * Copyright (c) 2014-2015 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef _HNS_DSAF_PPE_H
11#define _HNS_DSAF_PPE_H
12
13#include <linux/platform_device.h>
14
15#include "hns_dsaf_main.h"
16#include "hns_dsaf_mac.h"
17#include "hns_dsaf_rcb.h"
18
19#define HNS_PPE_SERVICE_NW_ENGINE_NUM DSAF_COMM_CHN
20#define HNS_PPE_DEBUG_NW_ENGINE_NUM 1
21#define HNS_PPE_COM_NUM DSAF_COMM_DEV_NUM
22
23#define PPE_COMMON_REG_OFFSET 0x70000
24#define PPE_REG_OFFSET 0x10000
25
26#define ETH_PPE_DUMP_NUM 576
27#define ETH_PPE_STATIC_NUM 12
28enum ppe_qid_mode {
29	PPE_QID_MODE0 = 0,	/* fixed queue id mode */
30	PPE_QID_MODE1,		/* switch:128VM non switch:6Port/4VM/4TC */
31	PPE_QID_MODE2,		/* switch:32VM/4TC non switch:6Port/16VM */
32	PPE_QID_MODE3,		/* switch:4TC/8TAG non switch:2Port/64VM */
33	PPE_QID_MODE4,		/* switch:8VM/16TAG non switch:2Port/16VM/4TC */
34	PPE_QID_MODE5,		/* non switch:6Port/16TAG */
35	PPE_QID_MODE6,		/* non switch:6Port/2VM/8TC */
36	PPE_QID_MODE7,		/* non switch:2Port/8VM/8TC */
37};
38
39enum ppe_port_mode {
40	PPE_MODE_GE = 0,
41	PPE_MODE_XGE,
42};
43
44enum ppe_common_mode {
45	PPE_COMMON_MODE_DEBUG = 0,
46	PPE_COMMON_MODE_SERVICE,
47	PPE_COMMON_MODE_MAX
48};
49
50struct hns_ppe_hw_stats {
51	u64 rx_pkts_from_sw;
52	u64 rx_pkts;
53	u64 rx_drop_no_bd;
54	u64 rx_alloc_buf_fail;
55	u64 rx_alloc_buf_wait;
56	u64 rx_drop_no_buf;
57	u64 rx_err_fifo_full;
58	u64 tx_bd_form_rcb;
59	u64 tx_pkts_from_rcb;
60	u64 tx_pkts;
61	u64 tx_err_fifo_empty;
62	u64 tx_err_checksum;
63};
64
65struct hns_ppe_cb {
66	struct device *dev;
67	struct hns_ppe_cb *next;	/* pointer to next ppe device */
68	struct ppe_common_cb *ppe_common_cb; /* belong to */
69	struct hns_ppe_hw_stats hw_stats;
70
71	u8 index;	/* index in a ppe common device */
72	u8 port;			 /* port id in dsaf  */
73	void __iomem *io_base;
74	int virq;
75};
76
77struct ppe_common_cb {
78	struct device *dev;
79	struct dsaf_device *dsaf_dev;
80	void __iomem *io_base;
81
82	enum ppe_common_mode ppe_mode;
83
84	u8 comm_index;   /*ppe_common index*/
85
86	u32 ppe_num;
87	struct hns_ppe_cb ppe_cb[0];
88
89};
90
91int hns_ppe_init(struct dsaf_device *dsaf_dev);
92
93void hns_ppe_uninit(struct dsaf_device *dsaf_dev);
94
95void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index);
96
97void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb);
98
99int hns_ppe_get_sset_count(int stringset);
100int hns_ppe_get_regs_count(void);
101void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data);
102
103void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data);
104void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data);
105#endif /* _HNS_DSAF_PPE_H */
106