1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/ptrace.h>
29 #include <linux/errno.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/in.h>
38 #include <linux/ip.h>
39 #include <net/ip.h>
40 #include <net/tso.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/icmp.h>
44 #include <linux/spinlock.h>
45 #include <linux/workqueue.h>
46 #include <linux/bitops.h>
47 #include <linux/io.h>
48 #include <linux/irq.h>
49 #include <linux/clk.h>
50 #include <linux/platform_device.h>
51 #include <linux/phy.h>
52 #include <linux/fec.h>
53 #include <linux/of.h>
54 #include <linux/of_device.h>
55 #include <linux/of_gpio.h>
56 #include <linux/of_mdio.h>
57 #include <linux/of_net.h>
58 #include <linux/regulator/consumer.h>
59 #include <linux/if_vlan.h>
60 #include <linux/pinctrl/consumer.h>
61 #include <linux/prefetch.h>
62
63 #include <asm/cacheflush.h>
64
65 #include "fec.h"
66
67 static void set_multicast_list(struct net_device *ndev);
68 static void fec_enet_itr_coal_init(struct net_device *ndev);
69
70 #define DRIVER_NAME "fec"
71
72 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
73
74 /* Pause frame feild and FIFO threshold */
75 #define FEC_ENET_FCE (1 << 5)
76 #define FEC_ENET_RSEM_V 0x84
77 #define FEC_ENET_RSFL_V 16
78 #define FEC_ENET_RAEM_V 0x8
79 #define FEC_ENET_RAFL_V 0x8
80 #define FEC_ENET_OPD_V 0xFFF0
81 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
82
83 static struct platform_device_id fec_devtype[] = {
84 {
85 /* keep it for coldfire */
86 .name = DRIVER_NAME,
87 .driver_data = 0,
88 }, {
89 .name = "imx25-fec",
90 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC,
91 }, {
92 .name = "imx27-fec",
93 .driver_data = FEC_QUIRK_HAS_RACC,
94 }, {
95 .name = "imx28-fec",
96 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
97 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
98 }, {
99 .name = "imx6q-fec",
100 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
101 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
102 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
103 FEC_QUIRK_HAS_RACC,
104 }, {
105 .name = "mvf600-fec",
106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
107 }, {
108 .name = "imx6sx-fec",
109 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
110 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
111 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
112 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
113 FEC_QUIRK_HAS_RACC,
114 }, {
115 /* sentinel */
116 }
117 };
118 MODULE_DEVICE_TABLE(platform, fec_devtype);
119
120 enum imx_fec_type {
121 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
122 IMX27_FEC, /* runs on i.mx27/35/51 */
123 IMX28_FEC,
124 IMX6Q_FEC,
125 MVF600_FEC,
126 IMX6SX_FEC,
127 };
128
129 static const struct of_device_id fec_dt_ids[] = {
130 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
131 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
132 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
133 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
134 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
135 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
136 { /* sentinel */ }
137 };
138 MODULE_DEVICE_TABLE(of, fec_dt_ids);
139
140 static unsigned char macaddr[ETH_ALEN];
141 module_param_array(macaddr, byte, NULL, 0);
142 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
143
144 #if defined(CONFIG_M5272)
145 /*
146 * Some hardware gets it MAC address out of local flash memory.
147 * if this is non-zero then assume it is the address to get MAC from.
148 */
149 #if defined(CONFIG_NETtel)
150 #define FEC_FLASHMAC 0xf0006006
151 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
152 #define FEC_FLASHMAC 0xf0006000
153 #elif defined(CONFIG_CANCam)
154 #define FEC_FLASHMAC 0xf0020000
155 #elif defined (CONFIG_M5272C3)
156 #define FEC_FLASHMAC (0xffe04000 + 4)
157 #elif defined(CONFIG_MOD5272)
158 #define FEC_FLASHMAC 0xffc0406b
159 #else
160 #define FEC_FLASHMAC 0
161 #endif
162 #endif /* CONFIG_M5272 */
163
164 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
165 */
166 #define PKT_MAXBUF_SIZE 1522
167 #define PKT_MINBUF_SIZE 64
168 #define PKT_MAXBLR_SIZE 1536
169
170 /* FEC receive acceleration */
171 #define FEC_RACC_IPDIS (1 << 1)
172 #define FEC_RACC_PRODIS (1 << 2)
173 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
174
175 /*
176 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
177 * size bits. Other FEC hardware does not, so we need to take that into
178 * account when setting it.
179 */
180 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
181 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
182 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
183 #else
184 #define OPT_FRAME_SIZE 0
185 #endif
186
187 /* FEC MII MMFR bits definition */
188 #define FEC_MMFR_ST (1 << 30)
189 #define FEC_MMFR_OP_READ (2 << 28)
190 #define FEC_MMFR_OP_WRITE (1 << 28)
191 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
192 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
193 #define FEC_MMFR_TA (2 << 16)
194 #define FEC_MMFR_DATA(v) (v & 0xffff)
195 /* FEC ECR bits definition */
196 #define FEC_ECR_MAGICEN (1 << 2)
197 #define FEC_ECR_SLEEP (1 << 3)
198
199 #define FEC_MII_TIMEOUT 30000 /* us */
200
201 /* Transmitter timeout */
202 #define TX_TIMEOUT (2 * HZ)
203
204 #define FEC_PAUSE_FLAG_AUTONEG 0x1
205 #define FEC_PAUSE_FLAG_ENABLE 0x2
206 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
207 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
208 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
209
210 #define COPYBREAK_DEFAULT 256
211
212 #define TSO_HEADER_SIZE 128
213 /* Max number of allowed TCP segments for software TSO */
214 #define FEC_MAX_TSO_SEGS 100
215 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
216
217 #define IS_TSO_HEADER(txq, addr) \
218 ((addr >= txq->tso_hdrs_dma) && \
219 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
220
221 static int mii_cnt;
222
223 static inline
fec_enet_get_nextdesc(struct bufdesc * bdp,struct fec_enet_private * fep,int queue_id)224 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
225 struct fec_enet_private *fep,
226 int queue_id)
227 {
228 struct bufdesc *new_bd = bdp + 1;
229 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
230 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
231 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
232 struct bufdesc_ex *ex_base;
233 struct bufdesc *base;
234 int ring_size;
235
236 if (bdp >= txq->tx_bd_base) {
237 base = txq->tx_bd_base;
238 ring_size = txq->tx_ring_size;
239 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
240 } else {
241 base = rxq->rx_bd_base;
242 ring_size = rxq->rx_ring_size;
243 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
244 }
245
246 if (fep->bufdesc_ex)
247 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
248 ex_base : ex_new_bd);
249 else
250 return (new_bd >= (base + ring_size)) ?
251 base : new_bd;
252 }
253
254 static inline
fec_enet_get_prevdesc(struct bufdesc * bdp,struct fec_enet_private * fep,int queue_id)255 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
256 struct fec_enet_private *fep,
257 int queue_id)
258 {
259 struct bufdesc *new_bd = bdp - 1;
260 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
261 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
262 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
263 struct bufdesc_ex *ex_base;
264 struct bufdesc *base;
265 int ring_size;
266
267 if (bdp >= txq->tx_bd_base) {
268 base = txq->tx_bd_base;
269 ring_size = txq->tx_ring_size;
270 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
271 } else {
272 base = rxq->rx_bd_base;
273 ring_size = rxq->rx_ring_size;
274 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
275 }
276
277 if (fep->bufdesc_ex)
278 return (struct bufdesc *)((ex_new_bd < ex_base) ?
279 (ex_new_bd + ring_size) : ex_new_bd);
280 else
281 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
282 }
283
fec_enet_get_bd_index(struct bufdesc * base,struct bufdesc * bdp,struct fec_enet_private * fep)284 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
285 struct fec_enet_private *fep)
286 {
287 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
288 }
289
fec_enet_get_free_txdesc_num(struct fec_enet_private * fep,struct fec_enet_priv_tx_q * txq)290 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
291 struct fec_enet_priv_tx_q *txq)
292 {
293 int entries;
294
295 entries = ((const char *)txq->dirty_tx -
296 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
297
298 return entries > 0 ? entries : entries + txq->tx_ring_size;
299 }
300
swap_buffer(void * bufaddr,int len)301 static void swap_buffer(void *bufaddr, int len)
302 {
303 int i;
304 unsigned int *buf = bufaddr;
305
306 for (i = 0; i < len; i += 4, buf++)
307 swab32s(buf);
308 }
309
swap_buffer2(void * dst_buf,void * src_buf,int len)310 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
311 {
312 int i;
313 unsigned int *src = src_buf;
314 unsigned int *dst = dst_buf;
315
316 for (i = 0; i < len; i += 4, src++, dst++)
317 *dst = swab32p(src);
318 }
319
fec_dump(struct net_device * ndev)320 static void fec_dump(struct net_device *ndev)
321 {
322 struct fec_enet_private *fep = netdev_priv(ndev);
323 struct bufdesc *bdp;
324 struct fec_enet_priv_tx_q *txq;
325 int index = 0;
326
327 netdev_info(ndev, "TX ring dump\n");
328 pr_info("Nr SC addr len SKB\n");
329
330 txq = fep->tx_queue[0];
331 bdp = txq->tx_bd_base;
332
333 do {
334 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
335 index,
336 bdp == txq->cur_tx ? 'S' : ' ',
337 bdp == txq->dirty_tx ? 'H' : ' ',
338 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
339 txq->tx_skbuff[index]);
340 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
341 index++;
342 } while (bdp != txq->tx_bd_base);
343 }
344
is_ipv4_pkt(struct sk_buff * skb)345 static inline bool is_ipv4_pkt(struct sk_buff *skb)
346 {
347 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
348 }
349
350 static int
fec_enet_clear_csum(struct sk_buff * skb,struct net_device * ndev)351 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
352 {
353 /* Only run for packets requiring a checksum. */
354 if (skb->ip_summed != CHECKSUM_PARTIAL)
355 return 0;
356
357 if (unlikely(skb_cow_head(skb, 0)))
358 return -1;
359
360 if (is_ipv4_pkt(skb))
361 ip_hdr(skb)->check = 0;
362 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
363
364 return 0;
365 }
366
367 static struct bufdesc *
fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev)368 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
369 struct sk_buff *skb,
370 struct net_device *ndev)
371 {
372 struct fec_enet_private *fep = netdev_priv(ndev);
373 struct bufdesc *bdp = txq->cur_tx;
374 struct bufdesc_ex *ebdp;
375 int nr_frags = skb_shinfo(skb)->nr_frags;
376 unsigned short queue = skb_get_queue_mapping(skb);
377 int frag, frag_len;
378 unsigned short status;
379 unsigned int estatus = 0;
380 skb_frag_t *this_frag;
381 unsigned int index;
382 void *bufaddr;
383 dma_addr_t addr;
384 int i;
385
386 for (frag = 0; frag < nr_frags; frag++) {
387 this_frag = &skb_shinfo(skb)->frags[frag];
388 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
389 ebdp = (struct bufdesc_ex *)bdp;
390
391 status = bdp->cbd_sc;
392 status &= ~BD_ENET_TX_STATS;
393 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
394 frag_len = skb_shinfo(skb)->frags[frag].size;
395
396 /* Handle the last BD specially */
397 if (frag == nr_frags - 1) {
398 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
399 if (fep->bufdesc_ex) {
400 estatus |= BD_ENET_TX_INT;
401 if (unlikely(skb_shinfo(skb)->tx_flags &
402 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
403 estatus |= BD_ENET_TX_TS;
404 }
405 }
406
407 if (fep->bufdesc_ex) {
408 if (fep->quirks & FEC_QUIRK_HAS_AVB)
409 estatus |= FEC_TX_BD_FTYPE(queue);
410 if (skb->ip_summed == CHECKSUM_PARTIAL)
411 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
412 ebdp->cbd_bdu = 0;
413 ebdp->cbd_esc = estatus;
414 }
415
416 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
417
418 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
419 if (((unsigned long) bufaddr) & fep->tx_align ||
420 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
421 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
422 bufaddr = txq->tx_bounce[index];
423
424 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
425 swap_buffer(bufaddr, frag_len);
426 }
427
428 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
429 DMA_TO_DEVICE);
430 if (dma_mapping_error(&fep->pdev->dev, addr)) {
431 dev_kfree_skb_any(skb);
432 if (net_ratelimit())
433 netdev_err(ndev, "Tx DMA memory map failed\n");
434 goto dma_mapping_error;
435 }
436
437 bdp->cbd_bufaddr = addr;
438 bdp->cbd_datlen = frag_len;
439 bdp->cbd_sc = status;
440 }
441
442 return bdp;
443 dma_mapping_error:
444 bdp = txq->cur_tx;
445 for (i = 0; i < frag; i++) {
446 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
447 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
448 bdp->cbd_datlen, DMA_TO_DEVICE);
449 }
450 return ERR_PTR(-ENOMEM);
451 }
452
fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev)453 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
454 struct sk_buff *skb, struct net_device *ndev)
455 {
456 struct fec_enet_private *fep = netdev_priv(ndev);
457 int nr_frags = skb_shinfo(skb)->nr_frags;
458 struct bufdesc *bdp, *last_bdp;
459 void *bufaddr;
460 dma_addr_t addr;
461 unsigned short status;
462 unsigned short buflen;
463 unsigned short queue;
464 unsigned int estatus = 0;
465 unsigned int index;
466 int entries_free;
467
468 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
469 if (entries_free < MAX_SKB_FRAGS + 1) {
470 dev_kfree_skb_any(skb);
471 if (net_ratelimit())
472 netdev_err(ndev, "NOT enough BD for SG!\n");
473 return NETDEV_TX_OK;
474 }
475
476 /* Protocol checksum off-load for TCP and UDP. */
477 if (fec_enet_clear_csum(skb, ndev)) {
478 dev_kfree_skb_any(skb);
479 return NETDEV_TX_OK;
480 }
481
482 /* Fill in a Tx ring entry */
483 bdp = txq->cur_tx;
484 last_bdp = bdp;
485 status = bdp->cbd_sc;
486 status &= ~BD_ENET_TX_STATS;
487
488 /* Set buffer length and buffer pointer */
489 bufaddr = skb->data;
490 buflen = skb_headlen(skb);
491
492 queue = skb_get_queue_mapping(skb);
493 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
494 if (((unsigned long) bufaddr) & fep->tx_align ||
495 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
496 memcpy(txq->tx_bounce[index], skb->data, buflen);
497 bufaddr = txq->tx_bounce[index];
498
499 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
500 swap_buffer(bufaddr, buflen);
501 }
502
503 /* Push the data cache so the CPM does not get stale memory data. */
504 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
505 if (dma_mapping_error(&fep->pdev->dev, addr)) {
506 dev_kfree_skb_any(skb);
507 if (net_ratelimit())
508 netdev_err(ndev, "Tx DMA memory map failed\n");
509 return NETDEV_TX_OK;
510 }
511
512 if (nr_frags) {
513 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
514 if (IS_ERR(last_bdp))
515 return NETDEV_TX_OK;
516 } else {
517 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
518 if (fep->bufdesc_ex) {
519 estatus = BD_ENET_TX_INT;
520 if (unlikely(skb_shinfo(skb)->tx_flags &
521 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
522 estatus |= BD_ENET_TX_TS;
523 }
524 }
525
526 if (fep->bufdesc_ex) {
527
528 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
529
530 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
531 fep->hwts_tx_en))
532 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
533
534 if (fep->quirks & FEC_QUIRK_HAS_AVB)
535 estatus |= FEC_TX_BD_FTYPE(queue);
536
537 if (skb->ip_summed == CHECKSUM_PARTIAL)
538 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
539
540 ebdp->cbd_bdu = 0;
541 ebdp->cbd_esc = estatus;
542 }
543
544 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
545 /* Save skb pointer */
546 txq->tx_skbuff[index] = skb;
547
548 bdp->cbd_datlen = buflen;
549 bdp->cbd_bufaddr = addr;
550
551 /* Send it on its way. Tell FEC it's ready, interrupt when done,
552 * it's the last BD of the frame, and to put the CRC on the end.
553 */
554 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
555 bdp->cbd_sc = status;
556
557 /* If this was the last BD in the ring, start at the beginning again. */
558 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
559
560 skb_tx_timestamp(skb);
561
562 /* Make sure the update to bdp and tx_skbuff are performed before
563 * cur_tx.
564 */
565 wmb();
566 txq->cur_tx = bdp;
567
568 /* Trigger transmission start */
569 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
570
571 return 0;
572 }
573
574 static int
fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev,struct bufdesc * bdp,int index,char * data,int size,bool last_tcp,bool is_last)575 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
576 struct net_device *ndev,
577 struct bufdesc *bdp, int index, char *data,
578 int size, bool last_tcp, bool is_last)
579 {
580 struct fec_enet_private *fep = netdev_priv(ndev);
581 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
582 unsigned short queue = skb_get_queue_mapping(skb);
583 unsigned short status;
584 unsigned int estatus = 0;
585 dma_addr_t addr;
586
587 status = bdp->cbd_sc;
588 status &= ~BD_ENET_TX_STATS;
589
590 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
591
592 if (((unsigned long) data) & fep->tx_align ||
593 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
594 memcpy(txq->tx_bounce[index], data, size);
595 data = txq->tx_bounce[index];
596
597 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
598 swap_buffer(data, size);
599 }
600
601 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
602 if (dma_mapping_error(&fep->pdev->dev, addr)) {
603 dev_kfree_skb_any(skb);
604 if (net_ratelimit())
605 netdev_err(ndev, "Tx DMA memory map failed\n");
606 return NETDEV_TX_BUSY;
607 }
608
609 bdp->cbd_datlen = size;
610 bdp->cbd_bufaddr = addr;
611
612 if (fep->bufdesc_ex) {
613 if (fep->quirks & FEC_QUIRK_HAS_AVB)
614 estatus |= FEC_TX_BD_FTYPE(queue);
615 if (skb->ip_summed == CHECKSUM_PARTIAL)
616 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
617 ebdp->cbd_bdu = 0;
618 ebdp->cbd_esc = estatus;
619 }
620
621 /* Handle the last BD specially */
622 if (last_tcp)
623 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
624 if (is_last) {
625 status |= BD_ENET_TX_INTR;
626 if (fep->bufdesc_ex)
627 ebdp->cbd_esc |= BD_ENET_TX_INT;
628 }
629
630 bdp->cbd_sc = status;
631
632 return 0;
633 }
634
635 static int
fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev,struct bufdesc * bdp,int index)636 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
637 struct sk_buff *skb, struct net_device *ndev,
638 struct bufdesc *bdp, int index)
639 {
640 struct fec_enet_private *fep = netdev_priv(ndev);
641 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
642 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
643 unsigned short queue = skb_get_queue_mapping(skb);
644 void *bufaddr;
645 unsigned long dmabuf;
646 unsigned short status;
647 unsigned int estatus = 0;
648
649 status = bdp->cbd_sc;
650 status &= ~BD_ENET_TX_STATS;
651 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
652
653 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
654 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
655 if (((unsigned long)bufaddr) & fep->tx_align ||
656 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
657 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
658 bufaddr = txq->tx_bounce[index];
659
660 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
661 swap_buffer(bufaddr, hdr_len);
662
663 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
664 hdr_len, DMA_TO_DEVICE);
665 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
666 dev_kfree_skb_any(skb);
667 if (net_ratelimit())
668 netdev_err(ndev, "Tx DMA memory map failed\n");
669 return NETDEV_TX_BUSY;
670 }
671 }
672
673 bdp->cbd_bufaddr = dmabuf;
674 bdp->cbd_datlen = hdr_len;
675
676 if (fep->bufdesc_ex) {
677 if (fep->quirks & FEC_QUIRK_HAS_AVB)
678 estatus |= FEC_TX_BD_FTYPE(queue);
679 if (skb->ip_summed == CHECKSUM_PARTIAL)
680 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
681 ebdp->cbd_bdu = 0;
682 ebdp->cbd_esc = estatus;
683 }
684
685 bdp->cbd_sc = status;
686
687 return 0;
688 }
689
fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev)690 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
691 struct sk_buff *skb,
692 struct net_device *ndev)
693 {
694 struct fec_enet_private *fep = netdev_priv(ndev);
695 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
696 int total_len, data_left;
697 struct bufdesc *bdp = txq->cur_tx;
698 unsigned short queue = skb_get_queue_mapping(skb);
699 struct tso_t tso;
700 unsigned int index = 0;
701 int ret;
702
703 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
704 dev_kfree_skb_any(skb);
705 if (net_ratelimit())
706 netdev_err(ndev, "NOT enough BD for TSO!\n");
707 return NETDEV_TX_OK;
708 }
709
710 /* Protocol checksum off-load for TCP and UDP. */
711 if (fec_enet_clear_csum(skb, ndev)) {
712 dev_kfree_skb_any(skb);
713 return NETDEV_TX_OK;
714 }
715
716 /* Initialize the TSO handler, and prepare the first payload */
717 tso_start(skb, &tso);
718
719 total_len = skb->len - hdr_len;
720 while (total_len > 0) {
721 char *hdr;
722
723 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
724 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
725 total_len -= data_left;
726
727 /* prepare packet headers: MAC + IP + TCP */
728 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
729 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
730 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
731 if (ret)
732 goto err_release;
733
734 while (data_left > 0) {
735 int size;
736
737 size = min_t(int, tso.size, data_left);
738 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
739 index = fec_enet_get_bd_index(txq->tx_bd_base,
740 bdp, fep);
741 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
742 bdp, index,
743 tso.data, size,
744 size == data_left,
745 total_len == 0);
746 if (ret)
747 goto err_release;
748
749 data_left -= size;
750 tso_build_data(skb, &tso, size);
751 }
752
753 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
754 }
755
756 /* Save skb pointer */
757 txq->tx_skbuff[index] = skb;
758
759 skb_tx_timestamp(skb);
760 txq->cur_tx = bdp;
761
762 /* Trigger transmission start */
763 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
764 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
765 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
766 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
767 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
768 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
769
770 return 0;
771
772 err_release:
773 /* TODO: Release all used data descriptors for TSO */
774 return ret;
775 }
776
777 static netdev_tx_t
fec_enet_start_xmit(struct sk_buff * skb,struct net_device * ndev)778 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
779 {
780 struct fec_enet_private *fep = netdev_priv(ndev);
781 int entries_free;
782 unsigned short queue;
783 struct fec_enet_priv_tx_q *txq;
784 struct netdev_queue *nq;
785 int ret;
786
787 queue = skb_get_queue_mapping(skb);
788 txq = fep->tx_queue[queue];
789 nq = netdev_get_tx_queue(ndev, queue);
790
791 if (skb_is_gso(skb))
792 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
793 else
794 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
795 if (ret)
796 return ret;
797
798 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
799 if (entries_free <= txq->tx_stop_threshold)
800 netif_tx_stop_queue(nq);
801
802 return NETDEV_TX_OK;
803 }
804
805 /* Init RX & TX buffer descriptors
806 */
fec_enet_bd_init(struct net_device * dev)807 static void fec_enet_bd_init(struct net_device *dev)
808 {
809 struct fec_enet_private *fep = netdev_priv(dev);
810 struct fec_enet_priv_tx_q *txq;
811 struct fec_enet_priv_rx_q *rxq;
812 struct bufdesc *bdp;
813 unsigned int i;
814 unsigned int q;
815
816 for (q = 0; q < fep->num_rx_queues; q++) {
817 /* Initialize the receive buffer descriptors. */
818 rxq = fep->rx_queue[q];
819 bdp = rxq->rx_bd_base;
820
821 for (i = 0; i < rxq->rx_ring_size; i++) {
822
823 /* Initialize the BD for every fragment in the page. */
824 if (bdp->cbd_bufaddr)
825 bdp->cbd_sc = BD_ENET_RX_EMPTY;
826 else
827 bdp->cbd_sc = 0;
828 bdp = fec_enet_get_nextdesc(bdp, fep, q);
829 }
830
831 /* Set the last buffer to wrap */
832 bdp = fec_enet_get_prevdesc(bdp, fep, q);
833 bdp->cbd_sc |= BD_SC_WRAP;
834
835 rxq->cur_rx = rxq->rx_bd_base;
836 }
837
838 for (q = 0; q < fep->num_tx_queues; q++) {
839 /* ...and the same for transmit */
840 txq = fep->tx_queue[q];
841 bdp = txq->tx_bd_base;
842 txq->cur_tx = bdp;
843
844 for (i = 0; i < txq->tx_ring_size; i++) {
845 /* Initialize the BD for every fragment in the page. */
846 bdp->cbd_sc = 0;
847 if (txq->tx_skbuff[i]) {
848 dev_kfree_skb_any(txq->tx_skbuff[i]);
849 txq->tx_skbuff[i] = NULL;
850 }
851 bdp->cbd_bufaddr = 0;
852 bdp = fec_enet_get_nextdesc(bdp, fep, q);
853 }
854
855 /* Set the last buffer to wrap */
856 bdp = fec_enet_get_prevdesc(bdp, fep, q);
857 bdp->cbd_sc |= BD_SC_WRAP;
858 txq->dirty_tx = bdp;
859 }
860 }
861
fec_enet_active_rxring(struct net_device * ndev)862 static void fec_enet_active_rxring(struct net_device *ndev)
863 {
864 struct fec_enet_private *fep = netdev_priv(ndev);
865 int i;
866
867 for (i = 0; i < fep->num_rx_queues; i++)
868 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
869 }
870
fec_enet_enable_ring(struct net_device * ndev)871 static void fec_enet_enable_ring(struct net_device *ndev)
872 {
873 struct fec_enet_private *fep = netdev_priv(ndev);
874 struct fec_enet_priv_tx_q *txq;
875 struct fec_enet_priv_rx_q *rxq;
876 int i;
877
878 for (i = 0; i < fep->num_rx_queues; i++) {
879 rxq = fep->rx_queue[i];
880 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
881 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
882
883 /* enable DMA1/2 */
884 if (i)
885 writel(RCMR_MATCHEN | RCMR_CMP(i),
886 fep->hwp + FEC_RCMR(i));
887 }
888
889 for (i = 0; i < fep->num_tx_queues; i++) {
890 txq = fep->tx_queue[i];
891 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
892
893 /* enable DMA1/2 */
894 if (i)
895 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
896 fep->hwp + FEC_DMA_CFG(i));
897 }
898 }
899
fec_enet_reset_skb(struct net_device * ndev)900 static void fec_enet_reset_skb(struct net_device *ndev)
901 {
902 struct fec_enet_private *fep = netdev_priv(ndev);
903 struct fec_enet_priv_tx_q *txq;
904 int i, j;
905
906 for (i = 0; i < fep->num_tx_queues; i++) {
907 txq = fep->tx_queue[i];
908
909 for (j = 0; j < txq->tx_ring_size; j++) {
910 if (txq->tx_skbuff[j]) {
911 dev_kfree_skb_any(txq->tx_skbuff[j]);
912 txq->tx_skbuff[j] = NULL;
913 }
914 }
915 }
916 }
917
918 /*
919 * This function is called to start or restart the FEC during a link
920 * change, transmit timeout, or to reconfigure the FEC. The network
921 * packet processing for this device must be stopped before this call.
922 */
923 static void
fec_restart(struct net_device * ndev)924 fec_restart(struct net_device *ndev)
925 {
926 struct fec_enet_private *fep = netdev_priv(ndev);
927 u32 val;
928 u32 temp_mac[2];
929 u32 rcntl = OPT_FRAME_SIZE | 0x04;
930 u32 ecntl = 0x2; /* ETHEREN */
931
932 /* Whack a reset. We should wait for this.
933 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
934 * instead of reset MAC itself.
935 */
936 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
937 writel(0, fep->hwp + FEC_ECNTRL);
938 } else {
939 writel(1, fep->hwp + FEC_ECNTRL);
940 udelay(10);
941 }
942
943 /*
944 * enet-mac reset will reset mac address registers too,
945 * so need to reconfigure it.
946 */
947 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
948 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
949 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
950 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
951 }
952
953 /* Clear any outstanding interrupt. */
954 writel(0xffffffff, fep->hwp + FEC_IEVENT);
955
956 fec_enet_bd_init(ndev);
957
958 fec_enet_enable_ring(ndev);
959
960 /* Reset tx SKB buffers. */
961 fec_enet_reset_skb(ndev);
962
963 /* Enable MII mode */
964 if (fep->full_duplex == DUPLEX_FULL) {
965 /* FD enable */
966 writel(0x04, fep->hwp + FEC_X_CNTRL);
967 } else {
968 /* No Rcv on Xmit */
969 rcntl |= 0x02;
970 writel(0x0, fep->hwp + FEC_X_CNTRL);
971 }
972
973 /* Set MII speed */
974 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
975
976 #if !defined(CONFIG_M5272)
977 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
978 /* set RX checksum */
979 val = readl(fep->hwp + FEC_RACC);
980 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
981 val |= FEC_RACC_OPTIONS;
982 else
983 val &= ~FEC_RACC_OPTIONS;
984 writel(val, fep->hwp + FEC_RACC);
985 }
986 #endif
987
988 /*
989 * The phy interface and speed need to get configured
990 * differently on enet-mac.
991 */
992 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
993 /* Enable flow control and length check */
994 rcntl |= 0x40000000 | 0x00000020;
995
996 /* RGMII, RMII or MII */
997 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
998 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
999 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1000 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1001 rcntl |= (1 << 6);
1002 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1003 rcntl |= (1 << 8);
1004 else
1005 rcntl &= ~(1 << 8);
1006
1007 /* 1G, 100M or 10M */
1008 if (fep->phy_dev) {
1009 if (fep->phy_dev->speed == SPEED_1000)
1010 ecntl |= (1 << 5);
1011 else if (fep->phy_dev->speed == SPEED_100)
1012 rcntl &= ~(1 << 9);
1013 else
1014 rcntl |= (1 << 9);
1015 }
1016 } else {
1017 #ifdef FEC_MIIGSK_ENR
1018 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1019 u32 cfgr;
1020 /* disable the gasket and wait */
1021 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1022 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1023 udelay(1);
1024
1025 /*
1026 * configure the gasket:
1027 * RMII, 50 MHz, no loopback, no echo
1028 * MII, 25 MHz, no loopback, no echo
1029 */
1030 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1031 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1032 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1033 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1034 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1035
1036 /* re-enable the gasket */
1037 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1038 }
1039 #endif
1040 }
1041
1042 #if !defined(CONFIG_M5272)
1043 /* enable pause frame*/
1044 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1045 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1046 fep->phy_dev && fep->phy_dev->pause)) {
1047 rcntl |= FEC_ENET_FCE;
1048
1049 /* set FIFO threshold parameter to reduce overrun */
1050 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1051 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1052 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1053 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1054
1055 /* OPD */
1056 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1057 } else {
1058 rcntl &= ~FEC_ENET_FCE;
1059 }
1060 #endif /* !defined(CONFIG_M5272) */
1061
1062 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1063
1064 /* Setup multicast filter. */
1065 set_multicast_list(ndev);
1066 #ifndef CONFIG_M5272
1067 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1068 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1069 #endif
1070
1071 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1072 /* enable ENET endian swap */
1073 ecntl |= (1 << 8);
1074 /* enable ENET store and forward mode */
1075 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1076 }
1077
1078 if (fep->bufdesc_ex)
1079 ecntl |= (1 << 4);
1080
1081 #ifndef CONFIG_M5272
1082 /* Enable the MIB statistic event counters */
1083 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1084 #endif
1085
1086 /* And last, enable the transmit and receive processing */
1087 writel(ecntl, fep->hwp + FEC_ECNTRL);
1088 fec_enet_active_rxring(ndev);
1089
1090 if (fep->bufdesc_ex)
1091 fec_ptp_start_cyclecounter(ndev);
1092
1093 /* Enable interrupts we wish to service */
1094 if (fep->link)
1095 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1096 else
1097 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1098
1099 /* Init the interrupt coalescing */
1100 fec_enet_itr_coal_init(ndev);
1101
1102 }
1103
1104 static void
fec_stop(struct net_device * ndev)1105 fec_stop(struct net_device *ndev)
1106 {
1107 struct fec_enet_private *fep = netdev_priv(ndev);
1108 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1109 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1110 u32 val;
1111
1112 /* We cannot expect a graceful transmit stop without link !!! */
1113 if (fep->link) {
1114 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1115 udelay(10);
1116 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1117 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1118 }
1119
1120 /* Whack a reset. We should wait for this.
1121 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1122 * instead of reset MAC itself.
1123 */
1124 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1125 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1126 writel(0, fep->hwp + FEC_ECNTRL);
1127 } else {
1128 writel(1, fep->hwp + FEC_ECNTRL);
1129 udelay(10);
1130 }
1131 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1132 } else {
1133 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1134 val = readl(fep->hwp + FEC_ECNTRL);
1135 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1136 writel(val, fep->hwp + FEC_ECNTRL);
1137
1138 if (pdata && pdata->sleep_mode_enable)
1139 pdata->sleep_mode_enable(true);
1140 }
1141 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1142
1143 /* We have to keep ENET enabled to have MII interrupt stay working */
1144 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1145 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1146 writel(2, fep->hwp + FEC_ECNTRL);
1147 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1148 }
1149 }
1150
1151
1152 static void
fec_timeout(struct net_device * ndev)1153 fec_timeout(struct net_device *ndev)
1154 {
1155 struct fec_enet_private *fep = netdev_priv(ndev);
1156
1157 fec_dump(ndev);
1158
1159 ndev->stats.tx_errors++;
1160
1161 schedule_work(&fep->tx_timeout_work);
1162 }
1163
fec_enet_timeout_work(struct work_struct * work)1164 static void fec_enet_timeout_work(struct work_struct *work)
1165 {
1166 struct fec_enet_private *fep =
1167 container_of(work, struct fec_enet_private, tx_timeout_work);
1168 struct net_device *ndev = fep->netdev;
1169
1170 rtnl_lock();
1171 if (netif_device_present(ndev) || netif_running(ndev)) {
1172 napi_disable(&fep->napi);
1173 netif_tx_lock_bh(ndev);
1174 fec_restart(ndev);
1175 netif_wake_queue(ndev);
1176 netif_tx_unlock_bh(ndev);
1177 napi_enable(&fep->napi);
1178 }
1179 rtnl_unlock();
1180 }
1181
1182 static void
fec_enet_hwtstamp(struct fec_enet_private * fep,unsigned ts,struct skb_shared_hwtstamps * hwtstamps)1183 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1184 struct skb_shared_hwtstamps *hwtstamps)
1185 {
1186 unsigned long flags;
1187 u64 ns;
1188
1189 spin_lock_irqsave(&fep->tmreg_lock, flags);
1190 ns = timecounter_cyc2time(&fep->tc, ts);
1191 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1192
1193 memset(hwtstamps, 0, sizeof(*hwtstamps));
1194 hwtstamps->hwtstamp = ns_to_ktime(ns);
1195 }
1196
1197 static void
fec_enet_tx_queue(struct net_device * ndev,u16 queue_id)1198 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1199 {
1200 struct fec_enet_private *fep;
1201 struct bufdesc *bdp;
1202 unsigned short status;
1203 struct sk_buff *skb;
1204 struct fec_enet_priv_tx_q *txq;
1205 struct netdev_queue *nq;
1206 int index = 0;
1207 int entries_free;
1208
1209 fep = netdev_priv(ndev);
1210
1211 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1212
1213 txq = fep->tx_queue[queue_id];
1214 /* get next bdp of dirty_tx */
1215 nq = netdev_get_tx_queue(ndev, queue_id);
1216 bdp = txq->dirty_tx;
1217
1218 /* get next bdp of dirty_tx */
1219 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1220
1221 while (bdp != READ_ONCE(txq->cur_tx)) {
1222 /* Order the load of cur_tx and cbd_sc */
1223 rmb();
1224 status = READ_ONCE(bdp->cbd_sc);
1225 if (status & BD_ENET_TX_READY)
1226 break;
1227
1228 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
1229
1230 skb = txq->tx_skbuff[index];
1231 txq->tx_skbuff[index] = NULL;
1232 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
1233 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1234 bdp->cbd_datlen, DMA_TO_DEVICE);
1235 bdp->cbd_bufaddr = 0;
1236 if (!skb) {
1237 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1238 continue;
1239 }
1240
1241 /* Check for errors. */
1242 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1243 BD_ENET_TX_RL | BD_ENET_TX_UN |
1244 BD_ENET_TX_CSL)) {
1245 ndev->stats.tx_errors++;
1246 if (status & BD_ENET_TX_HB) /* No heartbeat */
1247 ndev->stats.tx_heartbeat_errors++;
1248 if (status & BD_ENET_TX_LC) /* Late collision */
1249 ndev->stats.tx_window_errors++;
1250 if (status & BD_ENET_TX_RL) /* Retrans limit */
1251 ndev->stats.tx_aborted_errors++;
1252 if (status & BD_ENET_TX_UN) /* Underrun */
1253 ndev->stats.tx_fifo_errors++;
1254 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1255 ndev->stats.tx_carrier_errors++;
1256 } else {
1257 ndev->stats.tx_packets++;
1258 ndev->stats.tx_bytes += skb->len;
1259 }
1260
1261 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1262 fep->bufdesc_ex) {
1263 struct skb_shared_hwtstamps shhwtstamps;
1264 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1265
1266 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
1267 skb_tstamp_tx(skb, &shhwtstamps);
1268 }
1269
1270 /* Deferred means some collisions occurred during transmit,
1271 * but we eventually sent the packet OK.
1272 */
1273 if (status & BD_ENET_TX_DEF)
1274 ndev->stats.collisions++;
1275
1276 /* Free the sk buffer associated with this last transmit */
1277 dev_kfree_skb_any(skb);
1278
1279 /* Make sure the update to bdp and tx_skbuff are performed
1280 * before dirty_tx
1281 */
1282 wmb();
1283 txq->dirty_tx = bdp;
1284
1285 /* Update pointer to next buffer descriptor to be transmitted */
1286 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1287
1288 /* Since we have freed up a buffer, the ring is no longer full
1289 */
1290 if (netif_queue_stopped(ndev)) {
1291 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1292 if (entries_free >= txq->tx_wake_threshold)
1293 netif_tx_wake_queue(nq);
1294 }
1295 }
1296
1297 /* ERR006538: Keep the transmitter going */
1298 if (bdp != txq->cur_tx &&
1299 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1300 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1301 }
1302
1303 static void
fec_enet_tx(struct net_device * ndev)1304 fec_enet_tx(struct net_device *ndev)
1305 {
1306 struct fec_enet_private *fep = netdev_priv(ndev);
1307 u16 queue_id;
1308 /* First process class A queue, then Class B and Best Effort queue */
1309 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1310 clear_bit(queue_id, &fep->work_tx);
1311 fec_enet_tx_queue(ndev, queue_id);
1312 }
1313 return;
1314 }
1315
1316 static int
fec_enet_new_rxbdp(struct net_device * ndev,struct bufdesc * bdp,struct sk_buff * skb)1317 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1318 {
1319 struct fec_enet_private *fep = netdev_priv(ndev);
1320 int off;
1321
1322 off = ((unsigned long)skb->data) & fep->rx_align;
1323 if (off)
1324 skb_reserve(skb, fep->rx_align + 1 - off);
1325
1326 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1327 FEC_ENET_RX_FRSIZE - fep->rx_align,
1328 DMA_FROM_DEVICE);
1329 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1330 if (net_ratelimit())
1331 netdev_err(ndev, "Rx DMA memory map failed\n");
1332 return -ENOMEM;
1333 }
1334
1335 return 0;
1336 }
1337
fec_enet_copybreak(struct net_device * ndev,struct sk_buff ** skb,struct bufdesc * bdp,u32 length,bool swap)1338 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1339 struct bufdesc *bdp, u32 length, bool swap)
1340 {
1341 struct fec_enet_private *fep = netdev_priv(ndev);
1342 struct sk_buff *new_skb;
1343
1344 if (length > fep->rx_copybreak)
1345 return false;
1346
1347 new_skb = netdev_alloc_skb(ndev, length);
1348 if (!new_skb)
1349 return false;
1350
1351 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1352 FEC_ENET_RX_FRSIZE - fep->rx_align,
1353 DMA_FROM_DEVICE);
1354 if (!swap)
1355 memcpy(new_skb->data, (*skb)->data, length);
1356 else
1357 swap_buffer2(new_skb->data, (*skb)->data, length);
1358 *skb = new_skb;
1359
1360 return true;
1361 }
1362
1363 /* During a receive, the cur_rx points to the current incoming buffer.
1364 * When we update through the ring, if the next incoming buffer has
1365 * not been given to the system, we just set the empty indicator,
1366 * effectively tossing the packet.
1367 */
1368 static int
fec_enet_rx_queue(struct net_device * ndev,int budget,u16 queue_id)1369 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1370 {
1371 struct fec_enet_private *fep = netdev_priv(ndev);
1372 struct fec_enet_priv_rx_q *rxq;
1373 struct bufdesc *bdp;
1374 unsigned short status;
1375 struct sk_buff *skb_new = NULL;
1376 struct sk_buff *skb;
1377 ushort pkt_len;
1378 __u8 *data;
1379 int pkt_received = 0;
1380 struct bufdesc_ex *ebdp = NULL;
1381 bool vlan_packet_rcvd = false;
1382 u16 vlan_tag;
1383 int index = 0;
1384 bool is_copybreak;
1385 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1386
1387 #ifdef CONFIG_M532x
1388 flush_cache_all();
1389 #endif
1390 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1391 rxq = fep->rx_queue[queue_id];
1392
1393 /* First, grab all of the stats for the incoming packet.
1394 * These get messed up if we get called due to a busy condition.
1395 */
1396 bdp = rxq->cur_rx;
1397
1398 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1399
1400 if (pkt_received >= budget)
1401 break;
1402 pkt_received++;
1403
1404 /* Since we have allocated space to hold a complete frame,
1405 * the last indicator should be set.
1406 */
1407 if ((status & BD_ENET_RX_LAST) == 0)
1408 netdev_err(ndev, "rcv is not +last\n");
1409
1410 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1411
1412 /* Check for errors. */
1413 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1414 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1415 ndev->stats.rx_errors++;
1416 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1417 /* Frame too long or too short. */
1418 ndev->stats.rx_length_errors++;
1419 }
1420 if (status & BD_ENET_RX_NO) /* Frame alignment */
1421 ndev->stats.rx_frame_errors++;
1422 if (status & BD_ENET_RX_CR) /* CRC Error */
1423 ndev->stats.rx_crc_errors++;
1424 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1425 ndev->stats.rx_fifo_errors++;
1426 }
1427
1428 /* Report late collisions as a frame error.
1429 * On this error, the BD is closed, but we don't know what we
1430 * have in the buffer. So, just drop this frame on the floor.
1431 */
1432 if (status & BD_ENET_RX_CL) {
1433 ndev->stats.rx_errors++;
1434 ndev->stats.rx_frame_errors++;
1435 goto rx_processing_done;
1436 }
1437
1438 /* Process the incoming frame. */
1439 ndev->stats.rx_packets++;
1440 pkt_len = bdp->cbd_datlen;
1441 ndev->stats.rx_bytes += pkt_len;
1442
1443 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1444 skb = rxq->rx_skbuff[index];
1445
1446 /* The packet length includes FCS, but we don't want to
1447 * include that when passing upstream as it messes up
1448 * bridging applications.
1449 */
1450 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1451 need_swap);
1452 if (!is_copybreak) {
1453 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1454 if (unlikely(!skb_new)) {
1455 ndev->stats.rx_dropped++;
1456 goto rx_processing_done;
1457 }
1458 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1459 FEC_ENET_RX_FRSIZE - fep->rx_align,
1460 DMA_FROM_DEVICE);
1461 }
1462
1463 prefetch(skb->data - NET_IP_ALIGN);
1464 skb_put(skb, pkt_len - 4);
1465 data = skb->data;
1466 if (!is_copybreak && need_swap)
1467 swap_buffer(data, pkt_len);
1468
1469 /* Extract the enhanced buffer descriptor */
1470 ebdp = NULL;
1471 if (fep->bufdesc_ex)
1472 ebdp = (struct bufdesc_ex *)bdp;
1473
1474 /* If this is a VLAN packet remove the VLAN Tag */
1475 vlan_packet_rcvd = false;
1476 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1477 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1478 /* Push and remove the vlan tag */
1479 struct vlan_hdr *vlan_header =
1480 (struct vlan_hdr *) (data + ETH_HLEN);
1481 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1482
1483 vlan_packet_rcvd = true;
1484
1485 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1486 skb_pull(skb, VLAN_HLEN);
1487 }
1488
1489 skb->protocol = eth_type_trans(skb, ndev);
1490
1491 /* Get receive timestamp from the skb */
1492 if (fep->hwts_rx_en && fep->bufdesc_ex)
1493 fec_enet_hwtstamp(fep, ebdp->ts,
1494 skb_hwtstamps(skb));
1495
1496 if (fep->bufdesc_ex &&
1497 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1498 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1499 /* don't check it */
1500 skb->ip_summed = CHECKSUM_UNNECESSARY;
1501 } else {
1502 skb_checksum_none_assert(skb);
1503 }
1504 }
1505
1506 /* Handle received VLAN packets */
1507 if (vlan_packet_rcvd)
1508 __vlan_hwaccel_put_tag(skb,
1509 htons(ETH_P_8021Q),
1510 vlan_tag);
1511
1512 napi_gro_receive(&fep->napi, skb);
1513
1514 if (is_copybreak) {
1515 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1516 FEC_ENET_RX_FRSIZE - fep->rx_align,
1517 DMA_FROM_DEVICE);
1518 } else {
1519 rxq->rx_skbuff[index] = skb_new;
1520 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1521 }
1522
1523 rx_processing_done:
1524 /* Clear the status flags for this buffer */
1525 status &= ~BD_ENET_RX_STATS;
1526
1527 /* Mark the buffer empty */
1528 status |= BD_ENET_RX_EMPTY;
1529 bdp->cbd_sc = status;
1530
1531 if (fep->bufdesc_ex) {
1532 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1533
1534 ebdp->cbd_esc = BD_ENET_RX_INT;
1535 ebdp->cbd_prot = 0;
1536 ebdp->cbd_bdu = 0;
1537 }
1538
1539 /* Update BD pointer to next entry */
1540 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1541
1542 /* Doing this here will keep the FEC running while we process
1543 * incoming frames. On a heavily loaded network, we should be
1544 * able to keep up at the expense of system resources.
1545 */
1546 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
1547 }
1548 rxq->cur_rx = bdp;
1549 return pkt_received;
1550 }
1551
1552 static int
fec_enet_rx(struct net_device * ndev,int budget)1553 fec_enet_rx(struct net_device *ndev, int budget)
1554 {
1555 int pkt_received = 0;
1556 u16 queue_id;
1557 struct fec_enet_private *fep = netdev_priv(ndev);
1558
1559 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1560 int ret;
1561
1562 ret = fec_enet_rx_queue(ndev,
1563 budget - pkt_received, queue_id);
1564
1565 if (ret < budget - pkt_received)
1566 clear_bit(queue_id, &fep->work_rx);
1567
1568 pkt_received += ret;
1569 }
1570 return pkt_received;
1571 }
1572
1573 static bool
fec_enet_collect_events(struct fec_enet_private * fep,uint int_events)1574 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1575 {
1576 if (int_events == 0)
1577 return false;
1578
1579 if (int_events & FEC_ENET_RXF)
1580 fep->work_rx |= (1 << 2);
1581 if (int_events & FEC_ENET_RXF_1)
1582 fep->work_rx |= (1 << 0);
1583 if (int_events & FEC_ENET_RXF_2)
1584 fep->work_rx |= (1 << 1);
1585
1586 if (int_events & FEC_ENET_TXF)
1587 fep->work_tx |= (1 << 2);
1588 if (int_events & FEC_ENET_TXF_1)
1589 fep->work_tx |= (1 << 0);
1590 if (int_events & FEC_ENET_TXF_2)
1591 fep->work_tx |= (1 << 1);
1592
1593 return true;
1594 }
1595
1596 static irqreturn_t
fec_enet_interrupt(int irq,void * dev_id)1597 fec_enet_interrupt(int irq, void *dev_id)
1598 {
1599 struct net_device *ndev = dev_id;
1600 struct fec_enet_private *fep = netdev_priv(ndev);
1601 uint int_events;
1602 irqreturn_t ret = IRQ_NONE;
1603
1604 int_events = readl(fep->hwp + FEC_IEVENT);
1605 writel(int_events, fep->hwp + FEC_IEVENT);
1606 fec_enet_collect_events(fep, int_events);
1607
1608 if ((fep->work_tx || fep->work_rx) && fep->link) {
1609 ret = IRQ_HANDLED;
1610
1611 if (napi_schedule_prep(&fep->napi)) {
1612 /* Disable the NAPI interrupts */
1613 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1614 __napi_schedule(&fep->napi);
1615 }
1616 }
1617
1618 if (int_events & FEC_ENET_MII) {
1619 ret = IRQ_HANDLED;
1620 complete(&fep->mdio_done);
1621 }
1622
1623 if (fep->ptp_clock)
1624 fec_ptp_check_pps_event(fep);
1625
1626 return ret;
1627 }
1628
fec_enet_rx_napi(struct napi_struct * napi,int budget)1629 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1630 {
1631 struct net_device *ndev = napi->dev;
1632 struct fec_enet_private *fep = netdev_priv(ndev);
1633 int pkts;
1634
1635 pkts = fec_enet_rx(ndev, budget);
1636
1637 fec_enet_tx(ndev);
1638
1639 if (pkts < budget) {
1640 napi_complete(napi);
1641 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1642 }
1643 return pkts;
1644 }
1645
1646 /* ------------------------------------------------------------------------- */
fec_get_mac(struct net_device * ndev)1647 static void fec_get_mac(struct net_device *ndev)
1648 {
1649 struct fec_enet_private *fep = netdev_priv(ndev);
1650 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1651 unsigned char *iap, tmpaddr[ETH_ALEN];
1652
1653 /*
1654 * try to get mac address in following order:
1655 *
1656 * 1) module parameter via kernel command line in form
1657 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1658 */
1659 iap = macaddr;
1660
1661 /*
1662 * 2) from device tree data
1663 */
1664 if (!is_valid_ether_addr(iap)) {
1665 struct device_node *np = fep->pdev->dev.of_node;
1666 if (np) {
1667 const char *mac = of_get_mac_address(np);
1668 if (mac)
1669 iap = (unsigned char *) mac;
1670 }
1671 }
1672
1673 /*
1674 * 3) from flash or fuse (via platform data)
1675 */
1676 if (!is_valid_ether_addr(iap)) {
1677 #ifdef CONFIG_M5272
1678 if (FEC_FLASHMAC)
1679 iap = (unsigned char *)FEC_FLASHMAC;
1680 #else
1681 if (pdata)
1682 iap = (unsigned char *)&pdata->mac;
1683 #endif
1684 }
1685
1686 /*
1687 * 4) FEC mac registers set by bootloader
1688 */
1689 if (!is_valid_ether_addr(iap)) {
1690 *((__be32 *) &tmpaddr[0]) =
1691 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1692 *((__be16 *) &tmpaddr[4]) =
1693 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1694 iap = &tmpaddr[0];
1695 }
1696
1697 /*
1698 * 5) random mac address
1699 */
1700 if (!is_valid_ether_addr(iap)) {
1701 /* Report it and use a random ethernet address instead */
1702 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1703 eth_hw_addr_random(ndev);
1704 netdev_info(ndev, "Using random MAC address: %pM\n",
1705 ndev->dev_addr);
1706 return;
1707 }
1708
1709 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1710
1711 /* Adjust MAC if using macaddr */
1712 if (iap == macaddr)
1713 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1714 }
1715
1716 /* ------------------------------------------------------------------------- */
1717
1718 /*
1719 * Phy section
1720 */
fec_enet_adjust_link(struct net_device * ndev)1721 static void fec_enet_adjust_link(struct net_device *ndev)
1722 {
1723 struct fec_enet_private *fep = netdev_priv(ndev);
1724 struct phy_device *phy_dev = fep->phy_dev;
1725 int status_change = 0;
1726
1727 /* Prevent a state halted on mii error */
1728 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1729 phy_dev->state = PHY_RESUMING;
1730 return;
1731 }
1732
1733 /*
1734 * If the netdev is down, or is going down, we're not interested
1735 * in link state events, so just mark our idea of the link as down
1736 * and ignore the event.
1737 */
1738 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1739 fep->link = 0;
1740 } else if (phy_dev->link) {
1741 if (!fep->link) {
1742 fep->link = phy_dev->link;
1743 status_change = 1;
1744 }
1745
1746 if (fep->full_duplex != phy_dev->duplex) {
1747 fep->full_duplex = phy_dev->duplex;
1748 status_change = 1;
1749 }
1750
1751 if (phy_dev->speed != fep->speed) {
1752 fep->speed = phy_dev->speed;
1753 status_change = 1;
1754 }
1755
1756 /* if any of the above changed restart the FEC */
1757 if (status_change) {
1758 napi_disable(&fep->napi);
1759 netif_tx_lock_bh(ndev);
1760 fec_restart(ndev);
1761 netif_wake_queue(ndev);
1762 netif_tx_unlock_bh(ndev);
1763 napi_enable(&fep->napi);
1764 }
1765 } else {
1766 if (fep->link) {
1767 napi_disable(&fep->napi);
1768 netif_tx_lock_bh(ndev);
1769 fec_stop(ndev);
1770 netif_tx_unlock_bh(ndev);
1771 napi_enable(&fep->napi);
1772 fep->link = phy_dev->link;
1773 status_change = 1;
1774 }
1775 }
1776
1777 if (status_change)
1778 phy_print_status(phy_dev);
1779 }
1780
fec_enet_mdio_read(struct mii_bus * bus,int mii_id,int regnum)1781 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1782 {
1783 struct fec_enet_private *fep = bus->priv;
1784 struct device *dev = &fep->pdev->dev;
1785 unsigned long time_left;
1786 int ret = 0;
1787
1788 ret = pm_runtime_get_sync(dev);
1789 if (ret < 0)
1790 return ret;
1791
1792 fep->mii_timeout = 0;
1793 reinit_completion(&fep->mdio_done);
1794
1795 /* start a read op */
1796 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1797 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1798 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1799
1800 /* wait for end of transfer */
1801 time_left = wait_for_completion_timeout(&fep->mdio_done,
1802 usecs_to_jiffies(FEC_MII_TIMEOUT));
1803 if (time_left == 0) {
1804 fep->mii_timeout = 1;
1805 netdev_err(fep->netdev, "MDIO read timeout\n");
1806 ret = -ETIMEDOUT;
1807 goto out;
1808 }
1809
1810 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1811
1812 out:
1813 pm_runtime_mark_last_busy(dev);
1814 pm_runtime_put_autosuspend(dev);
1815
1816 return ret;
1817 }
1818
fec_enet_mdio_write(struct mii_bus * bus,int mii_id,int regnum,u16 value)1819 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1820 u16 value)
1821 {
1822 struct fec_enet_private *fep = bus->priv;
1823 struct device *dev = &fep->pdev->dev;
1824 unsigned long time_left;
1825 int ret;
1826
1827 ret = pm_runtime_get_sync(dev);
1828 if (ret < 0)
1829 return ret;
1830 else
1831 ret = 0;
1832
1833 fep->mii_timeout = 0;
1834 reinit_completion(&fep->mdio_done);
1835
1836 /* start a write op */
1837 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1838 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1839 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1840 fep->hwp + FEC_MII_DATA);
1841
1842 /* wait for end of transfer */
1843 time_left = wait_for_completion_timeout(&fep->mdio_done,
1844 usecs_to_jiffies(FEC_MII_TIMEOUT));
1845 if (time_left == 0) {
1846 fep->mii_timeout = 1;
1847 netdev_err(fep->netdev, "MDIO write timeout\n");
1848 ret = -ETIMEDOUT;
1849 }
1850
1851 pm_runtime_mark_last_busy(dev);
1852 pm_runtime_put_autosuspend(dev);
1853
1854 return ret;
1855 }
1856
fec_enet_clk_enable(struct net_device * ndev,bool enable)1857 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1858 {
1859 struct fec_enet_private *fep = netdev_priv(ndev);
1860 int ret;
1861
1862 if (enable) {
1863 ret = clk_prepare_enable(fep->clk_ahb);
1864 if (ret)
1865 return ret;
1866 if (fep->clk_enet_out) {
1867 ret = clk_prepare_enable(fep->clk_enet_out);
1868 if (ret)
1869 goto failed_clk_enet_out;
1870 }
1871 if (fep->clk_ptp) {
1872 mutex_lock(&fep->ptp_clk_mutex);
1873 ret = clk_prepare_enable(fep->clk_ptp);
1874 if (ret) {
1875 mutex_unlock(&fep->ptp_clk_mutex);
1876 goto failed_clk_ptp;
1877 } else {
1878 fep->ptp_clk_on = true;
1879 }
1880 mutex_unlock(&fep->ptp_clk_mutex);
1881 }
1882 if (fep->clk_ref) {
1883 ret = clk_prepare_enable(fep->clk_ref);
1884 if (ret)
1885 goto failed_clk_ref;
1886 }
1887 } else {
1888 clk_disable_unprepare(fep->clk_ahb);
1889 if (fep->clk_enet_out)
1890 clk_disable_unprepare(fep->clk_enet_out);
1891 if (fep->clk_ptp) {
1892 mutex_lock(&fep->ptp_clk_mutex);
1893 clk_disable_unprepare(fep->clk_ptp);
1894 fep->ptp_clk_on = false;
1895 mutex_unlock(&fep->ptp_clk_mutex);
1896 }
1897 if (fep->clk_ref)
1898 clk_disable_unprepare(fep->clk_ref);
1899 }
1900
1901 return 0;
1902
1903 failed_clk_ref:
1904 if (fep->clk_ref)
1905 clk_disable_unprepare(fep->clk_ref);
1906 failed_clk_ptp:
1907 if (fep->clk_enet_out)
1908 clk_disable_unprepare(fep->clk_enet_out);
1909 failed_clk_enet_out:
1910 clk_disable_unprepare(fep->clk_ahb);
1911
1912 return ret;
1913 }
1914
fec_enet_mii_probe(struct net_device * ndev)1915 static int fec_enet_mii_probe(struct net_device *ndev)
1916 {
1917 struct fec_enet_private *fep = netdev_priv(ndev);
1918 struct phy_device *phy_dev = NULL;
1919 char mdio_bus_id[MII_BUS_ID_SIZE];
1920 char phy_name[MII_BUS_ID_SIZE + 3];
1921 int phy_id;
1922 int dev_id = fep->dev_id;
1923
1924 fep->phy_dev = NULL;
1925
1926 if (fep->phy_node) {
1927 phy_dev = of_phy_connect(ndev, fep->phy_node,
1928 &fec_enet_adjust_link, 0,
1929 fep->phy_interface);
1930 if (!phy_dev)
1931 return -ENODEV;
1932 } else {
1933 /* check for attached phy */
1934 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1935 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1936 continue;
1937 if (fep->mii_bus->phy_map[phy_id] == NULL)
1938 continue;
1939 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1940 continue;
1941 if (dev_id--)
1942 continue;
1943 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1944 break;
1945 }
1946
1947 if (phy_id >= PHY_MAX_ADDR) {
1948 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1949 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1950 phy_id = 0;
1951 }
1952
1953 snprintf(phy_name, sizeof(phy_name),
1954 PHY_ID_FMT, mdio_bus_id, phy_id);
1955 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1956 fep->phy_interface);
1957 }
1958
1959 if (IS_ERR(phy_dev)) {
1960 netdev_err(ndev, "could not attach to PHY\n");
1961 return PTR_ERR(phy_dev);
1962 }
1963
1964 /* mask with MAC supported features */
1965 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1966 phy_dev->supported &= PHY_GBIT_FEATURES;
1967 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1968 #if !defined(CONFIG_M5272)
1969 phy_dev->supported |= SUPPORTED_Pause;
1970 #endif
1971 }
1972 else
1973 phy_dev->supported &= PHY_BASIC_FEATURES;
1974
1975 phy_dev->advertising = phy_dev->supported;
1976
1977 fep->phy_dev = phy_dev;
1978 fep->link = 0;
1979 fep->full_duplex = 0;
1980
1981 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1982 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1983 fep->phy_dev->irq);
1984
1985 return 0;
1986 }
1987
fec_enet_mii_init(struct platform_device * pdev)1988 static int fec_enet_mii_init(struct platform_device *pdev)
1989 {
1990 static struct mii_bus *fec0_mii_bus;
1991 struct net_device *ndev = platform_get_drvdata(pdev);
1992 struct fec_enet_private *fep = netdev_priv(ndev);
1993 struct device_node *node;
1994 int err = -ENXIO, i;
1995 u32 mii_speed, holdtime;
1996
1997 /*
1998 * The i.MX28 dual fec interfaces are not equal.
1999 * Here are the differences:
2000 *
2001 * - fec0 supports MII & RMII modes while fec1 only supports RMII
2002 * - fec0 acts as the 1588 time master while fec1 is slave
2003 * - external phys can only be configured by fec0
2004 *
2005 * That is to say fec1 can not work independently. It only works
2006 * when fec0 is working. The reason behind this design is that the
2007 * second interface is added primarily for Switch mode.
2008 *
2009 * Because of the last point above, both phys are attached on fec0
2010 * mdio interface in board design, and need to be configured by
2011 * fec0 mii_bus.
2012 */
2013 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2014 /* fec1 uses fec0 mii_bus */
2015 if (mii_cnt && fec0_mii_bus) {
2016 fep->mii_bus = fec0_mii_bus;
2017 mii_cnt++;
2018 return 0;
2019 }
2020 return -ENOENT;
2021 }
2022
2023 fep->mii_timeout = 0;
2024
2025 /*
2026 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
2027 *
2028 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2029 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2030 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2031 * document.
2032 */
2033 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2034 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2035 mii_speed--;
2036 if (mii_speed > 63) {
2037 dev_err(&pdev->dev,
2038 "fec clock (%lu) to fast to get right mii speed\n",
2039 clk_get_rate(fep->clk_ipg));
2040 err = -EINVAL;
2041 goto err_out;
2042 }
2043
2044 /*
2045 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2046 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2047 * versions are RAZ there, so just ignore the difference and write the
2048 * register always.
2049 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2050 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2051 * output.
2052 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2053 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2054 * holdtime cannot result in a value greater than 3.
2055 */
2056 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2057
2058 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2059
2060 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2061
2062 fep->mii_bus = mdiobus_alloc();
2063 if (fep->mii_bus == NULL) {
2064 err = -ENOMEM;
2065 goto err_out;
2066 }
2067
2068 fep->mii_bus->name = "fec_enet_mii_bus";
2069 fep->mii_bus->read = fec_enet_mdio_read;
2070 fep->mii_bus->write = fec_enet_mdio_write;
2071 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2072 pdev->name, fep->dev_id + 1);
2073 fep->mii_bus->priv = fep;
2074 fep->mii_bus->parent = &pdev->dev;
2075
2076 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
2077 if (!fep->mii_bus->irq) {
2078 err = -ENOMEM;
2079 goto err_out_free_mdiobus;
2080 }
2081
2082 for (i = 0; i < PHY_MAX_ADDR; i++)
2083 fep->mii_bus->irq[i] = PHY_POLL;
2084
2085 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2086 if (node) {
2087 err = of_mdiobus_register(fep->mii_bus, node);
2088 of_node_put(node);
2089 } else {
2090 err = mdiobus_register(fep->mii_bus);
2091 }
2092
2093 if (err)
2094 goto err_out_free_mdio_irq;
2095
2096 mii_cnt++;
2097
2098 /* save fec0 mii_bus */
2099 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2100 fec0_mii_bus = fep->mii_bus;
2101
2102 return 0;
2103
2104 err_out_free_mdio_irq:
2105 kfree(fep->mii_bus->irq);
2106 err_out_free_mdiobus:
2107 mdiobus_free(fep->mii_bus);
2108 err_out:
2109 return err;
2110 }
2111
fec_enet_mii_remove(struct fec_enet_private * fep)2112 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2113 {
2114 if (--mii_cnt == 0) {
2115 mdiobus_unregister(fep->mii_bus);
2116 kfree(fep->mii_bus->irq);
2117 mdiobus_free(fep->mii_bus);
2118 }
2119 }
2120
fec_enet_get_settings(struct net_device * ndev,struct ethtool_cmd * cmd)2121 static int fec_enet_get_settings(struct net_device *ndev,
2122 struct ethtool_cmd *cmd)
2123 {
2124 struct fec_enet_private *fep = netdev_priv(ndev);
2125 struct phy_device *phydev = fep->phy_dev;
2126
2127 if (!phydev)
2128 return -ENODEV;
2129
2130 return phy_ethtool_gset(phydev, cmd);
2131 }
2132
fec_enet_set_settings(struct net_device * ndev,struct ethtool_cmd * cmd)2133 static int fec_enet_set_settings(struct net_device *ndev,
2134 struct ethtool_cmd *cmd)
2135 {
2136 struct fec_enet_private *fep = netdev_priv(ndev);
2137 struct phy_device *phydev = fep->phy_dev;
2138
2139 if (!phydev)
2140 return -ENODEV;
2141
2142 return phy_ethtool_sset(phydev, cmd);
2143 }
2144
fec_enet_get_drvinfo(struct net_device * ndev,struct ethtool_drvinfo * info)2145 static void fec_enet_get_drvinfo(struct net_device *ndev,
2146 struct ethtool_drvinfo *info)
2147 {
2148 struct fec_enet_private *fep = netdev_priv(ndev);
2149
2150 strlcpy(info->driver, fep->pdev->dev.driver->name,
2151 sizeof(info->driver));
2152 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2153 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2154 }
2155
fec_enet_get_regs_len(struct net_device * ndev)2156 static int fec_enet_get_regs_len(struct net_device *ndev)
2157 {
2158 struct fec_enet_private *fep = netdev_priv(ndev);
2159 struct resource *r;
2160 int s = 0;
2161
2162 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2163 if (r)
2164 s = resource_size(r);
2165
2166 return s;
2167 }
2168
2169 /* List of registers that can be safety be read to dump them with ethtool */
2170 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2171 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
2172 defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
2173 static u32 fec_enet_register_offset[] = {
2174 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2175 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2176 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2177 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2178 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2179 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2180 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2181 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2182 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2183 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2184 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2185 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2186 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2187 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2188 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2189 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2190 RMON_T_P_GTE2048, RMON_T_OCTETS,
2191 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2192 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2193 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2194 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2195 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2196 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2197 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2198 RMON_R_P_GTE2048, RMON_R_OCTETS,
2199 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2200 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2201 };
2202 #else
2203 static u32 fec_enet_register_offset[] = {
2204 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2205 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2206 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2207 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2208 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2209 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2210 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2211 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2212 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2213 };
2214 #endif
2215
fec_enet_get_regs(struct net_device * ndev,struct ethtool_regs * regs,void * regbuf)2216 static void fec_enet_get_regs(struct net_device *ndev,
2217 struct ethtool_regs *regs, void *regbuf)
2218 {
2219 struct fec_enet_private *fep = netdev_priv(ndev);
2220 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2221 u32 *buf = (u32 *)regbuf;
2222 u32 i, off;
2223
2224 memset(buf, 0, regs->len);
2225
2226 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2227 off = fec_enet_register_offset[i] / 4;
2228 buf[off] = readl(&theregs[off]);
2229 }
2230 }
2231
fec_enet_get_ts_info(struct net_device * ndev,struct ethtool_ts_info * info)2232 static int fec_enet_get_ts_info(struct net_device *ndev,
2233 struct ethtool_ts_info *info)
2234 {
2235 struct fec_enet_private *fep = netdev_priv(ndev);
2236
2237 if (fep->bufdesc_ex) {
2238
2239 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2240 SOF_TIMESTAMPING_RX_SOFTWARE |
2241 SOF_TIMESTAMPING_SOFTWARE |
2242 SOF_TIMESTAMPING_TX_HARDWARE |
2243 SOF_TIMESTAMPING_RX_HARDWARE |
2244 SOF_TIMESTAMPING_RAW_HARDWARE;
2245 if (fep->ptp_clock)
2246 info->phc_index = ptp_clock_index(fep->ptp_clock);
2247 else
2248 info->phc_index = -1;
2249
2250 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2251 (1 << HWTSTAMP_TX_ON);
2252
2253 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2254 (1 << HWTSTAMP_FILTER_ALL);
2255 return 0;
2256 } else {
2257 return ethtool_op_get_ts_info(ndev, info);
2258 }
2259 }
2260
2261 #if !defined(CONFIG_M5272)
2262
fec_enet_get_pauseparam(struct net_device * ndev,struct ethtool_pauseparam * pause)2263 static void fec_enet_get_pauseparam(struct net_device *ndev,
2264 struct ethtool_pauseparam *pause)
2265 {
2266 struct fec_enet_private *fep = netdev_priv(ndev);
2267
2268 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2269 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2270 pause->rx_pause = pause->tx_pause;
2271 }
2272
fec_enet_set_pauseparam(struct net_device * ndev,struct ethtool_pauseparam * pause)2273 static int fec_enet_set_pauseparam(struct net_device *ndev,
2274 struct ethtool_pauseparam *pause)
2275 {
2276 struct fec_enet_private *fep = netdev_priv(ndev);
2277
2278 if (!fep->phy_dev)
2279 return -ENODEV;
2280
2281 if (pause->tx_pause != pause->rx_pause) {
2282 netdev_info(ndev,
2283 "hardware only support enable/disable both tx and rx");
2284 return -EINVAL;
2285 }
2286
2287 fep->pause_flag = 0;
2288
2289 /* tx pause must be same as rx pause */
2290 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2291 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2292
2293 if (pause->rx_pause || pause->autoneg) {
2294 fep->phy_dev->supported |= ADVERTISED_Pause;
2295 fep->phy_dev->advertising |= ADVERTISED_Pause;
2296 } else {
2297 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2298 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2299 }
2300
2301 if (pause->autoneg) {
2302 if (netif_running(ndev))
2303 fec_stop(ndev);
2304 phy_start_aneg(fep->phy_dev);
2305 }
2306 if (netif_running(ndev)) {
2307 napi_disable(&fep->napi);
2308 netif_tx_lock_bh(ndev);
2309 fec_restart(ndev);
2310 netif_wake_queue(ndev);
2311 netif_tx_unlock_bh(ndev);
2312 napi_enable(&fep->napi);
2313 }
2314
2315 return 0;
2316 }
2317
2318 static const struct fec_stat {
2319 char name[ETH_GSTRING_LEN];
2320 u16 offset;
2321 } fec_stats[] = {
2322 /* RMON TX */
2323 { "tx_dropped", RMON_T_DROP },
2324 { "tx_packets", RMON_T_PACKETS },
2325 { "tx_broadcast", RMON_T_BC_PKT },
2326 { "tx_multicast", RMON_T_MC_PKT },
2327 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2328 { "tx_undersize", RMON_T_UNDERSIZE },
2329 { "tx_oversize", RMON_T_OVERSIZE },
2330 { "tx_fragment", RMON_T_FRAG },
2331 { "tx_jabber", RMON_T_JAB },
2332 { "tx_collision", RMON_T_COL },
2333 { "tx_64byte", RMON_T_P64 },
2334 { "tx_65to127byte", RMON_T_P65TO127 },
2335 { "tx_128to255byte", RMON_T_P128TO255 },
2336 { "tx_256to511byte", RMON_T_P256TO511 },
2337 { "tx_512to1023byte", RMON_T_P512TO1023 },
2338 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2339 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2340 { "tx_octets", RMON_T_OCTETS },
2341
2342 /* IEEE TX */
2343 { "IEEE_tx_drop", IEEE_T_DROP },
2344 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2345 { "IEEE_tx_1col", IEEE_T_1COL },
2346 { "IEEE_tx_mcol", IEEE_T_MCOL },
2347 { "IEEE_tx_def", IEEE_T_DEF },
2348 { "IEEE_tx_lcol", IEEE_T_LCOL },
2349 { "IEEE_tx_excol", IEEE_T_EXCOL },
2350 { "IEEE_tx_macerr", IEEE_T_MACERR },
2351 { "IEEE_tx_cserr", IEEE_T_CSERR },
2352 { "IEEE_tx_sqe", IEEE_T_SQE },
2353 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2354 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2355
2356 /* RMON RX */
2357 { "rx_packets", RMON_R_PACKETS },
2358 { "rx_broadcast", RMON_R_BC_PKT },
2359 { "rx_multicast", RMON_R_MC_PKT },
2360 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2361 { "rx_undersize", RMON_R_UNDERSIZE },
2362 { "rx_oversize", RMON_R_OVERSIZE },
2363 { "rx_fragment", RMON_R_FRAG },
2364 { "rx_jabber", RMON_R_JAB },
2365 { "rx_64byte", RMON_R_P64 },
2366 { "rx_65to127byte", RMON_R_P65TO127 },
2367 { "rx_128to255byte", RMON_R_P128TO255 },
2368 { "rx_256to511byte", RMON_R_P256TO511 },
2369 { "rx_512to1023byte", RMON_R_P512TO1023 },
2370 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2371 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2372 { "rx_octets", RMON_R_OCTETS },
2373
2374 /* IEEE RX */
2375 { "IEEE_rx_drop", IEEE_R_DROP },
2376 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2377 { "IEEE_rx_crc", IEEE_R_CRC },
2378 { "IEEE_rx_align", IEEE_R_ALIGN },
2379 { "IEEE_rx_macerr", IEEE_R_MACERR },
2380 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2381 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2382 };
2383
fec_enet_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)2384 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2385 struct ethtool_stats *stats, u64 *data)
2386 {
2387 struct fec_enet_private *fep = netdev_priv(dev);
2388 int i;
2389
2390 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2391 data[i] = readl(fep->hwp + fec_stats[i].offset);
2392 }
2393
fec_enet_get_strings(struct net_device * netdev,u32 stringset,u8 * data)2394 static void fec_enet_get_strings(struct net_device *netdev,
2395 u32 stringset, u8 *data)
2396 {
2397 int i;
2398 switch (stringset) {
2399 case ETH_SS_STATS:
2400 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2401 memcpy(data + i * ETH_GSTRING_LEN,
2402 fec_stats[i].name, ETH_GSTRING_LEN);
2403 break;
2404 }
2405 }
2406
fec_enet_get_sset_count(struct net_device * dev,int sset)2407 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2408 {
2409 switch (sset) {
2410 case ETH_SS_STATS:
2411 return ARRAY_SIZE(fec_stats);
2412 default:
2413 return -EOPNOTSUPP;
2414 }
2415 }
2416 #endif /* !defined(CONFIG_M5272) */
2417
fec_enet_nway_reset(struct net_device * dev)2418 static int fec_enet_nway_reset(struct net_device *dev)
2419 {
2420 struct fec_enet_private *fep = netdev_priv(dev);
2421 struct phy_device *phydev = fep->phy_dev;
2422
2423 if (!phydev)
2424 return -ENODEV;
2425
2426 return genphy_restart_aneg(phydev);
2427 }
2428
2429 /* ITR clock source is enet system clock (clk_ahb).
2430 * TCTT unit is cycle_ns * 64 cycle
2431 * So, the ICTT value = X us / (cycle_ns * 64)
2432 */
fec_enet_us_to_itr_clock(struct net_device * ndev,int us)2433 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2434 {
2435 struct fec_enet_private *fep = netdev_priv(ndev);
2436
2437 return us * (fep->itr_clk_rate / 64000) / 1000;
2438 }
2439
2440 /* Set threshold for interrupt coalescing */
fec_enet_itr_coal_set(struct net_device * ndev)2441 static void fec_enet_itr_coal_set(struct net_device *ndev)
2442 {
2443 struct fec_enet_private *fep = netdev_priv(ndev);
2444 int rx_itr, tx_itr;
2445
2446 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2447 return;
2448
2449 /* Must be greater than zero to avoid unpredictable behavior */
2450 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2451 !fep->tx_time_itr || !fep->tx_pkts_itr)
2452 return;
2453
2454 /* Select enet system clock as Interrupt Coalescing
2455 * timer Clock Source
2456 */
2457 rx_itr = FEC_ITR_CLK_SEL;
2458 tx_itr = FEC_ITR_CLK_SEL;
2459
2460 /* set ICFT and ICTT */
2461 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2462 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2463 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2464 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2465
2466 rx_itr |= FEC_ITR_EN;
2467 tx_itr |= FEC_ITR_EN;
2468
2469 writel(tx_itr, fep->hwp + FEC_TXIC0);
2470 writel(rx_itr, fep->hwp + FEC_RXIC0);
2471 writel(tx_itr, fep->hwp + FEC_TXIC1);
2472 writel(rx_itr, fep->hwp + FEC_RXIC1);
2473 writel(tx_itr, fep->hwp + FEC_TXIC2);
2474 writel(rx_itr, fep->hwp + FEC_RXIC2);
2475 }
2476
2477 static int
fec_enet_get_coalesce(struct net_device * ndev,struct ethtool_coalesce * ec)2478 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2479 {
2480 struct fec_enet_private *fep = netdev_priv(ndev);
2481
2482 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2483 return -EOPNOTSUPP;
2484
2485 ec->rx_coalesce_usecs = fep->rx_time_itr;
2486 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2487
2488 ec->tx_coalesce_usecs = fep->tx_time_itr;
2489 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2490
2491 return 0;
2492 }
2493
2494 static int
fec_enet_set_coalesce(struct net_device * ndev,struct ethtool_coalesce * ec)2495 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2496 {
2497 struct fec_enet_private *fep = netdev_priv(ndev);
2498 unsigned int cycle;
2499
2500 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2501 return -EOPNOTSUPP;
2502
2503 if (ec->rx_max_coalesced_frames > 255) {
2504 pr_err("Rx coalesced frames exceed hardware limiation");
2505 return -EINVAL;
2506 }
2507
2508 if (ec->tx_max_coalesced_frames > 255) {
2509 pr_err("Tx coalesced frame exceed hardware limiation");
2510 return -EINVAL;
2511 }
2512
2513 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2514 if (cycle > 0xFFFF) {
2515 pr_err("Rx coalesed usec exceeed hardware limiation");
2516 return -EINVAL;
2517 }
2518
2519 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2520 if (cycle > 0xFFFF) {
2521 pr_err("Rx coalesed usec exceeed hardware limiation");
2522 return -EINVAL;
2523 }
2524
2525 fep->rx_time_itr = ec->rx_coalesce_usecs;
2526 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2527
2528 fep->tx_time_itr = ec->tx_coalesce_usecs;
2529 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2530
2531 fec_enet_itr_coal_set(ndev);
2532
2533 return 0;
2534 }
2535
fec_enet_itr_coal_init(struct net_device * ndev)2536 static void fec_enet_itr_coal_init(struct net_device *ndev)
2537 {
2538 struct ethtool_coalesce ec;
2539
2540 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2541 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2542
2543 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2544 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2545
2546 fec_enet_set_coalesce(ndev, &ec);
2547 }
2548
fec_enet_get_tunable(struct net_device * netdev,const struct ethtool_tunable * tuna,void * data)2549 static int fec_enet_get_tunable(struct net_device *netdev,
2550 const struct ethtool_tunable *tuna,
2551 void *data)
2552 {
2553 struct fec_enet_private *fep = netdev_priv(netdev);
2554 int ret = 0;
2555
2556 switch (tuna->id) {
2557 case ETHTOOL_RX_COPYBREAK:
2558 *(u32 *)data = fep->rx_copybreak;
2559 break;
2560 default:
2561 ret = -EINVAL;
2562 break;
2563 }
2564
2565 return ret;
2566 }
2567
fec_enet_set_tunable(struct net_device * netdev,const struct ethtool_tunable * tuna,const void * data)2568 static int fec_enet_set_tunable(struct net_device *netdev,
2569 const struct ethtool_tunable *tuna,
2570 const void *data)
2571 {
2572 struct fec_enet_private *fep = netdev_priv(netdev);
2573 int ret = 0;
2574
2575 switch (tuna->id) {
2576 case ETHTOOL_RX_COPYBREAK:
2577 fep->rx_copybreak = *(u32 *)data;
2578 break;
2579 default:
2580 ret = -EINVAL;
2581 break;
2582 }
2583
2584 return ret;
2585 }
2586
2587 static void
fec_enet_get_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)2588 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2589 {
2590 struct fec_enet_private *fep = netdev_priv(ndev);
2591
2592 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2593 wol->supported = WAKE_MAGIC;
2594 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2595 } else {
2596 wol->supported = wol->wolopts = 0;
2597 }
2598 }
2599
2600 static int
fec_enet_set_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)2601 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2602 {
2603 struct fec_enet_private *fep = netdev_priv(ndev);
2604
2605 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2606 return -EINVAL;
2607
2608 if (wol->wolopts & ~WAKE_MAGIC)
2609 return -EINVAL;
2610
2611 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2612 if (device_may_wakeup(&ndev->dev)) {
2613 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2614 if (fep->irq[0] > 0)
2615 enable_irq_wake(fep->irq[0]);
2616 } else {
2617 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2618 if (fep->irq[0] > 0)
2619 disable_irq_wake(fep->irq[0]);
2620 }
2621
2622 return 0;
2623 }
2624
2625 static const struct ethtool_ops fec_enet_ethtool_ops = {
2626 .get_settings = fec_enet_get_settings,
2627 .set_settings = fec_enet_set_settings,
2628 .get_drvinfo = fec_enet_get_drvinfo,
2629 .get_regs_len = fec_enet_get_regs_len,
2630 .get_regs = fec_enet_get_regs,
2631 .nway_reset = fec_enet_nway_reset,
2632 .get_link = ethtool_op_get_link,
2633 .get_coalesce = fec_enet_get_coalesce,
2634 .set_coalesce = fec_enet_set_coalesce,
2635 #ifndef CONFIG_M5272
2636 .get_pauseparam = fec_enet_get_pauseparam,
2637 .set_pauseparam = fec_enet_set_pauseparam,
2638 .get_strings = fec_enet_get_strings,
2639 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2640 .get_sset_count = fec_enet_get_sset_count,
2641 #endif
2642 .get_ts_info = fec_enet_get_ts_info,
2643 .get_tunable = fec_enet_get_tunable,
2644 .set_tunable = fec_enet_set_tunable,
2645 .get_wol = fec_enet_get_wol,
2646 .set_wol = fec_enet_set_wol,
2647 };
2648
fec_enet_ioctl(struct net_device * ndev,struct ifreq * rq,int cmd)2649 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2650 {
2651 struct fec_enet_private *fep = netdev_priv(ndev);
2652 struct phy_device *phydev = fep->phy_dev;
2653
2654 if (!netif_running(ndev))
2655 return -EINVAL;
2656
2657 if (!phydev)
2658 return -ENODEV;
2659
2660 if (fep->bufdesc_ex) {
2661 if (cmd == SIOCSHWTSTAMP)
2662 return fec_ptp_set(ndev, rq);
2663 if (cmd == SIOCGHWTSTAMP)
2664 return fec_ptp_get(ndev, rq);
2665 }
2666
2667 return phy_mii_ioctl(phydev, rq, cmd);
2668 }
2669
fec_enet_free_buffers(struct net_device * ndev)2670 static void fec_enet_free_buffers(struct net_device *ndev)
2671 {
2672 struct fec_enet_private *fep = netdev_priv(ndev);
2673 unsigned int i;
2674 struct sk_buff *skb;
2675 struct bufdesc *bdp;
2676 struct fec_enet_priv_tx_q *txq;
2677 struct fec_enet_priv_rx_q *rxq;
2678 unsigned int q;
2679
2680 for (q = 0; q < fep->num_rx_queues; q++) {
2681 rxq = fep->rx_queue[q];
2682 bdp = rxq->rx_bd_base;
2683 for (i = 0; i < rxq->rx_ring_size; i++) {
2684 skb = rxq->rx_skbuff[i];
2685 rxq->rx_skbuff[i] = NULL;
2686 if (skb) {
2687 dma_unmap_single(&fep->pdev->dev,
2688 bdp->cbd_bufaddr,
2689 FEC_ENET_RX_FRSIZE - fep->rx_align,
2690 DMA_FROM_DEVICE);
2691 dev_kfree_skb(skb);
2692 }
2693 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2694 }
2695 }
2696
2697 for (q = 0; q < fep->num_tx_queues; q++) {
2698 txq = fep->tx_queue[q];
2699 bdp = txq->tx_bd_base;
2700 for (i = 0; i < txq->tx_ring_size; i++) {
2701 kfree(txq->tx_bounce[i]);
2702 txq->tx_bounce[i] = NULL;
2703 skb = txq->tx_skbuff[i];
2704 txq->tx_skbuff[i] = NULL;
2705 dev_kfree_skb(skb);
2706 }
2707 }
2708 }
2709
fec_enet_free_queue(struct net_device * ndev)2710 static void fec_enet_free_queue(struct net_device *ndev)
2711 {
2712 struct fec_enet_private *fep = netdev_priv(ndev);
2713 int i;
2714 struct fec_enet_priv_tx_q *txq;
2715
2716 for (i = 0; i < fep->num_tx_queues; i++)
2717 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2718 txq = fep->tx_queue[i];
2719 dma_free_coherent(NULL,
2720 txq->tx_ring_size * TSO_HEADER_SIZE,
2721 txq->tso_hdrs,
2722 txq->tso_hdrs_dma);
2723 }
2724
2725 for (i = 0; i < fep->num_rx_queues; i++)
2726 kfree(fep->rx_queue[i]);
2727 for (i = 0; i < fep->num_tx_queues; i++)
2728 kfree(fep->tx_queue[i]);
2729 }
2730
fec_enet_alloc_queue(struct net_device * ndev)2731 static int fec_enet_alloc_queue(struct net_device *ndev)
2732 {
2733 struct fec_enet_private *fep = netdev_priv(ndev);
2734 int i;
2735 int ret = 0;
2736 struct fec_enet_priv_tx_q *txq;
2737
2738 for (i = 0; i < fep->num_tx_queues; i++) {
2739 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2740 if (!txq) {
2741 ret = -ENOMEM;
2742 goto alloc_failed;
2743 }
2744
2745 fep->tx_queue[i] = txq;
2746 txq->tx_ring_size = TX_RING_SIZE;
2747 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2748
2749 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2750 txq->tx_wake_threshold =
2751 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2752
2753 txq->tso_hdrs = dma_alloc_coherent(NULL,
2754 txq->tx_ring_size * TSO_HEADER_SIZE,
2755 &txq->tso_hdrs_dma,
2756 GFP_KERNEL);
2757 if (!txq->tso_hdrs) {
2758 ret = -ENOMEM;
2759 goto alloc_failed;
2760 }
2761 }
2762
2763 for (i = 0; i < fep->num_rx_queues; i++) {
2764 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2765 GFP_KERNEL);
2766 if (!fep->rx_queue[i]) {
2767 ret = -ENOMEM;
2768 goto alloc_failed;
2769 }
2770
2771 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2772 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2773 }
2774 return ret;
2775
2776 alloc_failed:
2777 fec_enet_free_queue(ndev);
2778 return ret;
2779 }
2780
2781 static int
fec_enet_alloc_rxq_buffers(struct net_device * ndev,unsigned int queue)2782 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2783 {
2784 struct fec_enet_private *fep = netdev_priv(ndev);
2785 unsigned int i;
2786 struct sk_buff *skb;
2787 struct bufdesc *bdp;
2788 struct fec_enet_priv_rx_q *rxq;
2789
2790 rxq = fep->rx_queue[queue];
2791 bdp = rxq->rx_bd_base;
2792 for (i = 0; i < rxq->rx_ring_size; i++) {
2793 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2794 if (!skb)
2795 goto err_alloc;
2796
2797 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2798 dev_kfree_skb(skb);
2799 goto err_alloc;
2800 }
2801
2802 rxq->rx_skbuff[i] = skb;
2803 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2804
2805 if (fep->bufdesc_ex) {
2806 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2807 ebdp->cbd_esc = BD_ENET_RX_INT;
2808 }
2809
2810 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2811 }
2812
2813 /* Set the last buffer to wrap. */
2814 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2815 bdp->cbd_sc |= BD_SC_WRAP;
2816 return 0;
2817
2818 err_alloc:
2819 fec_enet_free_buffers(ndev);
2820 return -ENOMEM;
2821 }
2822
2823 static int
fec_enet_alloc_txq_buffers(struct net_device * ndev,unsigned int queue)2824 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2825 {
2826 struct fec_enet_private *fep = netdev_priv(ndev);
2827 unsigned int i;
2828 struct bufdesc *bdp;
2829 struct fec_enet_priv_tx_q *txq;
2830
2831 txq = fep->tx_queue[queue];
2832 bdp = txq->tx_bd_base;
2833 for (i = 0; i < txq->tx_ring_size; i++) {
2834 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2835 if (!txq->tx_bounce[i])
2836 goto err_alloc;
2837
2838 bdp->cbd_sc = 0;
2839 bdp->cbd_bufaddr = 0;
2840
2841 if (fep->bufdesc_ex) {
2842 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2843 ebdp->cbd_esc = BD_ENET_TX_INT;
2844 }
2845
2846 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2847 }
2848
2849 /* Set the last buffer to wrap. */
2850 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2851 bdp->cbd_sc |= BD_SC_WRAP;
2852
2853 return 0;
2854
2855 err_alloc:
2856 fec_enet_free_buffers(ndev);
2857 return -ENOMEM;
2858 }
2859
fec_enet_alloc_buffers(struct net_device * ndev)2860 static int fec_enet_alloc_buffers(struct net_device *ndev)
2861 {
2862 struct fec_enet_private *fep = netdev_priv(ndev);
2863 unsigned int i;
2864
2865 for (i = 0; i < fep->num_rx_queues; i++)
2866 if (fec_enet_alloc_rxq_buffers(ndev, i))
2867 return -ENOMEM;
2868
2869 for (i = 0; i < fep->num_tx_queues; i++)
2870 if (fec_enet_alloc_txq_buffers(ndev, i))
2871 return -ENOMEM;
2872 return 0;
2873 }
2874
2875 static int
fec_enet_open(struct net_device * ndev)2876 fec_enet_open(struct net_device *ndev)
2877 {
2878 struct fec_enet_private *fep = netdev_priv(ndev);
2879 int ret;
2880
2881 ret = pm_runtime_get_sync(&fep->pdev->dev);
2882 if (ret < 0)
2883 return ret;
2884
2885 pinctrl_pm_select_default_state(&fep->pdev->dev);
2886 ret = fec_enet_clk_enable(ndev, true);
2887 if (ret)
2888 goto clk_enable;
2889
2890 /* I should reset the ring buffers here, but I don't yet know
2891 * a simple way to do that.
2892 */
2893
2894 ret = fec_enet_alloc_buffers(ndev);
2895 if (ret)
2896 goto err_enet_alloc;
2897
2898 /* Init MAC prior to mii bus probe */
2899 fec_restart(ndev);
2900
2901 /* Probe and connect to PHY when open the interface */
2902 ret = fec_enet_mii_probe(ndev);
2903 if (ret)
2904 goto err_enet_mii_probe;
2905
2906 napi_enable(&fep->napi);
2907 phy_start(fep->phy_dev);
2908 netif_tx_start_all_queues(ndev);
2909
2910 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2911 FEC_WOL_FLAG_ENABLE);
2912
2913 return 0;
2914
2915 err_enet_mii_probe:
2916 fec_enet_free_buffers(ndev);
2917 err_enet_alloc:
2918 fec_enet_clk_enable(ndev, false);
2919 clk_enable:
2920 pm_runtime_mark_last_busy(&fep->pdev->dev);
2921 pm_runtime_put_autosuspend(&fep->pdev->dev);
2922 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2923 return ret;
2924 }
2925
2926 static int
fec_enet_close(struct net_device * ndev)2927 fec_enet_close(struct net_device *ndev)
2928 {
2929 struct fec_enet_private *fep = netdev_priv(ndev);
2930
2931 phy_stop(fep->phy_dev);
2932
2933 if (netif_device_present(ndev)) {
2934 napi_disable(&fep->napi);
2935 netif_tx_disable(ndev);
2936 fec_stop(ndev);
2937 }
2938
2939 phy_disconnect(fep->phy_dev);
2940 fep->phy_dev = NULL;
2941
2942 fec_enet_clk_enable(ndev, false);
2943 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2944 pm_runtime_mark_last_busy(&fep->pdev->dev);
2945 pm_runtime_put_autosuspend(&fep->pdev->dev);
2946
2947 fec_enet_free_buffers(ndev);
2948
2949 return 0;
2950 }
2951
2952 /* Set or clear the multicast filter for this adaptor.
2953 * Skeleton taken from sunlance driver.
2954 * The CPM Ethernet implementation allows Multicast as well as individual
2955 * MAC address filtering. Some of the drivers check to make sure it is
2956 * a group multicast address, and discard those that are not. I guess I
2957 * will do the same for now, but just remove the test if you want
2958 * individual filtering as well (do the upper net layers want or support
2959 * this kind of feature?).
2960 */
2961
2962 #define HASH_BITS 6 /* #bits in hash */
2963 #define CRC32_POLY 0xEDB88320
2964
set_multicast_list(struct net_device * ndev)2965 static void set_multicast_list(struct net_device *ndev)
2966 {
2967 struct fec_enet_private *fep = netdev_priv(ndev);
2968 struct netdev_hw_addr *ha;
2969 unsigned int i, bit, data, crc, tmp;
2970 unsigned char hash;
2971
2972 if (ndev->flags & IFF_PROMISC) {
2973 tmp = readl(fep->hwp + FEC_R_CNTRL);
2974 tmp |= 0x8;
2975 writel(tmp, fep->hwp + FEC_R_CNTRL);
2976 return;
2977 }
2978
2979 tmp = readl(fep->hwp + FEC_R_CNTRL);
2980 tmp &= ~0x8;
2981 writel(tmp, fep->hwp + FEC_R_CNTRL);
2982
2983 if (ndev->flags & IFF_ALLMULTI) {
2984 /* Catch all multicast addresses, so set the
2985 * filter to all 1's
2986 */
2987 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2988 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2989
2990 return;
2991 }
2992
2993 /* Clear filter and add the addresses in hash register
2994 */
2995 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2996 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2997
2998 netdev_for_each_mc_addr(ha, ndev) {
2999 /* calculate crc32 value of mac address */
3000 crc = 0xffffffff;
3001
3002 for (i = 0; i < ndev->addr_len; i++) {
3003 data = ha->addr[i];
3004 for (bit = 0; bit < 8; bit++, data >>= 1) {
3005 crc = (crc >> 1) ^
3006 (((crc ^ data) & 1) ? CRC32_POLY : 0);
3007 }
3008 }
3009
3010 /* only upper 6 bits (HASH_BITS) are used
3011 * which point to specific bit in he hash registers
3012 */
3013 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
3014
3015 if (hash > 31) {
3016 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3017 tmp |= 1 << (hash - 32);
3018 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3019 } else {
3020 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3021 tmp |= 1 << hash;
3022 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3023 }
3024 }
3025 }
3026
3027 /* Set a MAC change in hardware. */
3028 static int
fec_set_mac_address(struct net_device * ndev,void * p)3029 fec_set_mac_address(struct net_device *ndev, void *p)
3030 {
3031 struct fec_enet_private *fep = netdev_priv(ndev);
3032 struct sockaddr *addr = p;
3033
3034 if (addr) {
3035 if (!is_valid_ether_addr(addr->sa_data))
3036 return -EADDRNOTAVAIL;
3037 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3038 }
3039
3040 /* Add netif status check here to avoid system hang in below case:
3041 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3042 * After ethx down, fec all clocks are gated off and then register
3043 * access causes system hang.
3044 */
3045 if (!netif_running(ndev))
3046 return 0;
3047
3048 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3049 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3050 fep->hwp + FEC_ADDR_LOW);
3051 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3052 fep->hwp + FEC_ADDR_HIGH);
3053 return 0;
3054 }
3055
3056 #ifdef CONFIG_NET_POLL_CONTROLLER
3057 /**
3058 * fec_poll_controller - FEC Poll controller function
3059 * @dev: The FEC network adapter
3060 *
3061 * Polled functionality used by netconsole and others in non interrupt mode
3062 *
3063 */
fec_poll_controller(struct net_device * dev)3064 static void fec_poll_controller(struct net_device *dev)
3065 {
3066 int i;
3067 struct fec_enet_private *fep = netdev_priv(dev);
3068
3069 for (i = 0; i < FEC_IRQ_NUM; i++) {
3070 if (fep->irq[i] > 0) {
3071 disable_irq(fep->irq[i]);
3072 fec_enet_interrupt(fep->irq[i], dev);
3073 enable_irq(fep->irq[i]);
3074 }
3075 }
3076 }
3077 #endif
3078
fec_enet_set_netdev_features(struct net_device * netdev,netdev_features_t features)3079 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3080 netdev_features_t features)
3081 {
3082 struct fec_enet_private *fep = netdev_priv(netdev);
3083 netdev_features_t changed = features ^ netdev->features;
3084
3085 netdev->features = features;
3086
3087 /* Receive checksum has been changed */
3088 if (changed & NETIF_F_RXCSUM) {
3089 if (features & NETIF_F_RXCSUM)
3090 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3091 else
3092 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3093 }
3094 }
3095
fec_set_features(struct net_device * netdev,netdev_features_t features)3096 static int fec_set_features(struct net_device *netdev,
3097 netdev_features_t features)
3098 {
3099 struct fec_enet_private *fep = netdev_priv(netdev);
3100 netdev_features_t changed = features ^ netdev->features;
3101
3102 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3103 napi_disable(&fep->napi);
3104 netif_tx_lock_bh(netdev);
3105 fec_stop(netdev);
3106 fec_enet_set_netdev_features(netdev, features);
3107 fec_restart(netdev);
3108 netif_tx_wake_all_queues(netdev);
3109 netif_tx_unlock_bh(netdev);
3110 napi_enable(&fep->napi);
3111 } else {
3112 fec_enet_set_netdev_features(netdev, features);
3113 }
3114
3115 return 0;
3116 }
3117
3118 static const struct net_device_ops fec_netdev_ops = {
3119 .ndo_open = fec_enet_open,
3120 .ndo_stop = fec_enet_close,
3121 .ndo_start_xmit = fec_enet_start_xmit,
3122 .ndo_set_rx_mode = set_multicast_list,
3123 .ndo_change_mtu = eth_change_mtu,
3124 .ndo_validate_addr = eth_validate_addr,
3125 .ndo_tx_timeout = fec_timeout,
3126 .ndo_set_mac_address = fec_set_mac_address,
3127 .ndo_do_ioctl = fec_enet_ioctl,
3128 #ifdef CONFIG_NET_POLL_CONTROLLER
3129 .ndo_poll_controller = fec_poll_controller,
3130 #endif
3131 .ndo_set_features = fec_set_features,
3132 };
3133
3134 /*
3135 * XXX: We need to clean up on failure exits here.
3136 *
3137 */
fec_enet_init(struct net_device * ndev)3138 static int fec_enet_init(struct net_device *ndev)
3139 {
3140 struct fec_enet_private *fep = netdev_priv(ndev);
3141 struct fec_enet_priv_tx_q *txq;
3142 struct fec_enet_priv_rx_q *rxq;
3143 struct bufdesc *cbd_base;
3144 dma_addr_t bd_dma;
3145 int bd_size;
3146 unsigned int i;
3147
3148 #if defined(CONFIG_ARM)
3149 fep->rx_align = 0xf;
3150 fep->tx_align = 0xf;
3151 #else
3152 fep->rx_align = 0x3;
3153 fep->tx_align = 0x3;
3154 #endif
3155
3156 fec_enet_alloc_queue(ndev);
3157
3158 if (fep->bufdesc_ex)
3159 fep->bufdesc_size = sizeof(struct bufdesc_ex);
3160 else
3161 fep->bufdesc_size = sizeof(struct bufdesc);
3162 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
3163 fep->bufdesc_size;
3164
3165 /* Allocate memory for buffer descriptors. */
3166 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3167 GFP_KERNEL);
3168 if (!cbd_base) {
3169 return -ENOMEM;
3170 }
3171
3172 memset(cbd_base, 0, bd_size);
3173
3174 /* Get the Ethernet address */
3175 fec_get_mac(ndev);
3176 /* make sure MAC we just acquired is programmed into the hw */
3177 fec_set_mac_address(ndev, NULL);
3178
3179 /* Set receive and transmit descriptor base. */
3180 for (i = 0; i < fep->num_rx_queues; i++) {
3181 rxq = fep->rx_queue[i];
3182 rxq->index = i;
3183 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
3184 rxq->bd_dma = bd_dma;
3185 if (fep->bufdesc_ex) {
3186 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
3187 cbd_base = (struct bufdesc *)
3188 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
3189 } else {
3190 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
3191 cbd_base += rxq->rx_ring_size;
3192 }
3193 }
3194
3195 for (i = 0; i < fep->num_tx_queues; i++) {
3196 txq = fep->tx_queue[i];
3197 txq->index = i;
3198 txq->tx_bd_base = (struct bufdesc *)cbd_base;
3199 txq->bd_dma = bd_dma;
3200 if (fep->bufdesc_ex) {
3201 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
3202 cbd_base = (struct bufdesc *)
3203 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
3204 } else {
3205 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
3206 cbd_base += txq->tx_ring_size;
3207 }
3208 }
3209
3210
3211 /* The FEC Ethernet specific entries in the device structure */
3212 ndev->watchdog_timeo = TX_TIMEOUT;
3213 ndev->netdev_ops = &fec_netdev_ops;
3214 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3215
3216 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3217 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3218
3219 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3220 /* enable hw VLAN support */
3221 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3222
3223 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3224 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3225
3226 /* enable hw accelerator */
3227 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3228 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3229 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3230 }
3231
3232 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3233 fep->tx_align = 0;
3234 fep->rx_align = 0x3f;
3235 }
3236
3237 ndev->hw_features = ndev->features;
3238
3239 fec_restart(ndev);
3240
3241 return 0;
3242 }
3243
3244 #ifdef CONFIG_OF
fec_reset_phy(struct platform_device * pdev)3245 static void fec_reset_phy(struct platform_device *pdev)
3246 {
3247 int err, phy_reset;
3248 int msec = 1;
3249 struct device_node *np = pdev->dev.of_node;
3250
3251 if (!np)
3252 return;
3253
3254 of_property_read_u32(np, "phy-reset-duration", &msec);
3255 /* A sane reset duration should not be longer than 1s */
3256 if (msec > 1000)
3257 msec = 1;
3258
3259 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3260 if (!gpio_is_valid(phy_reset))
3261 return;
3262
3263 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3264 GPIOF_OUT_INIT_LOW, "phy-reset");
3265 if (err) {
3266 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3267 return;
3268 }
3269 msleep(msec);
3270 gpio_set_value_cansleep(phy_reset, 1);
3271 }
3272 #else /* CONFIG_OF */
fec_reset_phy(struct platform_device * pdev)3273 static void fec_reset_phy(struct platform_device *pdev)
3274 {
3275 /*
3276 * In case of platform probe, the reset has been done
3277 * by machine code.
3278 */
3279 }
3280 #endif /* CONFIG_OF */
3281
3282 static void
fec_enet_get_queue_num(struct platform_device * pdev,int * num_tx,int * num_rx)3283 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3284 {
3285 struct device_node *np = pdev->dev.of_node;
3286 int err;
3287
3288 *num_tx = *num_rx = 1;
3289
3290 if (!np || !of_device_is_available(np))
3291 return;
3292
3293 /* parse the num of tx and rx queues */
3294 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3295 if (err)
3296 *num_tx = 1;
3297
3298 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3299 if (err)
3300 *num_rx = 1;
3301
3302 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3303 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3304 *num_tx);
3305 *num_tx = 1;
3306 return;
3307 }
3308
3309 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3310 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3311 *num_rx);
3312 *num_rx = 1;
3313 return;
3314 }
3315
3316 }
3317
3318 static int
fec_probe(struct platform_device * pdev)3319 fec_probe(struct platform_device *pdev)
3320 {
3321 struct fec_enet_private *fep;
3322 struct fec_platform_data *pdata;
3323 struct net_device *ndev;
3324 int i, irq, ret = 0;
3325 struct resource *r;
3326 const struct of_device_id *of_id;
3327 static int dev_id;
3328 struct device_node *np = pdev->dev.of_node, *phy_node;
3329 int num_tx_qs;
3330 int num_rx_qs;
3331
3332 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3333
3334 /* Init network device */
3335 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3336 num_tx_qs, num_rx_qs);
3337 if (!ndev)
3338 return -ENOMEM;
3339
3340 SET_NETDEV_DEV(ndev, &pdev->dev);
3341
3342 /* setup board info structure */
3343 fep = netdev_priv(ndev);
3344
3345 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3346 if (of_id)
3347 pdev->id_entry = of_id->data;
3348 fep->quirks = pdev->id_entry->driver_data;
3349
3350 fep->netdev = ndev;
3351 fep->num_rx_queues = num_rx_qs;
3352 fep->num_tx_queues = num_tx_qs;
3353
3354 #if !defined(CONFIG_M5272)
3355 /* default enable pause frame auto negotiation */
3356 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3357 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3358 #endif
3359
3360 /* Select default pin state */
3361 pinctrl_pm_select_default_state(&pdev->dev);
3362
3363 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3364 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3365 if (IS_ERR(fep->hwp)) {
3366 ret = PTR_ERR(fep->hwp);
3367 goto failed_ioremap;
3368 }
3369
3370 fep->pdev = pdev;
3371 fep->dev_id = dev_id++;
3372
3373 platform_set_drvdata(pdev, ndev);
3374
3375 if (of_get_property(np, "fsl,magic-packet", NULL))
3376 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3377
3378 phy_node = of_parse_phandle(np, "phy-handle", 0);
3379 if (!phy_node && of_phy_is_fixed_link(np)) {
3380 ret = of_phy_register_fixed_link(np);
3381 if (ret < 0) {
3382 dev_err(&pdev->dev,
3383 "broken fixed-link specification\n");
3384 goto failed_phy;
3385 }
3386 phy_node = of_node_get(np);
3387 }
3388 fep->phy_node = phy_node;
3389
3390 ret = of_get_phy_mode(pdev->dev.of_node);
3391 if (ret < 0) {
3392 pdata = dev_get_platdata(&pdev->dev);
3393 if (pdata)
3394 fep->phy_interface = pdata->phy;
3395 else
3396 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3397 } else {
3398 fep->phy_interface = ret;
3399 }
3400
3401 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3402 if (IS_ERR(fep->clk_ipg)) {
3403 ret = PTR_ERR(fep->clk_ipg);
3404 goto failed_clk;
3405 }
3406
3407 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3408 if (IS_ERR(fep->clk_ahb)) {
3409 ret = PTR_ERR(fep->clk_ahb);
3410 goto failed_clk;
3411 }
3412
3413 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3414
3415 /* enet_out is optional, depends on board */
3416 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3417 if (IS_ERR(fep->clk_enet_out))
3418 fep->clk_enet_out = NULL;
3419
3420 fep->ptp_clk_on = false;
3421 mutex_init(&fep->ptp_clk_mutex);
3422
3423 /* clk_ref is optional, depends on board */
3424 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3425 if (IS_ERR(fep->clk_ref))
3426 fep->clk_ref = NULL;
3427
3428 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3429 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3430 if (IS_ERR(fep->clk_ptp)) {
3431 fep->clk_ptp = NULL;
3432 fep->bufdesc_ex = false;
3433 }
3434
3435 ret = fec_enet_clk_enable(ndev, true);
3436 if (ret)
3437 goto failed_clk;
3438
3439 ret = clk_prepare_enable(fep->clk_ipg);
3440 if (ret)
3441 goto failed_clk_ipg;
3442
3443 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3444 if (!IS_ERR(fep->reg_phy)) {
3445 ret = regulator_enable(fep->reg_phy);
3446 if (ret) {
3447 dev_err(&pdev->dev,
3448 "Failed to enable phy regulator: %d\n", ret);
3449 goto failed_regulator;
3450 }
3451 } else {
3452 fep->reg_phy = NULL;
3453 }
3454
3455 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3456 pm_runtime_use_autosuspend(&pdev->dev);
3457 pm_runtime_get_noresume(&pdev->dev);
3458 pm_runtime_set_active(&pdev->dev);
3459 pm_runtime_enable(&pdev->dev);
3460
3461 fec_reset_phy(pdev);
3462
3463 if (fep->bufdesc_ex)
3464 fec_ptp_init(pdev);
3465
3466 ret = fec_enet_init(ndev);
3467 if (ret)
3468 goto failed_init;
3469
3470 for (i = 0; i < FEC_IRQ_NUM; i++) {
3471 irq = platform_get_irq(pdev, i);
3472 if (irq < 0) {
3473 if (i)
3474 break;
3475 ret = irq;
3476 goto failed_irq;
3477 }
3478 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3479 0, pdev->name, ndev);
3480 if (ret)
3481 goto failed_irq;
3482
3483 fep->irq[i] = irq;
3484 }
3485
3486 init_completion(&fep->mdio_done);
3487 ret = fec_enet_mii_init(pdev);
3488 if (ret)
3489 goto failed_mii_init;
3490
3491 /* Carrier starts down, phylib will bring it up */
3492 netif_carrier_off(ndev);
3493 fec_enet_clk_enable(ndev, false);
3494 pinctrl_pm_select_sleep_state(&pdev->dev);
3495
3496 ret = register_netdev(ndev);
3497 if (ret)
3498 goto failed_register;
3499
3500 device_init_wakeup(&ndev->dev, fep->wol_flag &
3501 FEC_WOL_HAS_MAGIC_PACKET);
3502
3503 if (fep->bufdesc_ex && fep->ptp_clock)
3504 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3505
3506 fep->rx_copybreak = COPYBREAK_DEFAULT;
3507 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3508
3509 pm_runtime_mark_last_busy(&pdev->dev);
3510 pm_runtime_put_autosuspend(&pdev->dev);
3511
3512 return 0;
3513
3514 failed_register:
3515 fec_enet_mii_remove(fep);
3516 failed_mii_init:
3517 failed_irq:
3518 failed_init:
3519 fec_ptp_stop(pdev);
3520 if (fep->reg_phy)
3521 regulator_disable(fep->reg_phy);
3522 failed_regulator:
3523 clk_disable_unprepare(fep->clk_ipg);
3524 failed_clk_ipg:
3525 fec_enet_clk_enable(ndev, false);
3526 failed_clk:
3527 failed_phy:
3528 of_node_put(phy_node);
3529 failed_ioremap:
3530 free_netdev(ndev);
3531
3532 return ret;
3533 }
3534
3535 static int
fec_drv_remove(struct platform_device * pdev)3536 fec_drv_remove(struct platform_device *pdev)
3537 {
3538 struct net_device *ndev = platform_get_drvdata(pdev);
3539 struct fec_enet_private *fep = netdev_priv(ndev);
3540
3541 cancel_work_sync(&fep->tx_timeout_work);
3542 fec_ptp_stop(pdev);
3543 unregister_netdev(ndev);
3544 fec_enet_mii_remove(fep);
3545 if (fep->reg_phy)
3546 regulator_disable(fep->reg_phy);
3547 of_node_put(fep->phy_node);
3548 free_netdev(ndev);
3549
3550 return 0;
3551 }
3552
fec_suspend(struct device * dev)3553 static int __maybe_unused fec_suspend(struct device *dev)
3554 {
3555 struct net_device *ndev = dev_get_drvdata(dev);
3556 struct fec_enet_private *fep = netdev_priv(ndev);
3557
3558 rtnl_lock();
3559 if (netif_running(ndev)) {
3560 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3561 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3562 phy_stop(fep->phy_dev);
3563 napi_disable(&fep->napi);
3564 netif_tx_lock_bh(ndev);
3565 netif_device_detach(ndev);
3566 netif_tx_unlock_bh(ndev);
3567 fec_stop(ndev);
3568 fec_enet_clk_enable(ndev, false);
3569 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3570 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3571 }
3572 rtnl_unlock();
3573
3574 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3575 regulator_disable(fep->reg_phy);
3576
3577 /* SOC supply clock to phy, when clock is disabled, phy link down
3578 * SOC control phy regulator, when regulator is disabled, phy link down
3579 */
3580 if (fep->clk_enet_out || fep->reg_phy)
3581 fep->link = 0;
3582
3583 return 0;
3584 }
3585
fec_resume(struct device * dev)3586 static int __maybe_unused fec_resume(struct device *dev)
3587 {
3588 struct net_device *ndev = dev_get_drvdata(dev);
3589 struct fec_enet_private *fep = netdev_priv(ndev);
3590 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3591 int ret;
3592 int val;
3593
3594 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3595 ret = regulator_enable(fep->reg_phy);
3596 if (ret)
3597 return ret;
3598 }
3599
3600 rtnl_lock();
3601 if (netif_running(ndev)) {
3602 ret = fec_enet_clk_enable(ndev, true);
3603 if (ret) {
3604 rtnl_unlock();
3605 goto failed_clk;
3606 }
3607 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3608 if (pdata && pdata->sleep_mode_enable)
3609 pdata->sleep_mode_enable(false);
3610 val = readl(fep->hwp + FEC_ECNTRL);
3611 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3612 writel(val, fep->hwp + FEC_ECNTRL);
3613 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3614 } else {
3615 pinctrl_pm_select_default_state(&fep->pdev->dev);
3616 }
3617 fec_restart(ndev);
3618 netif_tx_lock_bh(ndev);
3619 netif_device_attach(ndev);
3620 netif_tx_unlock_bh(ndev);
3621 napi_enable(&fep->napi);
3622 phy_start(fep->phy_dev);
3623 }
3624 rtnl_unlock();
3625
3626 return 0;
3627
3628 failed_clk:
3629 if (fep->reg_phy)
3630 regulator_disable(fep->reg_phy);
3631 return ret;
3632 }
3633
fec_runtime_suspend(struct device * dev)3634 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3635 {
3636 struct net_device *ndev = dev_get_drvdata(dev);
3637 struct fec_enet_private *fep = netdev_priv(ndev);
3638
3639 clk_disable_unprepare(fep->clk_ipg);
3640
3641 return 0;
3642 }
3643
fec_runtime_resume(struct device * dev)3644 static int __maybe_unused fec_runtime_resume(struct device *dev)
3645 {
3646 struct net_device *ndev = dev_get_drvdata(dev);
3647 struct fec_enet_private *fep = netdev_priv(ndev);
3648
3649 return clk_prepare_enable(fep->clk_ipg);
3650 }
3651
3652 static const struct dev_pm_ops fec_pm_ops = {
3653 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3654 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3655 };
3656
3657 static struct platform_driver fec_driver = {
3658 .driver = {
3659 .name = DRIVER_NAME,
3660 .pm = &fec_pm_ops,
3661 .of_match_table = fec_dt_ids,
3662 },
3663 .id_table = fec_devtype,
3664 .probe = fec_probe,
3665 .remove = fec_drv_remove,
3666 };
3667
3668 module_platform_driver(fec_driver);
3669
3670 MODULE_ALIAS("platform:"DRIVER_NAME);
3671 MODULE_LICENSE("GPL");
3672