1/* bnx2x_hsi.h: Qlogic Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * Copyright (c) 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 */ 11#ifndef BNX2X_HSI_H 12#define BNX2X_HSI_H 13 14#include "bnx2x_fw_defs.h" 15#include "bnx2x_mfw_req.h" 16 17#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 18 19struct license_key { 20 u32 reserved[6]; 21 22 u32 max_iscsi_conn; 23#define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 24#define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 25#define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 26#define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16 27 28 u32 reserved_a; 29 30 u32 max_fcoe_conn; 31#define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 32#define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 33#define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 34#define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16 35 36 u32 reserved_b[4]; 37}; 38 39/**************************************************************************** 40 * Shared HW configuration * 41 ****************************************************************************/ 42#define PIN_CFG_NA 0x00000000 43#define PIN_CFG_GPIO0_P0 0x00000001 44#define PIN_CFG_GPIO1_P0 0x00000002 45#define PIN_CFG_GPIO2_P0 0x00000003 46#define PIN_CFG_GPIO3_P0 0x00000004 47#define PIN_CFG_GPIO0_P1 0x00000005 48#define PIN_CFG_GPIO1_P1 0x00000006 49#define PIN_CFG_GPIO2_P1 0x00000007 50#define PIN_CFG_GPIO3_P1 0x00000008 51#define PIN_CFG_EPIO0 0x00000009 52#define PIN_CFG_EPIO1 0x0000000a 53#define PIN_CFG_EPIO2 0x0000000b 54#define PIN_CFG_EPIO3 0x0000000c 55#define PIN_CFG_EPIO4 0x0000000d 56#define PIN_CFG_EPIO5 0x0000000e 57#define PIN_CFG_EPIO6 0x0000000f 58#define PIN_CFG_EPIO7 0x00000010 59#define PIN_CFG_EPIO8 0x00000011 60#define PIN_CFG_EPIO9 0x00000012 61#define PIN_CFG_EPIO10 0x00000013 62#define PIN_CFG_EPIO11 0x00000014 63#define PIN_CFG_EPIO12 0x00000015 64#define PIN_CFG_EPIO13 0x00000016 65#define PIN_CFG_EPIO14 0x00000017 66#define PIN_CFG_EPIO15 0x00000018 67#define PIN_CFG_EPIO16 0x00000019 68#define PIN_CFG_EPIO17 0x0000001a 69#define PIN_CFG_EPIO18 0x0000001b 70#define PIN_CFG_EPIO19 0x0000001c 71#define PIN_CFG_EPIO20 0x0000001d 72#define PIN_CFG_EPIO21 0x0000001e 73#define PIN_CFG_EPIO22 0x0000001f 74#define PIN_CFG_EPIO23 0x00000020 75#define PIN_CFG_EPIO24 0x00000021 76#define PIN_CFG_EPIO25 0x00000022 77#define PIN_CFG_EPIO26 0x00000023 78#define PIN_CFG_EPIO27 0x00000024 79#define PIN_CFG_EPIO28 0x00000025 80#define PIN_CFG_EPIO29 0x00000026 81#define PIN_CFG_EPIO30 0x00000027 82#define PIN_CFG_EPIO31 0x00000028 83 84/* EPIO definition */ 85#define EPIO_CFG_NA 0x00000000 86#define EPIO_CFG_EPIO0 0x00000001 87#define EPIO_CFG_EPIO1 0x00000002 88#define EPIO_CFG_EPIO2 0x00000003 89#define EPIO_CFG_EPIO3 0x00000004 90#define EPIO_CFG_EPIO4 0x00000005 91#define EPIO_CFG_EPIO5 0x00000006 92#define EPIO_CFG_EPIO6 0x00000007 93#define EPIO_CFG_EPIO7 0x00000008 94#define EPIO_CFG_EPIO8 0x00000009 95#define EPIO_CFG_EPIO9 0x0000000a 96#define EPIO_CFG_EPIO10 0x0000000b 97#define EPIO_CFG_EPIO11 0x0000000c 98#define EPIO_CFG_EPIO12 0x0000000d 99#define EPIO_CFG_EPIO13 0x0000000e 100#define EPIO_CFG_EPIO14 0x0000000f 101#define EPIO_CFG_EPIO15 0x00000010 102#define EPIO_CFG_EPIO16 0x00000011 103#define EPIO_CFG_EPIO17 0x00000012 104#define EPIO_CFG_EPIO18 0x00000013 105#define EPIO_CFG_EPIO19 0x00000014 106#define EPIO_CFG_EPIO20 0x00000015 107#define EPIO_CFG_EPIO21 0x00000016 108#define EPIO_CFG_EPIO22 0x00000017 109#define EPIO_CFG_EPIO23 0x00000018 110#define EPIO_CFG_EPIO24 0x00000019 111#define EPIO_CFG_EPIO25 0x0000001a 112#define EPIO_CFG_EPIO26 0x0000001b 113#define EPIO_CFG_EPIO27 0x0000001c 114#define EPIO_CFG_EPIO28 0x0000001d 115#define EPIO_CFG_EPIO29 0x0000001e 116#define EPIO_CFG_EPIO30 0x0000001f 117#define EPIO_CFG_EPIO31 0x00000020 118 119struct mac_addr { 120 u32 upper; 121 u32 lower; 122}; 123 124struct shared_hw_cfg { /* NVRAM Offset */ 125 /* Up to 16 bytes of NULL-terminated string */ 126 u8 part_num[16]; /* 0x104 */ 127 128 u32 config; /* 0x114 */ 129 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 130 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 131 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 132 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 133 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 134 135 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 136 137 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 138 139 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 140 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 141 142 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 143 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 144 /* Whatever MFW found in NVM 145 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 146 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 147 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 148 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 149 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 150 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 151 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 152 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 153 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 154 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 155 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 156 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 157 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 158 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 159 160 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 161 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 162 #define SHARED_HW_CFG_LED_MAC1 0x00000000 163 #define SHARED_HW_CFG_LED_PHY1 0x00010000 164 #define SHARED_HW_CFG_LED_PHY2 0x00020000 165 #define SHARED_HW_CFG_LED_PHY3 0x00030000 166 #define SHARED_HW_CFG_LED_MAC2 0x00040000 167 #define SHARED_HW_CFG_LED_PHY4 0x00050000 168 #define SHARED_HW_CFG_LED_PHY5 0x00060000 169 #define SHARED_HW_CFG_LED_PHY6 0x00070000 170 #define SHARED_HW_CFG_LED_MAC3 0x00080000 171 #define SHARED_HW_CFG_LED_PHY7 0x00090000 172 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 173 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 174 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 175 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 176 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 177 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000 178 179 180 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 181 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 182 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 183 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 184 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 185 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 186 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 187 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 188 189 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 190 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 191 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 192 193 #define SHARED_HW_CFG_ATC_MASK 0x80000000 194 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 195 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 196 197 u32 config2; /* 0x118 */ 198 /* one time auto detect grace period (in sec) */ 199 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff 200 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 201 202 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 203 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 204 205 /* The default value for the core clock is 250MHz and it is 206 achieved by setting the clock change to 4 */ 207 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 208 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 209 210 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 211 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 212 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 213 214 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 215 216 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000 217 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000 218 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000 219 220 /* Output low when PERST is asserted */ 221 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 222 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 223 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 224 225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 228 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 229 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 230 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 231 232 /* The fan failure mechanism is usually related to the PHY type 233 since the power consumption of the board is determined by the PHY. 234 Currently, fan is required for most designs with SFX7101, BCM8727 235 and BCM8481. If a fan is not required for a board which uses one 236 of those PHYs, this field should be set to "Disabled". If a fan is 237 required for a different PHY type, this option should be set to 238 "Enabled". The fan failure indication is expected on SPIO5 */ 239 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 240 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 241 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 242 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 243 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 244 245 /* ASPM Power Management support */ 246 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 247 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 248 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 249 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 250 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 251 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 252 253 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 254 tl_control_0 (register 0x2800) */ 255 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 256 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 257 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 258 259 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000 260 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000 261 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000 262 263 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000 264 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000 265 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000 266 267 /* Set the MDC/MDIO access for the first external phy */ 268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 273 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 275 276 /* Set the MDC/MDIO access for the second external phy */ 277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 282 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 283 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 284 285 u32 config_3; /* 0x11C */ 286 #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00 287 #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8 288 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000 289 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100 290 291 u32 ump_nc_si_config; /* 0x120 */ 292 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 293 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 294 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 298 299 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 300 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 301 302 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 303 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 304 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 305 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 306 307 u32 board; /* 0x124 */ 308 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 309 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 310 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 311 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 312 /* Use the PIN_CFG_XXX defines on top */ 313 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 314 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 315 316 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000 317 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 318 319 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000 320 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 321 322 u32 wc_lane_config; /* 0x128 */ 323 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 324 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 325 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 326 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 327 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 328 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 329 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 330 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 331 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 332 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 333 334 /* TX lane Polarity swap */ 335 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 336 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 337 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 338 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 339 /* TX lane Polarity swap */ 340 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 341 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 342 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 343 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 344 345 /* Selects the port layout of the board */ 346 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 347 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 348 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 354}; 355 356 357/**************************************************************************** 358 * Port HW configuration * 359 ****************************************************************************/ 360struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 361 362 u32 pci_id; 363 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 364 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff 365 366 u32 pci_sub_id; 367 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 368 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff 369 370 u32 power_dissipated; 371 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff 372 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 373 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 374 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 375 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 376 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 377 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 378 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 379 380 u32 power_consumed; 381 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff 382 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 383 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 384 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 385 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 386 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 387 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 388 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 389 390 u32 mac_upper; 391 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff 392 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 393 u32 mac_lower; 394 395 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 396 u32 iscsi_mac_lower; 397 398 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ 399 u32 rdma_mac_lower; 400 401 u32 serdes_config; 402 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff 403 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 404 405 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000 406 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 407 408 409 /* Default values: 2P-64, 4P-32 */ 410 u32 pf_config; /* 0x158 */ 411 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F 412 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0 413 414 /* Default values: 17 */ 415 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00 416 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8 417 418 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000 419 #define PORT_HW_CFG_FLR_ENABLED 0x00010000 420 421 u32 vf_config; /* 0x15C */ 422 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F 423 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0 424 425 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 426 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 427 428 u32 mf_pci_id; /* 0x160 */ 429 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 430 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 431 432 /* Controls the TX laser of the SFP+ module */ 433 u32 sfp_ctrl; /* 0x164 */ 434 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 435 #define PORT_HW_CFG_TX_LASER_SHIFT 0 436 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 437 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 438 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 439 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 440 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 441 442 /* Controls the fault module LED of the SFP+ */ 443 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 444 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 445 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 446 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 447 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 449 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 450 451 /* The output pin TX_DIS that controls the TX laser of the SFP+ 452 module. Use the PIN_CFG_XXX defines on top */ 453 u32 e3_sfp_ctrl; /* 0x168 */ 454 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 455 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 456 457 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 458 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 459 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 460 461 /* The input pin MOD_ABS that indicates whether SFP+ module is 462 present or not. Use the PIN_CFG_XXX defines on top */ 463 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 464 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 465 466 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 467 module. Use the PIN_CFG_XXX defines on top */ 468 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 469 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 470 471 /* 472 * The input pin which signals module transmit fault. Use the 473 * PIN_CFG_XXX defines on top 474 */ 475 u32 e3_cmn_pin_cfg; /* 0x16C */ 476 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 477 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 478 479 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 480 top */ 481 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 482 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 483 484 /* 485 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 486 * defines on top 487 */ 488 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 489 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 490 491 /* The output pin values BSC_SEL which selects the I2C for this port 492 in the I2C Mux */ 493 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 494 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 495 496 497 /* 498 * The input pin I_FAULT which indicate over-current has occurred. 499 * Use the PIN_CFG_XXX defines on top 500 */ 501 u32 e3_cmn_pin_cfg1; /* 0x170 */ 502 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 503 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 504 505 /* pause on host ring */ 506 u32 generic_features; /* 0x174 */ 507 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 508 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 509 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 510 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 511 512 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 513 * LOM recommended and tested value is 0xBEB2. Using a different 514 * value means using a value not tested by BRCM 515 */ 516 u32 sfi_tap_values; /* 0x178 */ 517 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF 518 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 519 520 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested 521 * value is 0x2. LOM recommended and tested value is 0x2. Using a 522 * different value means using a value not tested by BRCM 523 */ 524 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 525 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 526 /* Set non-default values for TXFIR in SFP mode. */ 527 #define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000 528 #define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20 529 530 /* Set non-default values for IPREDRIVER in SFP mode. */ 531 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000 532 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT 24 533 534 /* Set non-default values for POST2 in SFP mode. */ 535 #define PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000 536 #define PORT_HW_CFG_TX_DRV_POST2_SHIFT 28 537 538 u32 reserved0[5]; /* 0x17c */ 539 540 u32 aeu_int_mask; /* 0x190 */ 541 542 u32 media_type; /* 0x194 */ 543 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 544 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 545 546 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 547 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 548 549 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 550 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 551 552 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 553 (not direct mode), those values will not take effect on the 4 XGXS 554 lanes. For some external PHYs (such as 8706 and 8726) the values 555 will be used to configure the external PHY in those cases, not 556 all 4 values are needed. */ 557 u16 xgxs_config_rx[4]; /* 0x198 */ 558 u16 xgxs_config_tx[4]; /* 0x1A0 */ 559 560 /* For storing FCOE mac on shared memory */ 561 u32 fcoe_fip_mac_upper; 562 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 563 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 564 u32 fcoe_fip_mac_lower; 565 566 u32 fcoe_wwn_port_name_upper; 567 u32 fcoe_wwn_port_name_lower; 568 569 u32 fcoe_wwn_node_name_upper; 570 u32 fcoe_wwn_node_name_lower; 571 572 u32 Reserved1[49]; /* 0x1C0 */ 573 574 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 575 84833 only */ 576 u32 xgbt_phy_cfg; /* 0x284 */ 577 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 578 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 579 580 u32 default_cfg; /* 0x288 */ 581 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 582 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 583 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 584 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 585 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 586 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 587 588 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 589 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 590 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 591 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 592 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 593 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 594 595 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 596 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 597 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 598 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 599 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 600 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 601 602 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 603 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 604 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 605 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 606 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 607 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 608 609 /* When KR link is required to be set to force which is not 610 KR-compliant, this parameter determine what is the trigger for it. 611 When GPIO is selected, low input will force the speed. Currently 612 default speed is 1G. In the future, it may be widen to select the 613 forced speed in with another parameter. Note when force-1G is 614 enabled, it override option 56: Link Speed option. */ 615 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 616 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 617 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 618 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 619 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 620 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 621 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 622 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 623 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 624 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 625 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 626 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 627 /* Enable to determine with which GPIO to reset the external phy */ 628 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 629 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 630 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 631 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 632 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 633 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 634 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 635 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 636 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 637 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 638 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 639 640 /* Enable BAM on KR */ 641 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 642 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 643 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 644 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 645 646 /* Enable Common Mode Sense */ 647 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 648 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 649 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 650 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 651 652 /* Determine the Serdes electrical interface */ 653 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 654 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 655 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 656 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 657 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 658 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 659 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 660 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 661 662 663 u32 speed_capability_mask2; /* 0x28C */ 664 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 665 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 666 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 667 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 668 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 669 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 670 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 671 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 672 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 673 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 674 675 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 676 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 677 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 678 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 679 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 680 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 681 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 682 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 683 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 684 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 685 686 687 /* In the case where two media types (e.g. copper and fiber) are 688 present and electrically active at the same time, PHY Selection 689 will determine which of the two PHYs will be designated as the 690 Active PHY and used for a connection to the network. */ 691 u32 multi_phy_config; /* 0x290 */ 692 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 693 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 694 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 695 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 696 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 697 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 698 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 699 700 /* When enabled, all second phy nvram parameters will be swapped 701 with the first phy parameters */ 702 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 703 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 704 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 705 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 706 707 708 /* Address of the second external phy */ 709 u32 external_phy_config2; /* 0x294 */ 710 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 711 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 712 713 /* The second XGXS external PHY type */ 714 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 715 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 716 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 717 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 718 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 719 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 720 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 721 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 722 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 723 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 724 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 725 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 726 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 727 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 728 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 729 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 730 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 731 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 732 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 733 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 734 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84858 0x00001200 735 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 736 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 737 738 739 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 740 8706, 8726 and 8727) not all 4 values are needed. */ 741 u16 xgxs_config2_rx[4]; /* 0x296 */ 742 u16 xgxs_config2_tx[4]; /* 0x2A0 */ 743 744 u32 lane_config; 745 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff 746 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 747 /* AN and forced */ 748 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 749 /* forced only */ 750 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 751 /* forced only */ 752 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 753 /* forced only */ 754 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 755 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff 756 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 757 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 758 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 759 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 760 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 761 762 /* Indicate whether to swap the external phy polarity */ 763 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 764 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 765 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 766 767 768 u32 external_phy_config; 769 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff 770 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 771 772 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 773 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 774 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 775 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 776 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 777 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 778 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 779 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 780 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 781 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 782 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 783 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 784 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 785 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 786 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 787 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 788 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 789 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 790 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 791 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 792 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858 0x00001200 793 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 794 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 795 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 796 797 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 798 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 799 800 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 801 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 802 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 803 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 804 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 805 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 806 807 u32 speed_capability_mask; 808 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff 809 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 810 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 811 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 812 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 813 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 814 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 815 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 816 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 817 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 818 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 819 820 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 821 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 822 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 823 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 824 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 825 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 826 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 827 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 828 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 829 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 830 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 831 832 /* A place to hold the original MAC address as a backup */ 833 u32 backup_mac_upper; /* 0x2B4 */ 834 u32 backup_mac_lower; /* 0x2B8 */ 835 836}; 837 838 839/**************************************************************************** 840 * Shared Feature configuration * 841 ****************************************************************************/ 842struct shared_feat_cfg { /* NVRAM Offset */ 843 844 u32 config; /* 0x450 */ 845 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 846 847 /* Use NVRAM values instead of HW default values */ 848 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 849 0x00000002 850 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 851 0x00000000 852 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 853 0x00000002 854 855 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 856 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 857 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 858 859 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 860 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 861 862 /* Override the OTP back to single function mode. When using GPIO, 863 high means only SF, 0 is according to CLP configuration */ 864 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 865 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 866 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 867 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 868 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 869 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 870 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 871 #define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500 872 #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600 873 #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700 874 875 /* The interval in seconds between sending LLDP packets. Set to zero 876 to disable the feature */ 877 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000 878 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 879 880 /* The assigned device type ID for LLDP usage */ 881 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000 882 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 883 884}; 885 886 887/**************************************************************************** 888 * Port Feature configuration * 889 ****************************************************************************/ 890struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 891 892 u32 config; 893 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f 894 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 895 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 896 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 897 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 898 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 899 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 900 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 901 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 902 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 903 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 904 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 905 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a 906 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b 907 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c 908 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d 909 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e 910 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f 911 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 912 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 913 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 914 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 915 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 916 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 917 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 918 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 919 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 920 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 921 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 922 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 923 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 924 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 925 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 926 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 927 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 928 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 929 930 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 931 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 932 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 933 934 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 935 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 936 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 937 938 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 939 #define PORT_FEATURE_EN_SIZE_SHIFT 24 940 #define PORT_FEATURE_WOL_ENABLED 0x01000000 941 #define PORT_FEATURE_MBA_ENABLED 0x02000000 942 #define PORT_FEATURE_MFW_ENABLED 0x04000000 943 944 /* Advertise expansion ROM even if MBA is disabled */ 945 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 946 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 947 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 948 949 /* Check the optic vendor via i2c against a list of approved modules 950 in a separate nvram image */ 951 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000 952 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 953 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 954 0x00000000 955 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 956 0x20000000 957 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 958 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 959 960 u32 wol_config; 961 /* Default is used when driver sets to "auto" mode */ 962 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 963 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 964 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 965 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 966 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 967 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 968 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 969 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 970 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 971 972 u32 mba_config; 973 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 974 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 975 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 976 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 977 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 978 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 979 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 980 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 981 982 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 983 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 984 985 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 986 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 987 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 988 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 989 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 990 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 991 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 992 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 993 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 994 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 995 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 996 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 997 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 998 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 999 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 1000 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 1001 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 1002 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 1003 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 1004 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 1005 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 1006 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 1007 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 1008 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 1009 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 1010 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 1011 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 1012 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 1013 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 1014 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 1015 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 1016 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 1017 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 1018 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 1019 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 1020 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 1021 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 1022 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 1023 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 1024 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 1025 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 1026 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 1027 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000 1028 u32 bmc_config; 1029 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001 1030 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 1031 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 1032 1033 u32 mba_vlan_cfg; 1034 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff 1035 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1036 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1037 1038 u32 resource_cfg; 1039 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 1040 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 1041 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 1042 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 1043 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 1044 1045 u32 smbus_config; 1046 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1047 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1048 1049 u32 vf_config; 1050 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f 1051 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1052 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1053 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1054 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1055 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1056 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1057 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1058 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1059 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1060 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1061 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1062 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1063 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1064 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1065 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1066 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1067 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1068 1069 u32 link_config; /* Used as HW defaults for the driver */ 1070 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1071 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1072 /* (forced) low speed switch (< 10G) */ 1073 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1074 /* (forced) high speed switch (>= 10G) */ 1075 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1076 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1077 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1078 1079 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 1080 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1081 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1082 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 1083 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 1084 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1085 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1086 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1087 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1088 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1089 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1090 1091 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1092 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1093 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1094 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1095 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1096 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1097 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1098 1099 /* The default for MCP link configuration, 1100 uses the same defines as link_config */ 1101 u32 mfw_wol_link_cfg; 1102 1103 /* The default for the driver of the second external phy, 1104 uses the same defines as link_config */ 1105 u32 link_config2; /* 0x47C */ 1106 1107 /* The default for MCP of the second external phy, 1108 uses the same defines as link_config */ 1109 u32 mfw_wol_link_cfg2; /* 0x480 */ 1110 1111 1112 /* EEE power saving mode */ 1113 u32 eee_power_mode; /* 0x484 */ 1114 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1115 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1116 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1117 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1118 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1119 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1120 1121 1122 u32 Reserved2[16]; /* 0x488 */ 1123}; 1124 1125 1126/**************************************************************************** 1127 * Device Information * 1128 ****************************************************************************/ 1129struct shm_dev_info { /* size */ 1130 1131 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1132 1133 struct shared_hw_cfg shared_hw_config; /* 40 */ 1134 1135 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1136 1137 struct shared_feat_cfg shared_feature_config; /* 4 */ 1138 1139 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1140 1141}; 1142 1143 1144#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1145 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1146#endif 1147 1148#define FUNC_0 0 1149#define FUNC_1 1 1150#define FUNC_2 2 1151#define FUNC_3 3 1152#define FUNC_4 4 1153#define FUNC_5 5 1154#define FUNC_6 6 1155#define FUNC_7 7 1156#define E1_FUNC_MAX 2 1157#define E1H_FUNC_MAX 8 1158#define E2_FUNC_MAX 4 /* per path */ 1159 1160#define VN_0 0 1161#define VN_1 1 1162#define VN_2 2 1163#define VN_3 3 1164#define E1VN_MAX 1 1165#define E1HVN_MAX 4 1166 1167#define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1168/* This value (in milliseconds) determines the frequency of the driver 1169 * issuing the PULSE message code. The firmware monitors this periodic 1170 * pulse to determine when to switch to an OS-absent mode. */ 1171#define DRV_PULSE_PERIOD_MS 250 1172 1173/* This value (in milliseconds) determines how long the driver should 1174 * wait for an acknowledgement from the firmware before timing out. Once 1175 * the firmware has timed out, the driver will assume there is no firmware 1176 * running and there won't be any firmware-driver synchronization during a 1177 * driver reset. */ 1178#define FW_ACK_TIME_OUT_MS 5000 1179 1180#define FW_ACK_POLL_TIME_MS 1 1181 1182#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1183 1184#define MFW_TRACE_SIGNATURE 0x54524342 1185 1186/**************************************************************************** 1187 * Driver <-> FW Mailbox * 1188 ****************************************************************************/ 1189struct drv_port_mb { 1190 1191 u32 link_status; 1192 /* Driver should update this field on any link change event */ 1193 1194 #define LINK_STATUS_NONE (0<<0) 1195 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1196 #define LINK_STATUS_LINK_UP 0x00000001 1197 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1198 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1199 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1200 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1201 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1202 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1203 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1204 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1205 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1206 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1207 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1208 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1209 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1210 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1211 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1212 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1213 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1214 1215 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1216 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1217 1218 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1219 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1220 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1221 1222 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1223 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1224 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1225 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1226 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1227 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1228 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1229 1230 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1231 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1232 1233 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1234 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1235 1236 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1237 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1238 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1239 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1240 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1241 1242 #define LINK_STATUS_SERDES_LINK 0x00100000 1243 1244 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1245 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1246 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1247 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1248 1249 #define LINK_STATUS_PFC_ENABLED 0x20000000 1250 1251 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1252 #define LINK_STATUS_SFP_TX_FAULT 0x80000000 1253 1254 u32 port_stx; 1255 1256 u32 stat_nig_timer; 1257 1258 /* MCP firmware does not use this field */ 1259 u32 ext_phy_fw_version; 1260 1261}; 1262 1263 1264struct drv_func_mb { 1265 1266 u32 drv_mb_header; 1267 #define DRV_MSG_CODE_MASK 0xffff0000 1268 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1269 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1270 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1271 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1272 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1273 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1274 #define DRV_MSG_CODE_DCC_OK 0x30000000 1275 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1276 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1277 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1278 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1279 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1280 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1281 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1282 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1283 #define DRV_MSG_CODE_OEM_OK 0x00010000 1284 #define DRV_MSG_CODE_OEM_FAILURE 0x00020000 1285 #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000 1286 #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000 1287 /* 1288 * The optic module verification command requires bootcode 1289 * v5.0.6 or later, te specific optic module verification command 1290 * requires bootcode v5.2.12 or later 1291 */ 1292 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1293 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1294 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1295 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1296 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 1297 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 1298 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1299 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 1300 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1301 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 1302 1303 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1304 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1305 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 1306 1307 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1308 1309 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 1310 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 1311 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 1312 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 1313 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 1314 1315 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1316 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1317 1318 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 1319 1320 #define DRV_MSG_CODE_RMMOD 0xdb000000 1321 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f 1322 1323 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1324 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1325 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1326 1327 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1328 1329 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 1330 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 1331 1332 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1333 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1334 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1335 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1336 1337 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1338 1339 u32 drv_mb_param; 1340 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1341 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1342 1343 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 1344 1345 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a 1346 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000 1347 1348 u32 fw_mb_header; 1349 #define FW_MSG_CODE_MASK 0xffff0000 1350 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1351 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1352 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1353 /* Load common chip is supported from bc 6.0.0 */ 1354 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1355 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1356 1357 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1358 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1359 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1360 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1361 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1362 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1363 #define FW_MSG_CODE_DCC_DONE 0x30100000 1364 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1365 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1366 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1367 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1368 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1369 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1370 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1371 #define FW_MSG_CODE_NO_KEY 0x80f00000 1372 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1373 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1374 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1375 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1376 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1377 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1378 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1379 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1380 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1381 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1382 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 1383 1384 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 1385 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 1386 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 1387 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 1388 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 1389 1390 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1391 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1392 1393 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 1394 1395 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000 1396 1397 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1398 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1399 1400 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1401 1402 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1403 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1404 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1405 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1406 1407 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1408 1409 u32 fw_mb_param; 1410 1411 u32 drv_pulse_mb; 1412 #define DRV_PULSE_SEQ_MASK 0x00007fff 1413 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1414 /* 1415 * The system time is in the format of 1416 * (year-2001)*12*32 + month*32 + day. 1417 */ 1418 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1419 /* 1420 * Indicate to the firmware not to go into the 1421 * OS-absent when it is not getting driver pulse. 1422 * This is used for debugging as well for PXE(MBA). 1423 */ 1424 1425 u32 mcp_pulse_mb; 1426 #define MCP_PULSE_SEQ_MASK 0x00007fff 1427 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1428 /* Indicates to the driver not to assert due to lack 1429 * of MCP response */ 1430 #define MCP_EVENT_MASK 0xffff0000 1431 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1432 1433 u32 iscsi_boot_signature; 1434 u32 iscsi_boot_block_offset; 1435 1436 u32 drv_status; 1437 #define DRV_STATUS_PMF 0x00000001 1438 #define DRV_STATUS_VF_DISABLED 0x00000002 1439 #define DRV_STATUS_SET_MF_BW 0x00000004 1440 #define DRV_STATUS_LINK_EVENT 0x00000008 1441 1442 #define DRV_STATUS_OEM_EVENT_MASK 0x00000070 1443 #define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010 1444 #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020 1445 1446 #define DRV_STATUS_OEM_UPDATE_SVID 0x00000080 1447 1448 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1449 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1450 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1451 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1452 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1453 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1454 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1455 1456 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1457 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1458 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 1459 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 1460 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 1461 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 1462 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 1463 1464 #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1465 1466 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 1467 1468 u32 virt_mac_upper; 1469 #define VIRT_MAC_SIGN_MASK 0xffff0000 1470 #define VIRT_MAC_SIGNATURE 0x564d0000 1471 u32 virt_mac_lower; 1472 1473}; 1474 1475 1476/**************************************************************************** 1477 * Management firmware state * 1478 ****************************************************************************/ 1479/* Allocate 440 bytes for management firmware */ 1480#define MGMTFW_STATE_WORD_SIZE 110 1481 1482struct mgmtfw_state { 1483 u32 opaque[MGMTFW_STATE_WORD_SIZE]; 1484}; 1485 1486 1487/**************************************************************************** 1488 * Multi-Function configuration * 1489 ****************************************************************************/ 1490struct shared_mf_cfg { 1491 1492 u32 clp_mb; 1493 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1494 /* set by CLP */ 1495 #define SHARED_MF_CLP_EXIT 0x00000001 1496 /* set by MCP */ 1497 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1498 1499}; 1500 1501struct port_mf_cfg { 1502 1503 u32 dynamic_cfg; /* device control channel */ 1504 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1505 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1506 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1507 1508 u32 reserved[1]; 1509 1510}; 1511 1512struct func_mf_cfg { 1513 1514 u32 config; 1515 /* E/R/I/D */ 1516 /* function 0 of each port cannot be hidden */ 1517 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1518 1519 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1520 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1521 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1522 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1523 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1524 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1525 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1526 1527 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1528 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1529 1530 /* PRI */ 1531 /* 0 - low priority, 3 - high priority */ 1532 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1533 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1534 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1535 1536 /* MINBW, MAXBW */ 1537 /* value range - 0..100, increments in 100Mbps */ 1538 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1539 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1540 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1541 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1542 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1543 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1544 1545 u32 mac_upper; /* MAC */ 1546 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1547 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1548 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1549 u32 mac_lower; 1550 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1551 1552 u32 e1hov_tag; /* VNI */ 1553 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1554 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1555 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1556 1557 /* afex default VLAN ID - 12 bits */ 1558 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 1559 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 1560 1561 u32 afex_config; 1562 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff 1563 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 1564 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 1565 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 1566 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 1567 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 1568 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 1569 1570 u32 reserved; 1571}; 1572 1573enum mf_cfg_afex_vlan_mode { 1574 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, 1575 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, 1576 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE 1577}; 1578 1579/* This structure is not applicable and should not be accessed on 57711 */ 1580struct func_ext_cfg { 1581 u32 func_cfg; 1582 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F 1583 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1584 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1585 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1586 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1587 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1588 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 1589 1590 u32 iscsi_mac_addr_upper; 1591 u32 iscsi_mac_addr_lower; 1592 1593 u32 fcoe_mac_addr_upper; 1594 u32 fcoe_mac_addr_lower; 1595 1596 u32 fcoe_wwn_port_name_upper; 1597 u32 fcoe_wwn_port_name_lower; 1598 1599 u32 fcoe_wwn_node_name_upper; 1600 u32 fcoe_wwn_node_name_lower; 1601 1602 u32 preserve_data; 1603 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1604 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1605 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1606 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1607 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1608 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 1609}; 1610 1611struct mf_cfg { 1612 1613 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 1614 /* 0x8*2*2=0x20 */ 1615 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 1616 /* for all chips, there are 8 mf functions */ 1617 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 1618 /* 1619 * Extended configuration per function - this array does not exist and 1620 * should not be accessed on 57711 1621 */ 1622 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 1623}; /* 0x224 */ 1624 1625/**************************************************************************** 1626 * Shared Memory Region * 1627 ****************************************************************************/ 1628struct shmem_region { /* SharedMem Offset (size) */ 1629 1630 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1631 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1632 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1633 /* validity bits */ 1634 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1635 #define SHR_MEM_VALIDITY_MB 0x00200000 1636 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1637 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1638 /* One licensing bit should be set */ 1639 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1640 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1641 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1642 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1643 /* Active MFW */ 1644 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1645 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1646 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1647 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1648 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1649 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1650 1651 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1652 1653 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1654 1655 /* FW information (for internal FW use) */ 1656 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ 1657 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1658 1659 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1660 1661#ifdef BMAPI 1662 /* This is a variable length array */ 1663 /* the number of function depends on the chip type */ 1664 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1665#else 1666 /* the number of function depends on the chip type */ 1667 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1668#endif /* BMAPI */ 1669 1670}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 1671 1672/**************************************************************************** 1673 * Shared Memory 2 Region * 1674 ****************************************************************************/ 1675/* The fw_flr_ack is actually built in the following way: */ 1676/* 8 bit: PF ack */ 1677/* 64 bit: VF ack */ 1678/* 8 bit: ios_dis_ack */ 1679/* In order to maintain endianity in the mailbox hsi, we want to keep using */ 1680/* u32. The fw must have the VF right after the PF since this is how it */ 1681/* access arrays(it expects always the VF to reside after the PF, and that */ 1682/* makes the calculation much easier for it. ) */ 1683/* In order to answer both limitations, and keep the struct small, the code */ 1684/* will abuse the structure defined here to achieve the actual partition */ 1685/* above */ 1686/****************************************************************************/ 1687struct fw_flr_ack { 1688 u32 pf_ack; 1689 u32 vf_ack[1]; 1690 u32 iov_dis_ack; 1691}; 1692 1693struct fw_flr_mb { 1694 u32 aggint; 1695 u32 opgen_addr; 1696 struct fw_flr_ack ack; 1697}; 1698 1699struct eee_remote_vals { 1700 u32 tx_tw; 1701 u32 rx_tw; 1702}; 1703 1704/**** SUPPORT FOR SHMEM ARRRAYS *** 1705 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 1706 * define arrays with storage types smaller then unsigned dwords. 1707 * The macros below add generic support for SHMEM arrays with numeric elements 1708 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 1709 * array with individual bit-filed elements accessed using shifts and masks. 1710 * 1711 */ 1712 1713/* eb is the bitwidth of a single element */ 1714#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 1715#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 1716 1717/* the bit-position macro allows the used to flip the order of the arrays 1718 * elements on a per byte or word boundary. 1719 * 1720 * example: an array with 8 entries each 4 bit wide. This array will fit into 1721 * a single dword. The diagrmas below show the array order of the nibbles. 1722 * 1723 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 1724 * 1725 * | | | | 1726 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 1727 * | | | | 1728 * 1729 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 1730 * 1731 * | | | | 1732 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 1733 * | | | | 1734 * 1735 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 1736 * 1737 * | | | | 1738 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 1739 * | | | | 1740 */ 1741#define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 1742 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 1743 (((i)%((fb)/(eb))) * (eb))) 1744 1745#define SHMEM_ARRAY_GET(a, i, eb, fb) \ 1746 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 1747 SHMEM_ARRAY_MASK(eb)) 1748 1749#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 1750do { \ 1751 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 1752 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1753 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 1754 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1755} while (0) 1756 1757 1758/****START OF DCBX STRUCTURES DECLARATIONS****/ 1759#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 1760#define DCBX_PRI_PG_BITWIDTH 4 1761#define DCBX_PRI_PG_FBITS 8 1762#define DCBX_PRI_PG_GET(a, i) \ 1763 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 1764#define DCBX_PRI_PG_SET(a, i, val) \ 1765 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 1766#define DCBX_MAX_NUM_PG_BW_ENTRIES 8 1767#define DCBX_BW_PG_BITWIDTH 8 1768#define DCBX_PG_BW_GET(a, i) \ 1769 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 1770#define DCBX_PG_BW_SET(a, i, val) \ 1771 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 1772#define DCBX_STRICT_PRI_PG 15 1773#define DCBX_MAX_APP_PROTOCOL 16 1774#define FCOE_APP_IDX 0 1775#define ISCSI_APP_IDX 1 1776#define PREDEFINED_APP_IDX_MAX 2 1777 1778 1779/* Big/Little endian have the same representation. */ 1780struct dcbx_ets_feature { 1781 /* 1782 * For Admin MIB - is this feature supported by the 1783 * driver | For Local MIB - should this feature be enabled. 1784 */ 1785 u32 enabled; 1786 u32 pg_bw_tbl[2]; 1787 u32 pri_pg_tbl[1]; 1788}; 1789 1790/* Driver structure in LE */ 1791struct dcbx_pfc_feature { 1792#ifdef __BIG_ENDIAN 1793 u8 pri_en_bitmap; 1794 #define DCBX_PFC_PRI_0 0x01 1795 #define DCBX_PFC_PRI_1 0x02 1796 #define DCBX_PFC_PRI_2 0x04 1797 #define DCBX_PFC_PRI_3 0x08 1798 #define DCBX_PFC_PRI_4 0x10 1799 #define DCBX_PFC_PRI_5 0x20 1800 #define DCBX_PFC_PRI_6 0x40 1801 #define DCBX_PFC_PRI_7 0x80 1802 u8 pfc_caps; 1803 u8 reserved; 1804 u8 enabled; 1805#elif defined(__LITTLE_ENDIAN) 1806 u8 enabled; 1807 u8 reserved; 1808 u8 pfc_caps; 1809 u8 pri_en_bitmap; 1810 #define DCBX_PFC_PRI_0 0x01 1811 #define DCBX_PFC_PRI_1 0x02 1812 #define DCBX_PFC_PRI_2 0x04 1813 #define DCBX_PFC_PRI_3 0x08 1814 #define DCBX_PFC_PRI_4 0x10 1815 #define DCBX_PFC_PRI_5 0x20 1816 #define DCBX_PFC_PRI_6 0x40 1817 #define DCBX_PFC_PRI_7 0x80 1818#endif 1819}; 1820 1821struct dcbx_app_priority_entry { 1822#ifdef __BIG_ENDIAN 1823 u16 app_id; 1824 u8 pri_bitmap; 1825 u8 appBitfield; 1826 #define DCBX_APP_ENTRY_VALID 0x01 1827 #define DCBX_APP_ENTRY_SF_MASK 0x30 1828 #define DCBX_APP_ENTRY_SF_SHIFT 4 1829 #define DCBX_APP_SF_ETH_TYPE 0x10 1830 #define DCBX_APP_SF_PORT 0x20 1831#elif defined(__LITTLE_ENDIAN) 1832 u8 appBitfield; 1833 #define DCBX_APP_ENTRY_VALID 0x01 1834 #define DCBX_APP_ENTRY_SF_MASK 0x30 1835 #define DCBX_APP_ENTRY_SF_SHIFT 4 1836 #define DCBX_APP_SF_ETH_TYPE 0x10 1837 #define DCBX_APP_SF_PORT 0x20 1838 u8 pri_bitmap; 1839 u16 app_id; 1840#endif 1841}; 1842 1843 1844/* FW structure in BE */ 1845struct dcbx_app_priority_feature { 1846#ifdef __BIG_ENDIAN 1847 u8 reserved; 1848 u8 default_pri; 1849 u8 tc_supported; 1850 u8 enabled; 1851#elif defined(__LITTLE_ENDIAN) 1852 u8 enabled; 1853 u8 tc_supported; 1854 u8 default_pri; 1855 u8 reserved; 1856#endif 1857 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 1858}; 1859 1860/* FW structure in BE */ 1861struct dcbx_features { 1862 /* PG feature */ 1863 struct dcbx_ets_feature ets; 1864 /* PFC feature */ 1865 struct dcbx_pfc_feature pfc; 1866 /* APP feature */ 1867 struct dcbx_app_priority_feature app; 1868}; 1869 1870/* LLDP protocol parameters */ 1871/* FW structure in BE */ 1872struct lldp_params { 1873#ifdef __BIG_ENDIAN 1874 u8 msg_fast_tx_interval; 1875 u8 msg_tx_hold; 1876 u8 msg_tx_interval; 1877 u8 admin_status; 1878 #define LLDP_TX_ONLY 0x01 1879 #define LLDP_RX_ONLY 0x02 1880 #define LLDP_TX_RX 0x03 1881 #define LLDP_DISABLED 0x04 1882 u8 reserved1; 1883 u8 tx_fast; 1884 u8 tx_crd_max; 1885 u8 tx_crd; 1886#elif defined(__LITTLE_ENDIAN) 1887 u8 admin_status; 1888 #define LLDP_TX_ONLY 0x01 1889 #define LLDP_RX_ONLY 0x02 1890 #define LLDP_TX_RX 0x03 1891 #define LLDP_DISABLED 0x04 1892 u8 msg_tx_interval; 1893 u8 msg_tx_hold; 1894 u8 msg_fast_tx_interval; 1895 u8 tx_crd; 1896 u8 tx_crd_max; 1897 u8 tx_fast; 1898 u8 reserved1; 1899#endif 1900 #define REM_CHASSIS_ID_STAT_LEN 4 1901 #define REM_PORT_ID_STAT_LEN 4 1902 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 1903 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 1904 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 1905 u32 peer_port_id[REM_PORT_ID_STAT_LEN]; 1906}; 1907 1908struct lldp_dcbx_stat { 1909 #define LOCAL_CHASSIS_ID_STAT_LEN 2 1910 #define LOCAL_PORT_ID_STAT_LEN 2 1911 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 1912 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 1913 /* Holds local Port ID 8B payload of constant subtype 3. */ 1914 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; 1915 /* Number of DCBX frames transmitted. */ 1916 u32 num_tx_dcbx_pkts; 1917 /* Number of DCBX frames received. */ 1918 u32 num_rx_dcbx_pkts; 1919}; 1920 1921/* ADMIN MIB - DCBX local machine default configuration. */ 1922struct lldp_admin_mib { 1923 u32 ver_cfg_flags; 1924 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 1925 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 1926 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 1927 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 1928 #define DCBX_ETS_RECO_VALID 0x00000010 1929 #define DCBX_ETS_WILLING 0x00000020 1930 #define DCBX_PFC_WILLING 0x00000040 1931 #define DCBX_APP_WILLING 0x00000080 1932 #define DCBX_VERSION_CEE 0x00000100 1933 #define DCBX_VERSION_IEEE 0x00000200 1934 #define DCBX_DCBX_ENABLED 0x00000400 1935 #define DCBX_CEE_VERSION_MASK 0x0000f000 1936 #define DCBX_CEE_VERSION_SHIFT 12 1937 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 1938 #define DCBX_CEE_MAX_VERSION_SHIFT 16 1939 struct dcbx_features features; 1940}; 1941 1942/* REMOTE MIB - remote machine DCBX configuration. */ 1943struct lldp_remote_mib { 1944 u32 prefix_seq_num; 1945 u32 flags; 1946 #define DCBX_ETS_TLV_RX 0x00000001 1947 #define DCBX_PFC_TLV_RX 0x00000002 1948 #define DCBX_APP_TLV_RX 0x00000004 1949 #define DCBX_ETS_RX_ERROR 0x00000010 1950 #define DCBX_PFC_RX_ERROR 0x00000020 1951 #define DCBX_APP_RX_ERROR 0x00000040 1952 #define DCBX_ETS_REM_WILLING 0x00000100 1953 #define DCBX_PFC_REM_WILLING 0x00000200 1954 #define DCBX_APP_REM_WILLING 0x00000400 1955 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 1956 #define DCBX_REMOTE_MIB_VALID 0x00002000 1957 struct dcbx_features features; 1958 u32 suffix_seq_num; 1959}; 1960 1961/* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 1962struct lldp_local_mib { 1963 u32 prefix_seq_num; 1964 /* Indicates if there is mismatch with negotiation results. */ 1965 u32 error; 1966 #define DCBX_LOCAL_ETS_ERROR 0x00000001 1967 #define DCBX_LOCAL_PFC_ERROR 0x00000002 1968 #define DCBX_LOCAL_APP_ERROR 0x00000004 1969 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 1970 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 1971 #define DCBX_REMOTE_MIB_ERROR 0x00000040 1972 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 1973 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 1974 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 1975 struct dcbx_features features; 1976 u32 suffix_seq_num; 1977}; 1978/***END OF DCBX STRUCTURES DECLARATIONS***/ 1979 1980/***********************************************************/ 1981/* Elink section */ 1982/***********************************************************/ 1983#define SHMEM_LINK_CONFIG_SIZE 2 1984struct shmem_lfa { 1985 u32 req_duplex; 1986 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff 1987 #define REQ_DUPLEX_PHY0_SHIFT 0 1988 #define REQ_DUPLEX_PHY1_MASK 0xffff0000 1989 #define REQ_DUPLEX_PHY1_SHIFT 16 1990 u32 req_flow_ctrl; 1991 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff 1992 #define REQ_FLOW_CTRL_PHY0_SHIFT 0 1993 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 1994 #define REQ_FLOW_CTRL_PHY1_SHIFT 16 1995 u32 req_line_speed; /* Also determine AutoNeg */ 1996 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff 1997 #define REQ_LINE_SPD_PHY0_SHIFT 0 1998 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 1999 #define REQ_LINE_SPD_PHY1_SHIFT 16 2000 u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; 2001 u32 additional_config; 2002 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff 2003 #define REQ_FC_AUTO_ADV0_SHIFT 0 2004 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 2005 u32 lfa_sts; 2006 #define LFA_LINK_FLAP_REASON_OFFSET 0 2007 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 2008 #define LFA_LINK_DOWN 0x1 2009 #define LFA_LOOPBACK_ENABLED 0x2 2010 #define LFA_DUPLEX_MISMATCH 0x3 2011 #define LFA_MFW_IS_TOO_OLD 0x4 2012 #define LFA_LINK_SPEED_MISMATCH 0x5 2013 #define LFA_FLOW_CTRL_MISMATCH 0x6 2014 #define LFA_SPEED_CAP_MISMATCH 0x7 2015 #define LFA_DCC_LFA_DISABLED 0x8 2016 #define LFA_EEE_MISMATCH 0x9 2017 2018 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 2019 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 2020 2021 #define LINK_FLAP_COUNT_OFFSET 16 2022 #define LINK_FLAP_COUNT_MASK 0x00ff0000 2023 2024 #define LFA_FLAGS_MASK 0xff000000 2025 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) 2026}; 2027 2028/* Used to support NSCI get OS driver version 2029 * on driver load the version value will be set 2030 * on driver unload driver value of 0x0 will be set. 2031 */ 2032struct os_drv_ver { 2033#define DRV_VER_NOT_LOADED 0 2034 2035 /* personalties order is important */ 2036#define DRV_PERS_ETHERNET 0 2037#define DRV_PERS_ISCSI 1 2038#define DRV_PERS_FCOE 2 2039 2040 /* shmem2 struct is constant can't add more personalties here */ 2041#define MAX_DRV_PERS 3 2042 u32 versions[MAX_DRV_PERS]; 2043}; 2044 2045struct ncsi_oem_fcoe_features { 2046 u32 fcoe_features1; 2047 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF 2048 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0 2049 2050 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000 2051 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16 2052 2053 u32 fcoe_features2; 2054 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF 2055 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0 2056 2057 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000 2058 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16 2059 2060 u32 fcoe_features3; 2061 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF 2062 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0 2063 2064 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000 2065 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16 2066 2067 u32 fcoe_features4; 2068 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F 2069 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0 2070}; 2071 2072enum curr_cfg_method_e { 2073 CURR_CFG_MET_NONE = 0, /* default config */ 2074 CURR_CFG_MET_OS = 1, 2075 CURR_CFG_MET_VENDOR_SPEC = 2,/* e.g. Option ROM, NPAR, O/S Cfg Utils */ 2076}; 2077 2078#define FC_NPIV_WWPN_SIZE 8 2079#define FC_NPIV_WWNN_SIZE 8 2080struct bdn_npiv_settings { 2081 u8 npiv_wwpn[FC_NPIV_WWPN_SIZE]; 2082 u8 npiv_wwnn[FC_NPIV_WWNN_SIZE]; 2083}; 2084 2085struct bdn_fc_npiv_cfg { 2086 /* hdr used internally by the MFW */ 2087 u32 hdr; 2088 u32 num_of_npiv; 2089}; 2090 2091#define MAX_NUMBER_NPIV 64 2092struct bdn_fc_npiv_tbl { 2093 struct bdn_fc_npiv_cfg fc_npiv_cfg; 2094 struct bdn_npiv_settings settings[MAX_NUMBER_NPIV]; 2095}; 2096 2097struct mdump_driver_info { 2098 u32 epoc; 2099 u32 drv_ver; 2100 u32 fw_ver; 2101 2102 u32 valid_dump; 2103 #define FIRST_DUMP_VALID (1 << 0) 2104 #define SECOND_DUMP_VALID (1 << 1) 2105 2106 u32 flags; 2107 #define ENABLE_ALL_TRIGGERS (0x7fffffff) 2108 #define TRIGGER_MDUMP_ONCE (1 << 31) 2109}; 2110 2111struct ncsi_oem_data { 2112 u32 driver_version[4]; 2113 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features; 2114}; 2115 2116struct shmem2_region { 2117 2118 u32 size; /* 0x0000 */ 2119 2120 u32 dcc_support; /* 0x0004 */ 2121 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 2122 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 2123 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 2124 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 2125 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 2126 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 2127 2128 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 2129 /* 2130 * For backwards compatibility, if the mf_cfg_addr does not exist 2131 * (the size filed is smaller than 0xc) the mf_cfg resides at the 2132 * end of struct shmem_region 2133 */ 2134 u32 mf_cfg_addr; /* 0x0010 */ 2135 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 2136 2137 struct fw_flr_mb flr_mb; /* 0x0014 */ 2138 u32 dcbx_lldp_params_offset; /* 0x0028 */ 2139 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 2140 u32 dcbx_neg_res_offset; /* 0x002c */ 2141 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 2142 u32 dcbx_remote_mib_offset; /* 0x0030 */ 2143 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 2144 /* 2145 * The other shmemX_base_addr holds the other path's shmem address 2146 * required for example in case of common phy init, or for path1 to know 2147 * the address of mcp debug trace which is located in offset from shmem 2148 * of path0 2149 */ 2150 u32 other_shmem_base_addr; /* 0x0034 */ 2151 u32 other_shmem2_base_addr; /* 0x0038 */ 2152 /* 2153 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 2154 * which were disabled/flred 2155 */ 2156 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 2157 2158 /* 2159 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 2160 * VFs 2161 */ 2162 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 2163 2164 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 2165 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 2166 2167 /* 2168 * edebug_driver_if field is used to transfer messages between edebug 2169 * app to the driver through shmem2. 2170 * 2171 * message format: 2172 * bits 0-2 - function number / instance of driver to perform request 2173 * bits 3-5 - op code / is_ack? 2174 * bits 6-63 - data 2175 */ 2176 u32 edebug_driver_if[2]; /* 0x0068 */ 2177 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 2178 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 2179 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 2180 2181 u32 nvm_retain_bitmap_addr; /* 0x0070 */ 2182 2183 /* afex support of that driver */ 2184 u32 afex_driver_support; /* 0x0074 */ 2185 #define SHMEM_AFEX_VERSION_MASK 0x100f 2186 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 2187 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 2188 2189 /* driver receives addr in scratchpad to which it should respond */ 2190 u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX]; 2191 2192 /* generic params from MCP to driver (value depends on the msg sent 2193 * to driver 2194 */ 2195 u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ 2196 u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ 2197 2198 u32 swim_base_addr; /* 0x0108 */ 2199 u32 swim_funcs; 2200 u32 swim_main_cb; 2201 2202 /* bitmap notifying which VIF profiles stored in nvram are enabled by 2203 * switch 2204 */ 2205 u32 afex_profiles_enabled[2]; 2206 2207 /* generic flags controlled by the driver */ 2208 u32 drv_flags; 2209 #define DRV_FLAGS_DCB_CONFIGURED 0x0 2210 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 2211 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 2212 2213 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ 2214 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ 2215 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) 2216 /* pointer to extended dev_info shared data copied from nvm image */ 2217 u32 extended_dev_info_shared_addr; 2218 u32 ncsi_oem_data_addr; 2219 2220 u32 ocsd_host_addr; /* initialized by option ROM */ 2221 u32 ocbb_host_addr; /* initialized by option ROM */ 2222 u32 ocsd_req_update_interval; /* initialized by option ROM */ 2223 u32 temperature_in_half_celsius; 2224 u32 glob_struct_in_host; 2225 2226 u32 dcbx_neg_res_ext_offset; 2227#define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 2228 2229 u32 drv_capabilities_flag[E2_FUNC_MAX]; 2230#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 2231#define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 2232#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 2233#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 2234#define DRV_FLAGS_MTU_MASK 0xffff0000 2235#define DRV_FLAGS_MTU_SHIFT 16 2236 2237 u32 extended_dev_info_shared_cfg_size; 2238 2239 u32 dcbx_en[PORT_MAX]; 2240 2241 /* The offset points to the multi threaded meta structure */ 2242 u32 multi_thread_data_offset; 2243 2244 /* address of DMAable host address holding values from the drivers */ 2245 u32 drv_info_host_addr_lo; 2246 u32 drv_info_host_addr_hi; 2247 2248 /* general values written by the MFW (such as current version) */ 2249 u32 drv_info_control; 2250#define DRV_INFO_CONTROL_VER_MASK 0x000000ff 2251#define DRV_INFO_CONTROL_VER_SHIFT 0 2252#define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 2253#define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 2254 u32 ibft_host_addr; /* initialized by option ROM */ 2255 struct eee_remote_vals eee_remote_vals[PORT_MAX]; 2256 u32 reserved[E2_FUNC_MAX]; 2257 2258 2259 /* the status of EEE auto-negotiation 2260 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. 2261 * bits 19:16 the supported modes for EEE. 2262 * bits 23:20 the speeds advertised for EEE. 2263 * bits 27:24 the speeds the Link partner advertised for EEE. 2264 * The supported/adv. modes in bits 27:19 originate from the 2265 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 2266 * bit 28 when 1'b1 EEE was requested. 2267 * bit 29 when 1'b1 tx lpi was requested. 2268 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff 2269 * 30:29 are 2'b11. 2270 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as 2271 * value. When 1'b1 those bits contains a value times 16 microseconds. 2272 */ 2273 u32 eee_status[PORT_MAX]; 2274 #define SHMEM_EEE_TIMER_MASK 0x0000ffff 2275 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 2276 #define SHMEM_EEE_SUPPORTED_SHIFT 16 2277 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 2278 #define SHMEM_EEE_100M_ADV (1<<0) 2279 #define SHMEM_EEE_1G_ADV (1<<1) 2280 #define SHMEM_EEE_10G_ADV (1<<2) 2281 #define SHMEM_EEE_ADV_STATUS_SHIFT 20 2282 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 2283 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 2284 #define SHMEM_EEE_REQUESTED_BIT 0x10000000 2285 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 2286 #define SHMEM_EEE_ACTIVE_BIT 0x40000000 2287 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 2288 2289 u32 sizeof_port_stats; 2290 2291 /* Link Flap Avoidance */ 2292 u32 lfa_host_addr[PORT_MAX]; 2293 u32 reserved1; 2294 2295 u32 reserved2; /* Offset 0x148 */ 2296 u32 reserved3; /* Offset 0x14C */ 2297 u32 reserved4; /* Offset 0x150 */ 2298 u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */ 2299 #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001 2300 #define LINK_ATTR_84858 0x00000002 2301 #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00 2302 #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8 2303 #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000 2304 #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000 2305 #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000 2306 2307 u32 reserved5[2]; 2308 u32 link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */ 2309 #define LINK_CHANGE_COUNT_MASK 0xff /* Offset 0x168 */ 2310 /* driver version for each personality */ 2311 struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */ 2312 2313 /* Flag to the driver that PF's drv_info_host_addr buffer was read */ 2314 u32 mfw_drv_indication; 2315 2316 /* We use indication for each PF (0..3) */ 2317#define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_)) 2318 union { /* For various OEMs */ /* Offset 0x1a0 */ 2319 u8 storage_boot_prog[E2_FUNC_MAX]; 2320 #define STORAGE_BOOT_PROG_MASK 0x000000FF 2321 #define STORAGE_BOOT_PROG_NONE 0x00000000 2322 #define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002 2323 #define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002 2324 #define STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004 2325 #define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008 2326 #define STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008 2327 #define STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010 2328 #define STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020 2329 #define STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040 2330 #define STORAGE_BOOT_PROG_COMPLETED 0x00000080 2331 2332 u32 oem_i2c_data_addr; 2333 }; 2334 2335 /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */ 2336 /* For PCP values 0-3 use the map lower */ 2337 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1, 2338 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3 2339 */ 2340 u32 c2s_pcp_map_lower[E2_FUNC_MAX]; /* 0x1a4 */ 2341 2342 /* For PCP values 4-7 use the map upper */ 2343 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5, 2344 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7 2345 */ 2346 u32 c2s_pcp_map_upper[E2_FUNC_MAX]; /* 0x1b4 */ 2347 2348 /* For PCP default value get the MSB byte of the map default */ 2349 u32 c2s_pcp_map_default[E2_FUNC_MAX]; /* 0x1c4 */ 2350 2351 /* FC_NPIV table offset in NVRAM */ 2352 u32 fc_npiv_nvram_tbl_addr[PORT_MAX]; /* 0x1d4 */ 2353 2354 /* Shows last method that changed configuration of this device */ 2355 enum curr_cfg_method_e curr_cfg; /* 0x1dc */ 2356 2357 /* Storm FW version, shold be kept in the format 0xMMmmbbdd: 2358 * MM - Major, mm - Minor, bb - Build ,dd - Drop 2359 */ 2360 u32 netproc_fw_ver; /* 0x1e0 */ 2361 2362 /* Option ROM SMASH CLP version */ 2363 u32 clp_ver; /* 0x1e4 */ 2364 2365 u32 pcie_bus_num; /* 0x1e8 */ 2366 2367 u32 sriov_switch_mode; /* 0x1ec */ 2368 #define SRIOV_SWITCH_MODE_NONE 0x0 2369 #define SRIOV_SWITCH_MODE_VEB 0x1 2370 #define SRIOV_SWITCH_MODE_VEPA 0x2 2371 2372 u8 rsrv2[E2_FUNC_MAX]; /* 0x1f0 */ 2373 2374 u32 img_inv_table_addr; /* Address to INV_TABLE_P */ /* 0x1f4 */ 2375 2376 u32 mtu_size[E2_FUNC_MAX]; /* 0x1f8 */ 2377 2378 u32 os_driver_state[E2_FUNC_MAX]; /* 0x208 */ 2379 #define OS_DRIVER_STATE_NOT_LOADED 0 /* not installed */ 2380 #define OS_DRIVER_STATE_LOADING 1 /* transition state */ 2381 #define OS_DRIVER_STATE_DISABLED 2 /* installed but disabled */ 2382 #define OS_DRIVER_STATE_ACTIVE 3 /* installed and active */ 2383 2384 /* mini dump driver info */ 2385 struct mdump_driver_info drv_info; /* 0x218 */ 2386}; 2387 2388 2389struct emac_stats { 2390 u32 rx_stat_ifhcinoctets; 2391 u32 rx_stat_ifhcinbadoctets; 2392 u32 rx_stat_etherstatsfragments; 2393 u32 rx_stat_ifhcinucastpkts; 2394 u32 rx_stat_ifhcinmulticastpkts; 2395 u32 rx_stat_ifhcinbroadcastpkts; 2396 u32 rx_stat_dot3statsfcserrors; 2397 u32 rx_stat_dot3statsalignmenterrors; 2398 u32 rx_stat_dot3statscarriersenseerrors; 2399 u32 rx_stat_xonpauseframesreceived; 2400 u32 rx_stat_xoffpauseframesreceived; 2401 u32 rx_stat_maccontrolframesreceived; 2402 u32 rx_stat_xoffstateentered; 2403 u32 rx_stat_dot3statsframestoolong; 2404 u32 rx_stat_etherstatsjabbers; 2405 u32 rx_stat_etherstatsundersizepkts; 2406 u32 rx_stat_etherstatspkts64octets; 2407 u32 rx_stat_etherstatspkts65octetsto127octets; 2408 u32 rx_stat_etherstatspkts128octetsto255octets; 2409 u32 rx_stat_etherstatspkts256octetsto511octets; 2410 u32 rx_stat_etherstatspkts512octetsto1023octets; 2411 u32 rx_stat_etherstatspkts1024octetsto1522octets; 2412 u32 rx_stat_etherstatspktsover1522octets; 2413 2414 u32 rx_stat_falsecarriererrors; 2415 2416 u32 tx_stat_ifhcoutoctets; 2417 u32 tx_stat_ifhcoutbadoctets; 2418 u32 tx_stat_etherstatscollisions; 2419 u32 tx_stat_outxonsent; 2420 u32 tx_stat_outxoffsent; 2421 u32 tx_stat_flowcontroldone; 2422 u32 tx_stat_dot3statssinglecollisionframes; 2423 u32 tx_stat_dot3statsmultiplecollisionframes; 2424 u32 tx_stat_dot3statsdeferredtransmissions; 2425 u32 tx_stat_dot3statsexcessivecollisions; 2426 u32 tx_stat_dot3statslatecollisions; 2427 u32 tx_stat_ifhcoutucastpkts; 2428 u32 tx_stat_ifhcoutmulticastpkts; 2429 u32 tx_stat_ifhcoutbroadcastpkts; 2430 u32 tx_stat_etherstatspkts64octets; 2431 u32 tx_stat_etherstatspkts65octetsto127octets; 2432 u32 tx_stat_etherstatspkts128octetsto255octets; 2433 u32 tx_stat_etherstatspkts256octetsto511octets; 2434 u32 tx_stat_etherstatspkts512octetsto1023octets; 2435 u32 tx_stat_etherstatspkts1024octetsto1522octets; 2436 u32 tx_stat_etherstatspktsover1522octets; 2437 u32 tx_stat_dot3statsinternalmactransmiterrors; 2438}; 2439 2440 2441struct bmac1_stats { 2442 u32 tx_stat_gtpkt_lo; 2443 u32 tx_stat_gtpkt_hi; 2444 u32 tx_stat_gtxpf_lo; 2445 u32 tx_stat_gtxpf_hi; 2446 u32 tx_stat_gtfcs_lo; 2447 u32 tx_stat_gtfcs_hi; 2448 u32 tx_stat_gtmca_lo; 2449 u32 tx_stat_gtmca_hi; 2450 u32 tx_stat_gtbca_lo; 2451 u32 tx_stat_gtbca_hi; 2452 u32 tx_stat_gtfrg_lo; 2453 u32 tx_stat_gtfrg_hi; 2454 u32 tx_stat_gtovr_lo; 2455 u32 tx_stat_gtovr_hi; 2456 u32 tx_stat_gt64_lo; 2457 u32 tx_stat_gt64_hi; 2458 u32 tx_stat_gt127_lo; 2459 u32 tx_stat_gt127_hi; 2460 u32 tx_stat_gt255_lo; 2461 u32 tx_stat_gt255_hi; 2462 u32 tx_stat_gt511_lo; 2463 u32 tx_stat_gt511_hi; 2464 u32 tx_stat_gt1023_lo; 2465 u32 tx_stat_gt1023_hi; 2466 u32 tx_stat_gt1518_lo; 2467 u32 tx_stat_gt1518_hi; 2468 u32 tx_stat_gt2047_lo; 2469 u32 tx_stat_gt2047_hi; 2470 u32 tx_stat_gt4095_lo; 2471 u32 tx_stat_gt4095_hi; 2472 u32 tx_stat_gt9216_lo; 2473 u32 tx_stat_gt9216_hi; 2474 u32 tx_stat_gt16383_lo; 2475 u32 tx_stat_gt16383_hi; 2476 u32 tx_stat_gtmax_lo; 2477 u32 tx_stat_gtmax_hi; 2478 u32 tx_stat_gtufl_lo; 2479 u32 tx_stat_gtufl_hi; 2480 u32 tx_stat_gterr_lo; 2481 u32 tx_stat_gterr_hi; 2482 u32 tx_stat_gtbyt_lo; 2483 u32 tx_stat_gtbyt_hi; 2484 2485 u32 rx_stat_gr64_lo; 2486 u32 rx_stat_gr64_hi; 2487 u32 rx_stat_gr127_lo; 2488 u32 rx_stat_gr127_hi; 2489 u32 rx_stat_gr255_lo; 2490 u32 rx_stat_gr255_hi; 2491 u32 rx_stat_gr511_lo; 2492 u32 rx_stat_gr511_hi; 2493 u32 rx_stat_gr1023_lo; 2494 u32 rx_stat_gr1023_hi; 2495 u32 rx_stat_gr1518_lo; 2496 u32 rx_stat_gr1518_hi; 2497 u32 rx_stat_gr2047_lo; 2498 u32 rx_stat_gr2047_hi; 2499 u32 rx_stat_gr4095_lo; 2500 u32 rx_stat_gr4095_hi; 2501 u32 rx_stat_gr9216_lo; 2502 u32 rx_stat_gr9216_hi; 2503 u32 rx_stat_gr16383_lo; 2504 u32 rx_stat_gr16383_hi; 2505 u32 rx_stat_grmax_lo; 2506 u32 rx_stat_grmax_hi; 2507 u32 rx_stat_grpkt_lo; 2508 u32 rx_stat_grpkt_hi; 2509 u32 rx_stat_grfcs_lo; 2510 u32 rx_stat_grfcs_hi; 2511 u32 rx_stat_grmca_lo; 2512 u32 rx_stat_grmca_hi; 2513 u32 rx_stat_grbca_lo; 2514 u32 rx_stat_grbca_hi; 2515 u32 rx_stat_grxcf_lo; 2516 u32 rx_stat_grxcf_hi; 2517 u32 rx_stat_grxpf_lo; 2518 u32 rx_stat_grxpf_hi; 2519 u32 rx_stat_grxuo_lo; 2520 u32 rx_stat_grxuo_hi; 2521 u32 rx_stat_grjbr_lo; 2522 u32 rx_stat_grjbr_hi; 2523 u32 rx_stat_grovr_lo; 2524 u32 rx_stat_grovr_hi; 2525 u32 rx_stat_grflr_lo; 2526 u32 rx_stat_grflr_hi; 2527 u32 rx_stat_grmeg_lo; 2528 u32 rx_stat_grmeg_hi; 2529 u32 rx_stat_grmeb_lo; 2530 u32 rx_stat_grmeb_hi; 2531 u32 rx_stat_grbyt_lo; 2532 u32 rx_stat_grbyt_hi; 2533 u32 rx_stat_grund_lo; 2534 u32 rx_stat_grund_hi; 2535 u32 rx_stat_grfrg_lo; 2536 u32 rx_stat_grfrg_hi; 2537 u32 rx_stat_grerb_lo; 2538 u32 rx_stat_grerb_hi; 2539 u32 rx_stat_grfre_lo; 2540 u32 rx_stat_grfre_hi; 2541 u32 rx_stat_gripj_lo; 2542 u32 rx_stat_gripj_hi; 2543}; 2544 2545struct bmac2_stats { 2546 u32 tx_stat_gtpk_lo; /* gtpok */ 2547 u32 tx_stat_gtpk_hi; /* gtpok */ 2548 u32 tx_stat_gtxpf_lo; /* gtpf */ 2549 u32 tx_stat_gtxpf_hi; /* gtpf */ 2550 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */ 2551 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */ 2552 u32 tx_stat_gtfcs_lo; 2553 u32 tx_stat_gtfcs_hi; 2554 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */ 2555 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */ 2556 u32 tx_stat_gtmca_lo; 2557 u32 tx_stat_gtmca_hi; 2558 u32 tx_stat_gtbca_lo; 2559 u32 tx_stat_gtbca_hi; 2560 u32 tx_stat_gtovr_lo; 2561 u32 tx_stat_gtovr_hi; 2562 u32 tx_stat_gtfrg_lo; 2563 u32 tx_stat_gtfrg_hi; 2564 u32 tx_stat_gtpkt1_lo; /* gtpkt */ 2565 u32 tx_stat_gtpkt1_hi; /* gtpkt */ 2566 u32 tx_stat_gt64_lo; 2567 u32 tx_stat_gt64_hi; 2568 u32 tx_stat_gt127_lo; 2569 u32 tx_stat_gt127_hi; 2570 u32 tx_stat_gt255_lo; 2571 u32 tx_stat_gt255_hi; 2572 u32 tx_stat_gt511_lo; 2573 u32 tx_stat_gt511_hi; 2574 u32 tx_stat_gt1023_lo; 2575 u32 tx_stat_gt1023_hi; 2576 u32 tx_stat_gt1518_lo; 2577 u32 tx_stat_gt1518_hi; 2578 u32 tx_stat_gt2047_lo; 2579 u32 tx_stat_gt2047_hi; 2580 u32 tx_stat_gt4095_lo; 2581 u32 tx_stat_gt4095_hi; 2582 u32 tx_stat_gt9216_lo; 2583 u32 tx_stat_gt9216_hi; 2584 u32 tx_stat_gt16383_lo; 2585 u32 tx_stat_gt16383_hi; 2586 u32 tx_stat_gtmax_lo; 2587 u32 tx_stat_gtmax_hi; 2588 u32 tx_stat_gtufl_lo; 2589 u32 tx_stat_gtufl_hi; 2590 u32 tx_stat_gterr_lo; 2591 u32 tx_stat_gterr_hi; 2592 u32 tx_stat_gtbyt_lo; 2593 u32 tx_stat_gtbyt_hi; 2594 2595 u32 rx_stat_gr64_lo; 2596 u32 rx_stat_gr64_hi; 2597 u32 rx_stat_gr127_lo; 2598 u32 rx_stat_gr127_hi; 2599 u32 rx_stat_gr255_lo; 2600 u32 rx_stat_gr255_hi; 2601 u32 rx_stat_gr511_lo; 2602 u32 rx_stat_gr511_hi; 2603 u32 rx_stat_gr1023_lo; 2604 u32 rx_stat_gr1023_hi; 2605 u32 rx_stat_gr1518_lo; 2606 u32 rx_stat_gr1518_hi; 2607 u32 rx_stat_gr2047_lo; 2608 u32 rx_stat_gr2047_hi; 2609 u32 rx_stat_gr4095_lo; 2610 u32 rx_stat_gr4095_hi; 2611 u32 rx_stat_gr9216_lo; 2612 u32 rx_stat_gr9216_hi; 2613 u32 rx_stat_gr16383_lo; 2614 u32 rx_stat_gr16383_hi; 2615 u32 rx_stat_grmax_lo; 2616 u32 rx_stat_grmax_hi; 2617 u32 rx_stat_grpkt_lo; 2618 u32 rx_stat_grpkt_hi; 2619 u32 rx_stat_grfcs_lo; 2620 u32 rx_stat_grfcs_hi; 2621 u32 rx_stat_gruca_lo; 2622 u32 rx_stat_gruca_hi; 2623 u32 rx_stat_grmca_lo; 2624 u32 rx_stat_grmca_hi; 2625 u32 rx_stat_grbca_lo; 2626 u32 rx_stat_grbca_hi; 2627 u32 rx_stat_grxpf_lo; /* grpf */ 2628 u32 rx_stat_grxpf_hi; /* grpf */ 2629 u32 rx_stat_grpp_lo; 2630 u32 rx_stat_grpp_hi; 2631 u32 rx_stat_grxuo_lo; /* gruo */ 2632 u32 rx_stat_grxuo_hi; /* gruo */ 2633 u32 rx_stat_grjbr_lo; 2634 u32 rx_stat_grjbr_hi; 2635 u32 rx_stat_grovr_lo; 2636 u32 rx_stat_grovr_hi; 2637 u32 rx_stat_grxcf_lo; /* grcf */ 2638 u32 rx_stat_grxcf_hi; /* grcf */ 2639 u32 rx_stat_grflr_lo; 2640 u32 rx_stat_grflr_hi; 2641 u32 rx_stat_grpok_lo; 2642 u32 rx_stat_grpok_hi; 2643 u32 rx_stat_grmeg_lo; 2644 u32 rx_stat_grmeg_hi; 2645 u32 rx_stat_grmeb_lo; 2646 u32 rx_stat_grmeb_hi; 2647 u32 rx_stat_grbyt_lo; 2648 u32 rx_stat_grbyt_hi; 2649 u32 rx_stat_grund_lo; 2650 u32 rx_stat_grund_hi; 2651 u32 rx_stat_grfrg_lo; 2652 u32 rx_stat_grfrg_hi; 2653 u32 rx_stat_grerb_lo; /* grerrbyt */ 2654 u32 rx_stat_grerb_hi; /* grerrbyt */ 2655 u32 rx_stat_grfre_lo; /* grfrerr */ 2656 u32 rx_stat_grfre_hi; /* grfrerr */ 2657 u32 rx_stat_gripj_lo; 2658 u32 rx_stat_gripj_hi; 2659}; 2660 2661struct mstat_stats { 2662 struct { 2663 /* OTE MSTAT on E3 has a bug where this register's contents are 2664 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 2665 */ 2666 u32 tx_gtxpok_lo; 2667 u32 tx_gtxpok_hi; 2668 u32 tx_gtxpf_lo; 2669 u32 tx_gtxpf_hi; 2670 u32 tx_gtxpp_lo; 2671 u32 tx_gtxpp_hi; 2672 u32 tx_gtfcs_lo; 2673 u32 tx_gtfcs_hi; 2674 u32 tx_gtuca_lo; 2675 u32 tx_gtuca_hi; 2676 u32 tx_gtmca_lo; 2677 u32 tx_gtmca_hi; 2678 u32 tx_gtgca_lo; 2679 u32 tx_gtgca_hi; 2680 u32 tx_gtpkt_lo; 2681 u32 tx_gtpkt_hi; 2682 u32 tx_gt64_lo; 2683 u32 tx_gt64_hi; 2684 u32 tx_gt127_lo; 2685 u32 tx_gt127_hi; 2686 u32 tx_gt255_lo; 2687 u32 tx_gt255_hi; 2688 u32 tx_gt511_lo; 2689 u32 tx_gt511_hi; 2690 u32 tx_gt1023_lo; 2691 u32 tx_gt1023_hi; 2692 u32 tx_gt1518_lo; 2693 u32 tx_gt1518_hi; 2694 u32 tx_gt2047_lo; 2695 u32 tx_gt2047_hi; 2696 u32 tx_gt4095_lo; 2697 u32 tx_gt4095_hi; 2698 u32 tx_gt9216_lo; 2699 u32 tx_gt9216_hi; 2700 u32 tx_gt16383_lo; 2701 u32 tx_gt16383_hi; 2702 u32 tx_gtufl_lo; 2703 u32 tx_gtufl_hi; 2704 u32 tx_gterr_lo; 2705 u32 tx_gterr_hi; 2706 u32 tx_gtbyt_lo; 2707 u32 tx_gtbyt_hi; 2708 u32 tx_collisions_lo; 2709 u32 tx_collisions_hi; 2710 u32 tx_singlecollision_lo; 2711 u32 tx_singlecollision_hi; 2712 u32 tx_multiplecollisions_lo; 2713 u32 tx_multiplecollisions_hi; 2714 u32 tx_deferred_lo; 2715 u32 tx_deferred_hi; 2716 u32 tx_excessivecollisions_lo; 2717 u32 tx_excessivecollisions_hi; 2718 u32 tx_latecollisions_lo; 2719 u32 tx_latecollisions_hi; 2720 } stats_tx; 2721 2722 struct { 2723 u32 rx_gr64_lo; 2724 u32 rx_gr64_hi; 2725 u32 rx_gr127_lo; 2726 u32 rx_gr127_hi; 2727 u32 rx_gr255_lo; 2728 u32 rx_gr255_hi; 2729 u32 rx_gr511_lo; 2730 u32 rx_gr511_hi; 2731 u32 rx_gr1023_lo; 2732 u32 rx_gr1023_hi; 2733 u32 rx_gr1518_lo; 2734 u32 rx_gr1518_hi; 2735 u32 rx_gr2047_lo; 2736 u32 rx_gr2047_hi; 2737 u32 rx_gr4095_lo; 2738 u32 rx_gr4095_hi; 2739 u32 rx_gr9216_lo; 2740 u32 rx_gr9216_hi; 2741 u32 rx_gr16383_lo; 2742 u32 rx_gr16383_hi; 2743 u32 rx_grpkt_lo; 2744 u32 rx_grpkt_hi; 2745 u32 rx_grfcs_lo; 2746 u32 rx_grfcs_hi; 2747 u32 rx_gruca_lo; 2748 u32 rx_gruca_hi; 2749 u32 rx_grmca_lo; 2750 u32 rx_grmca_hi; 2751 u32 rx_grbca_lo; 2752 u32 rx_grbca_hi; 2753 u32 rx_grxpf_lo; 2754 u32 rx_grxpf_hi; 2755 u32 rx_grxpp_lo; 2756 u32 rx_grxpp_hi; 2757 u32 rx_grxuo_lo; 2758 u32 rx_grxuo_hi; 2759 u32 rx_grovr_lo; 2760 u32 rx_grovr_hi; 2761 u32 rx_grxcf_lo; 2762 u32 rx_grxcf_hi; 2763 u32 rx_grflr_lo; 2764 u32 rx_grflr_hi; 2765 u32 rx_grpok_lo; 2766 u32 rx_grpok_hi; 2767 u32 rx_grbyt_lo; 2768 u32 rx_grbyt_hi; 2769 u32 rx_grund_lo; 2770 u32 rx_grund_hi; 2771 u32 rx_grfrg_lo; 2772 u32 rx_grfrg_hi; 2773 u32 rx_grerb_lo; 2774 u32 rx_grerb_hi; 2775 u32 rx_grfre_lo; 2776 u32 rx_grfre_hi; 2777 2778 u32 rx_alignmenterrors_lo; 2779 u32 rx_alignmenterrors_hi; 2780 u32 rx_falsecarrier_lo; 2781 u32 rx_falsecarrier_hi; 2782 u32 rx_llfcmsgcnt_lo; 2783 u32 rx_llfcmsgcnt_hi; 2784 } stats_rx; 2785}; 2786 2787union mac_stats { 2788 struct emac_stats emac_stats; 2789 struct bmac1_stats bmac1_stats; 2790 struct bmac2_stats bmac2_stats; 2791 struct mstat_stats mstat_stats; 2792}; 2793 2794 2795struct mac_stx { 2796 /* in_bad_octets */ 2797 u32 rx_stat_ifhcinbadoctets_hi; 2798 u32 rx_stat_ifhcinbadoctets_lo; 2799 2800 /* out_bad_octets */ 2801 u32 tx_stat_ifhcoutbadoctets_hi; 2802 u32 tx_stat_ifhcoutbadoctets_lo; 2803 2804 /* crc_receive_errors */ 2805 u32 rx_stat_dot3statsfcserrors_hi; 2806 u32 rx_stat_dot3statsfcserrors_lo; 2807 /* alignment_errors */ 2808 u32 rx_stat_dot3statsalignmenterrors_hi; 2809 u32 rx_stat_dot3statsalignmenterrors_lo; 2810 /* carrier_sense_errors */ 2811 u32 rx_stat_dot3statscarriersenseerrors_hi; 2812 u32 rx_stat_dot3statscarriersenseerrors_lo; 2813 /* false_carrier_detections */ 2814 u32 rx_stat_falsecarriererrors_hi; 2815 u32 rx_stat_falsecarriererrors_lo; 2816 2817 /* runt_packets_received */ 2818 u32 rx_stat_etherstatsundersizepkts_hi; 2819 u32 rx_stat_etherstatsundersizepkts_lo; 2820 /* jabber_packets_received */ 2821 u32 rx_stat_dot3statsframestoolong_hi; 2822 u32 rx_stat_dot3statsframestoolong_lo; 2823 2824 /* error_runt_packets_received */ 2825 u32 rx_stat_etherstatsfragments_hi; 2826 u32 rx_stat_etherstatsfragments_lo; 2827 /* error_jabber_packets_received */ 2828 u32 rx_stat_etherstatsjabbers_hi; 2829 u32 rx_stat_etherstatsjabbers_lo; 2830 2831 /* control_frames_received */ 2832 u32 rx_stat_maccontrolframesreceived_hi; 2833 u32 rx_stat_maccontrolframesreceived_lo; 2834 u32 rx_stat_mac_xpf_hi; 2835 u32 rx_stat_mac_xpf_lo; 2836 u32 rx_stat_mac_xcf_hi; 2837 u32 rx_stat_mac_xcf_lo; 2838 2839 /* xoff_state_entered */ 2840 u32 rx_stat_xoffstateentered_hi; 2841 u32 rx_stat_xoffstateentered_lo; 2842 /* pause_xon_frames_received */ 2843 u32 rx_stat_xonpauseframesreceived_hi; 2844 u32 rx_stat_xonpauseframesreceived_lo; 2845 /* pause_xoff_frames_received */ 2846 u32 rx_stat_xoffpauseframesreceived_hi; 2847 u32 rx_stat_xoffpauseframesreceived_lo; 2848 /* pause_xon_frames_transmitted */ 2849 u32 tx_stat_outxonsent_hi; 2850 u32 tx_stat_outxonsent_lo; 2851 /* pause_xoff_frames_transmitted */ 2852 u32 tx_stat_outxoffsent_hi; 2853 u32 tx_stat_outxoffsent_lo; 2854 /* flow_control_done */ 2855 u32 tx_stat_flowcontroldone_hi; 2856 u32 tx_stat_flowcontroldone_lo; 2857 2858 /* ether_stats_collisions */ 2859 u32 tx_stat_etherstatscollisions_hi; 2860 u32 tx_stat_etherstatscollisions_lo; 2861 /* single_collision_transmit_frames */ 2862 u32 tx_stat_dot3statssinglecollisionframes_hi; 2863 u32 tx_stat_dot3statssinglecollisionframes_lo; 2864 /* multiple_collision_transmit_frames */ 2865 u32 tx_stat_dot3statsmultiplecollisionframes_hi; 2866 u32 tx_stat_dot3statsmultiplecollisionframes_lo; 2867 /* deferred_transmissions */ 2868 u32 tx_stat_dot3statsdeferredtransmissions_hi; 2869 u32 tx_stat_dot3statsdeferredtransmissions_lo; 2870 /* excessive_collision_frames */ 2871 u32 tx_stat_dot3statsexcessivecollisions_hi; 2872 u32 tx_stat_dot3statsexcessivecollisions_lo; 2873 /* late_collision_frames */ 2874 u32 tx_stat_dot3statslatecollisions_hi; 2875 u32 tx_stat_dot3statslatecollisions_lo; 2876 2877 /* frames_transmitted_64_bytes */ 2878 u32 tx_stat_etherstatspkts64octets_hi; 2879 u32 tx_stat_etherstatspkts64octets_lo; 2880 /* frames_transmitted_65_127_bytes */ 2881 u32 tx_stat_etherstatspkts65octetsto127octets_hi; 2882 u32 tx_stat_etherstatspkts65octetsto127octets_lo; 2883 /* frames_transmitted_128_255_bytes */ 2884 u32 tx_stat_etherstatspkts128octetsto255octets_hi; 2885 u32 tx_stat_etherstatspkts128octetsto255octets_lo; 2886 /* frames_transmitted_256_511_bytes */ 2887 u32 tx_stat_etherstatspkts256octetsto511octets_hi; 2888 u32 tx_stat_etherstatspkts256octetsto511octets_lo; 2889 /* frames_transmitted_512_1023_bytes */ 2890 u32 tx_stat_etherstatspkts512octetsto1023octets_hi; 2891 u32 tx_stat_etherstatspkts512octetsto1023octets_lo; 2892 /* frames_transmitted_1024_1522_bytes */ 2893 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; 2894 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; 2895 /* frames_transmitted_1523_9022_bytes */ 2896 u32 tx_stat_etherstatspktsover1522octets_hi; 2897 u32 tx_stat_etherstatspktsover1522octets_lo; 2898 u32 tx_stat_mac_2047_hi; 2899 u32 tx_stat_mac_2047_lo; 2900 u32 tx_stat_mac_4095_hi; 2901 u32 tx_stat_mac_4095_lo; 2902 u32 tx_stat_mac_9216_hi; 2903 u32 tx_stat_mac_9216_lo; 2904 u32 tx_stat_mac_16383_hi; 2905 u32 tx_stat_mac_16383_lo; 2906 2907 /* internal_mac_transmit_errors */ 2908 u32 tx_stat_dot3statsinternalmactransmiterrors_hi; 2909 u32 tx_stat_dot3statsinternalmactransmiterrors_lo; 2910 2911 /* if_out_discards */ 2912 u32 tx_stat_mac_ufl_hi; 2913 u32 tx_stat_mac_ufl_lo; 2914}; 2915 2916 2917#define MAC_STX_IDX_MAX 2 2918 2919struct host_port_stats { 2920 u32 host_port_stats_counter; 2921 2922 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 2923 2924 u32 brb_drop_hi; 2925 u32 brb_drop_lo; 2926 2927 u32 not_used; /* obsolete */ 2928 u32 pfc_frames_tx_hi; 2929 u32 pfc_frames_tx_lo; 2930 u32 pfc_frames_rx_hi; 2931 u32 pfc_frames_rx_lo; 2932 2933 u32 eee_lpi_count_hi; 2934 u32 eee_lpi_count_lo; 2935}; 2936 2937 2938struct host_func_stats { 2939 u32 host_func_stats_start; 2940 2941 u32 total_bytes_received_hi; 2942 u32 total_bytes_received_lo; 2943 2944 u32 total_bytes_transmitted_hi; 2945 u32 total_bytes_transmitted_lo; 2946 2947 u32 total_unicast_packets_received_hi; 2948 u32 total_unicast_packets_received_lo; 2949 2950 u32 total_multicast_packets_received_hi; 2951 u32 total_multicast_packets_received_lo; 2952 2953 u32 total_broadcast_packets_received_hi; 2954 u32 total_broadcast_packets_received_lo; 2955 2956 u32 total_unicast_packets_transmitted_hi; 2957 u32 total_unicast_packets_transmitted_lo; 2958 2959 u32 total_multicast_packets_transmitted_hi; 2960 u32 total_multicast_packets_transmitted_lo; 2961 2962 u32 total_broadcast_packets_transmitted_hi; 2963 u32 total_broadcast_packets_transmitted_lo; 2964 2965 u32 valid_bytes_received_hi; 2966 u32 valid_bytes_received_lo; 2967 2968 u32 host_func_stats_end; 2969}; 2970 2971/* VIC definitions */ 2972#define VICSTATST_UIF_INDEX 2 2973 2974 2975/* stats collected for afex. 2976 * NOTE: structure is exactly as expected to be received by the switch. 2977 * order must remain exactly as is unless protocol changes ! 2978 */ 2979struct afex_stats { 2980 u32 tx_unicast_frames_hi; 2981 u32 tx_unicast_frames_lo; 2982 u32 tx_unicast_bytes_hi; 2983 u32 tx_unicast_bytes_lo; 2984 u32 tx_multicast_frames_hi; 2985 u32 tx_multicast_frames_lo; 2986 u32 tx_multicast_bytes_hi; 2987 u32 tx_multicast_bytes_lo; 2988 u32 tx_broadcast_frames_hi; 2989 u32 tx_broadcast_frames_lo; 2990 u32 tx_broadcast_bytes_hi; 2991 u32 tx_broadcast_bytes_lo; 2992 u32 tx_frames_discarded_hi; 2993 u32 tx_frames_discarded_lo; 2994 u32 tx_frames_dropped_hi; 2995 u32 tx_frames_dropped_lo; 2996 2997 u32 rx_unicast_frames_hi; 2998 u32 rx_unicast_frames_lo; 2999 u32 rx_unicast_bytes_hi; 3000 u32 rx_unicast_bytes_lo; 3001 u32 rx_multicast_frames_hi; 3002 u32 rx_multicast_frames_lo; 3003 u32 rx_multicast_bytes_hi; 3004 u32 rx_multicast_bytes_lo; 3005 u32 rx_broadcast_frames_hi; 3006 u32 rx_broadcast_frames_lo; 3007 u32 rx_broadcast_bytes_hi; 3008 u32 rx_broadcast_bytes_lo; 3009 u32 rx_frames_discarded_hi; 3010 u32 rx_frames_discarded_lo; 3011 u32 rx_frames_dropped_hi; 3012 u32 rx_frames_dropped_lo; 3013}; 3014 3015#define BCM_5710_FW_MAJOR_VERSION 7 3016#define BCM_5710_FW_MINOR_VERSION 12 3017#define BCM_5710_FW_REVISION_VERSION 30 3018#define BCM_5710_FW_ENGINEERING_VERSION 0 3019#define BCM_5710_FW_COMPILE_FLAGS 1 3020 3021 3022/* 3023 * attention bits 3024 */ 3025struct atten_sp_status_block { 3026 __le32 attn_bits; 3027 __le32 attn_bits_ack; 3028 u8 status_block_id; 3029 u8 reserved0; 3030 __le16 attn_bits_index; 3031 __le32 reserved1; 3032}; 3033 3034 3035/* 3036 * The eth aggregative context of Cstorm 3037 */ 3038struct cstorm_eth_ag_context { 3039 u32 __reserved0[10]; 3040}; 3041 3042 3043/* 3044 * dmae command structure 3045 */ 3046struct dmae_command { 3047 u32 opcode; 3048#define DMAE_COMMAND_SRC (0x1<<0) 3049#define DMAE_COMMAND_SRC_SHIFT 0 3050#define DMAE_COMMAND_DST (0x3<<1) 3051#define DMAE_COMMAND_DST_SHIFT 1 3052#define DMAE_COMMAND_C_DST (0x1<<3) 3053#define DMAE_COMMAND_C_DST_SHIFT 3 3054#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) 3055#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 3056#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) 3057#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 3058#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) 3059#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 3060#define DMAE_COMMAND_ENDIANITY (0x3<<9) 3061#define DMAE_COMMAND_ENDIANITY_SHIFT 9 3062#define DMAE_COMMAND_PORT (0x1<<11) 3063#define DMAE_COMMAND_PORT_SHIFT 11 3064#define DMAE_COMMAND_CRC_RESET (0x1<<12) 3065#define DMAE_COMMAND_CRC_RESET_SHIFT 12 3066#define DMAE_COMMAND_SRC_RESET (0x1<<13) 3067#define DMAE_COMMAND_SRC_RESET_SHIFT 13 3068#define DMAE_COMMAND_DST_RESET (0x1<<14) 3069#define DMAE_COMMAND_DST_RESET_SHIFT 14 3070#define DMAE_COMMAND_E1HVN (0x3<<15) 3071#define DMAE_COMMAND_E1HVN_SHIFT 15 3072#define DMAE_COMMAND_DST_VN (0x3<<17) 3073#define DMAE_COMMAND_DST_VN_SHIFT 17 3074#define DMAE_COMMAND_C_FUNC (0x1<<19) 3075#define DMAE_COMMAND_C_FUNC_SHIFT 19 3076#define DMAE_COMMAND_ERR_POLICY (0x3<<20) 3077#define DMAE_COMMAND_ERR_POLICY_SHIFT 20 3078#define DMAE_COMMAND_RESERVED0 (0x3FF<<22) 3079#define DMAE_COMMAND_RESERVED0_SHIFT 22 3080 u32 src_addr_lo; 3081 u32 src_addr_hi; 3082 u32 dst_addr_lo; 3083 u32 dst_addr_hi; 3084#if defined(__BIG_ENDIAN) 3085 u16 opcode_iov; 3086#define DMAE_COMMAND_SRC_VFID (0x3F<<0) 3087#define DMAE_COMMAND_SRC_VFID_SHIFT 0 3088#define DMAE_COMMAND_SRC_VFPF (0x1<<6) 3089#define DMAE_COMMAND_SRC_VFPF_SHIFT 6 3090#define DMAE_COMMAND_RESERVED1 (0x1<<7) 3091#define DMAE_COMMAND_RESERVED1_SHIFT 7 3092#define DMAE_COMMAND_DST_VFID (0x3F<<8) 3093#define DMAE_COMMAND_DST_VFID_SHIFT 8 3094#define DMAE_COMMAND_DST_VFPF (0x1<<14) 3095#define DMAE_COMMAND_DST_VFPF_SHIFT 14 3096#define DMAE_COMMAND_RESERVED2 (0x1<<15) 3097#define DMAE_COMMAND_RESERVED2_SHIFT 15 3098 u16 len; 3099#elif defined(__LITTLE_ENDIAN) 3100 u16 len; 3101 u16 opcode_iov; 3102#define DMAE_COMMAND_SRC_VFID (0x3F<<0) 3103#define DMAE_COMMAND_SRC_VFID_SHIFT 0 3104#define DMAE_COMMAND_SRC_VFPF (0x1<<6) 3105#define DMAE_COMMAND_SRC_VFPF_SHIFT 6 3106#define DMAE_COMMAND_RESERVED1 (0x1<<7) 3107#define DMAE_COMMAND_RESERVED1_SHIFT 7 3108#define DMAE_COMMAND_DST_VFID (0x3F<<8) 3109#define DMAE_COMMAND_DST_VFID_SHIFT 8 3110#define DMAE_COMMAND_DST_VFPF (0x1<<14) 3111#define DMAE_COMMAND_DST_VFPF_SHIFT 14 3112#define DMAE_COMMAND_RESERVED2 (0x1<<15) 3113#define DMAE_COMMAND_RESERVED2_SHIFT 15 3114#endif 3115 u32 comp_addr_lo; 3116 u32 comp_addr_hi; 3117 u32 comp_val; 3118 u32 crc32; 3119 u32 crc32_c; 3120#if defined(__BIG_ENDIAN) 3121 u16 crc16_c; 3122 u16 crc16; 3123#elif defined(__LITTLE_ENDIAN) 3124 u16 crc16; 3125 u16 crc16_c; 3126#endif 3127#if defined(__BIG_ENDIAN) 3128 u16 reserved3; 3129 u16 crc_t10; 3130#elif defined(__LITTLE_ENDIAN) 3131 u16 crc_t10; 3132 u16 reserved3; 3133#endif 3134#if defined(__BIG_ENDIAN) 3135 u16 xsum8; 3136 u16 xsum16; 3137#elif defined(__LITTLE_ENDIAN) 3138 u16 xsum16; 3139 u16 xsum8; 3140#endif 3141}; 3142 3143 3144/* 3145 * common data for all protocols 3146 */ 3147struct doorbell_hdr { 3148 u8 header; 3149#define DOORBELL_HDR_RX (0x1<<0) 3150#define DOORBELL_HDR_RX_SHIFT 0 3151#define DOORBELL_HDR_DB_TYPE (0x1<<1) 3152#define DOORBELL_HDR_DB_TYPE_SHIFT 1 3153#define DOORBELL_HDR_DPM_SIZE (0x3<<2) 3154#define DOORBELL_HDR_DPM_SIZE_SHIFT 2 3155#define DOORBELL_HDR_CONN_TYPE (0xF<<4) 3156#define DOORBELL_HDR_CONN_TYPE_SHIFT 4 3157}; 3158 3159/* 3160 * Ethernet doorbell 3161 */ 3162struct eth_tx_doorbell { 3163#if defined(__BIG_ENDIAN) 3164 u16 npackets; 3165 u8 params; 3166#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 3167#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3168#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 3169#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3170#define ETH_TX_DOORBELL_SPARE (0x1<<7) 3171#define ETH_TX_DOORBELL_SPARE_SHIFT 7 3172 struct doorbell_hdr hdr; 3173#elif defined(__LITTLE_ENDIAN) 3174 struct doorbell_hdr hdr; 3175 u8 params; 3176#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 3177#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3178#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 3179#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3180#define ETH_TX_DOORBELL_SPARE (0x1<<7) 3181#define ETH_TX_DOORBELL_SPARE_SHIFT 7 3182 u16 npackets; 3183#endif 3184}; 3185 3186 3187/* 3188 * 3 lines. status block 3189 */ 3190struct hc_status_block_e1x { 3191 __le16 index_values[HC_SB_MAX_INDICES_E1X]; 3192 __le16 running_index[HC_SB_MAX_SM]; 3193 __le32 rsrv[11]; 3194}; 3195 3196/* 3197 * host status block 3198 */ 3199struct host_hc_status_block_e1x { 3200 struct hc_status_block_e1x sb; 3201}; 3202 3203 3204/* 3205 * 3 lines. status block 3206 */ 3207struct hc_status_block_e2 { 3208 __le16 index_values[HC_SB_MAX_INDICES_E2]; 3209 __le16 running_index[HC_SB_MAX_SM]; 3210 __le32 reserved[11]; 3211}; 3212 3213/* 3214 * host status block 3215 */ 3216struct host_hc_status_block_e2 { 3217 struct hc_status_block_e2 sb; 3218}; 3219 3220 3221/* 3222 * 5 lines. slow-path status block 3223 */ 3224struct hc_sp_status_block { 3225 __le16 index_values[HC_SP_SB_MAX_INDICES]; 3226 __le16 running_index; 3227 __le16 rsrv; 3228 u32 rsrv1; 3229}; 3230 3231/* 3232 * host status block 3233 */ 3234struct host_sp_status_block { 3235 struct atten_sp_status_block atten_status_block; 3236 struct hc_sp_status_block sp_sb; 3237}; 3238 3239 3240/* 3241 * IGU driver acknowledgment register 3242 */ 3243struct igu_ack_register { 3244#if defined(__BIG_ENDIAN) 3245 u16 sb_id_and_flags; 3246#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 3247#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3248#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 3249#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3250#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 3251#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3252#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 3253#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3254#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 3255#define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3256 u16 status_block_index; 3257#elif defined(__LITTLE_ENDIAN) 3258 u16 status_block_index; 3259 u16 sb_id_and_flags; 3260#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 3261#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3262#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 3263#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3264#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 3265#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3266#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 3267#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3268#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 3269#define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3270#endif 3271}; 3272 3273 3274/* 3275 * IGU driver acknowledgement register 3276 */ 3277struct igu_backward_compatible { 3278 u32 sb_id_and_flags; 3279#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) 3280#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 3281#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) 3282#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 3283#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) 3284#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 3285#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) 3286#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 3287#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) 3288#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 3289#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) 3290#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 3291 u32 reserved_2; 3292}; 3293 3294 3295/* 3296 * IGU driver acknowledgement register 3297 */ 3298struct igu_regular { 3299 u32 sb_id_and_flags; 3300#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) 3301#define IGU_REGULAR_SB_INDEX_SHIFT 0 3302#define IGU_REGULAR_RESERVED0 (0x1<<20) 3303#define IGU_REGULAR_RESERVED0_SHIFT 20 3304#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) 3305#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 3306#define IGU_REGULAR_BUPDATE (0x1<<24) 3307#define IGU_REGULAR_BUPDATE_SHIFT 24 3308#define IGU_REGULAR_ENABLE_INT (0x3<<25) 3309#define IGU_REGULAR_ENABLE_INT_SHIFT 25 3310#define IGU_REGULAR_RESERVED_1 (0x1<<27) 3311#define IGU_REGULAR_RESERVED_1_SHIFT 27 3312#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) 3313#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 3314#define IGU_REGULAR_CLEANUP_SET (0x1<<30) 3315#define IGU_REGULAR_CLEANUP_SET_SHIFT 30 3316#define IGU_REGULAR_BCLEANUP (0x1<<31) 3317#define IGU_REGULAR_BCLEANUP_SHIFT 31 3318 u32 reserved_2; 3319}; 3320 3321/* 3322 * IGU driver acknowledgement register 3323 */ 3324union igu_consprod_reg { 3325 struct igu_regular regular; 3326 struct igu_backward_compatible backward_compatible; 3327}; 3328 3329 3330/* 3331 * Igu control commands 3332 */ 3333enum igu_ctrl_cmd { 3334 IGU_CTRL_CMD_TYPE_RD, 3335 IGU_CTRL_CMD_TYPE_WR, 3336 MAX_IGU_CTRL_CMD 3337}; 3338 3339 3340/* 3341 * Control register for the IGU command register 3342 */ 3343struct igu_ctrl_reg { 3344 u32 ctrl_data; 3345#define IGU_CTRL_REG_ADDRESS (0xFFF<<0) 3346#define IGU_CTRL_REG_ADDRESS_SHIFT 0 3347#define IGU_CTRL_REG_FID (0x7F<<12) 3348#define IGU_CTRL_REG_FID_SHIFT 12 3349#define IGU_CTRL_REG_RESERVED (0x1<<19) 3350#define IGU_CTRL_REG_RESERVED_SHIFT 19 3351#define IGU_CTRL_REG_TYPE (0x1<<20) 3352#define IGU_CTRL_REG_TYPE_SHIFT 20 3353#define IGU_CTRL_REG_UNUSED (0x7FF<<21) 3354#define IGU_CTRL_REG_UNUSED_SHIFT 21 3355}; 3356 3357 3358/* 3359 * Igu interrupt command 3360 */ 3361enum igu_int_cmd { 3362 IGU_INT_ENABLE, 3363 IGU_INT_DISABLE, 3364 IGU_INT_NOP, 3365 IGU_INT_NOP2, 3366 MAX_IGU_INT_CMD 3367}; 3368 3369 3370/* 3371 * Igu segments 3372 */ 3373enum igu_seg_access { 3374 IGU_SEG_ACCESS_NORM, 3375 IGU_SEG_ACCESS_DEF, 3376 IGU_SEG_ACCESS_ATTN, 3377 MAX_IGU_SEG_ACCESS 3378}; 3379 3380 3381/* 3382 * Parser parsing flags field 3383 */ 3384struct parsing_flags { 3385 __le16 flags; 3386#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) 3387#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 3388#define PARSING_FLAGS_VLAN (0x1<<1) 3389#define PARSING_FLAGS_VLAN_SHIFT 1 3390#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) 3391#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 3392#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) 3393#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 3394#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) 3395#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 3396#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) 3397#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 3398#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) 3399#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 3400#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) 3401#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 3402#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) 3403#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 3404#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) 3405#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 3406#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) 3407#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 3408#define PARSING_FLAGS_LLC_SNAP (0x1<<13) 3409#define PARSING_FLAGS_LLC_SNAP_SHIFT 13 3410#define PARSING_FLAGS_RESERVED0 (0x3<<14) 3411#define PARSING_FLAGS_RESERVED0_SHIFT 14 3412}; 3413 3414 3415/* 3416 * Parsing flags for TCP ACK type 3417 */ 3418enum prs_flags_ack_type { 3419 PRS_FLAG_PUREACK_PIGGY, 3420 PRS_FLAG_PUREACK_PURE, 3421 MAX_PRS_FLAGS_ACK_TYPE 3422}; 3423 3424 3425/* 3426 * Parsing flags for Ethernet address type 3427 */ 3428enum prs_flags_eth_addr_type { 3429 PRS_FLAG_ETHTYPE_NON_UNICAST, 3430 PRS_FLAG_ETHTYPE_UNICAST, 3431 MAX_PRS_FLAGS_ETH_ADDR_TYPE 3432}; 3433 3434 3435/* 3436 * Parsing flags for over-ethernet protocol 3437 */ 3438enum prs_flags_over_eth { 3439 PRS_FLAG_OVERETH_UNKNOWN, 3440 PRS_FLAG_OVERETH_IPV4, 3441 PRS_FLAG_OVERETH_IPV6, 3442 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 3443 MAX_PRS_FLAGS_OVER_ETH 3444}; 3445 3446 3447/* 3448 * Parsing flags for over-IP protocol 3449 */ 3450enum prs_flags_over_ip { 3451 PRS_FLAG_OVERIP_UNKNOWN, 3452 PRS_FLAG_OVERIP_TCP, 3453 PRS_FLAG_OVERIP_UDP, 3454 MAX_PRS_FLAGS_OVER_IP 3455}; 3456 3457 3458/* 3459 * SDM operation gen command (generate aggregative interrupt) 3460 */ 3461struct sdm_op_gen { 3462 __le32 command; 3463#define SDM_OP_GEN_COMP_PARAM (0x1F<<0) 3464#define SDM_OP_GEN_COMP_PARAM_SHIFT 0 3465#define SDM_OP_GEN_COMP_TYPE (0x7<<5) 3466#define SDM_OP_GEN_COMP_TYPE_SHIFT 5 3467#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) 3468#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 3469#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) 3470#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 3471#define SDM_OP_GEN_RESERVED (0x7FFF<<17) 3472#define SDM_OP_GEN_RESERVED_SHIFT 17 3473}; 3474 3475 3476/* 3477 * Timers connection context 3478 */ 3479struct timers_block_context { 3480 u32 __reserved_0; 3481 u32 __reserved_1; 3482 u32 __reserved_2; 3483 u32 flags; 3484#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) 3485#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 3486#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) 3487#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 3488#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) 3489#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 3490}; 3491 3492 3493/* 3494 * The eth aggregative context of Tstorm 3495 */ 3496struct tstorm_eth_ag_context { 3497 u32 __reserved0[14]; 3498}; 3499 3500 3501/* 3502 * The eth aggregative context of Ustorm 3503 */ 3504struct ustorm_eth_ag_context { 3505 u32 __reserved0; 3506#if defined(__BIG_ENDIAN) 3507 u8 cdu_usage; 3508 u8 __reserved2; 3509 u16 __reserved1; 3510#elif defined(__LITTLE_ENDIAN) 3511 u16 __reserved1; 3512 u8 __reserved2; 3513 u8 cdu_usage; 3514#endif 3515 u32 __reserved3[6]; 3516}; 3517 3518 3519/* 3520 * The eth aggregative context of Xstorm 3521 */ 3522struct xstorm_eth_ag_context { 3523 u32 reserved0; 3524#if defined(__BIG_ENDIAN) 3525 u8 cdu_reserved; 3526 u8 reserved2; 3527 u16 reserved1; 3528#elif defined(__LITTLE_ENDIAN) 3529 u16 reserved1; 3530 u8 reserved2; 3531 u8 cdu_reserved; 3532#endif 3533 u32 reserved3[30]; 3534}; 3535 3536 3537/* 3538 * doorbell message sent to the chip 3539 */ 3540struct doorbell { 3541#if defined(__BIG_ENDIAN) 3542 u16 zero_fill2; 3543 u8 zero_fill1; 3544 struct doorbell_hdr header; 3545#elif defined(__LITTLE_ENDIAN) 3546 struct doorbell_hdr header; 3547 u8 zero_fill1; 3548 u16 zero_fill2; 3549#endif 3550}; 3551 3552 3553/* 3554 * doorbell message sent to the chip 3555 */ 3556struct doorbell_set_prod { 3557#if defined(__BIG_ENDIAN) 3558 u16 prod; 3559 u8 zero_fill1; 3560 struct doorbell_hdr header; 3561#elif defined(__LITTLE_ENDIAN) 3562 struct doorbell_hdr header; 3563 u8 zero_fill1; 3564 u16 prod; 3565#endif 3566}; 3567 3568 3569struct regpair { 3570 __le32 lo; 3571 __le32 hi; 3572}; 3573 3574struct regpair_native { 3575 u32 lo; 3576 u32 hi; 3577}; 3578 3579/* 3580 * Classify rule opcodes in E2/E3 3581 */ 3582enum classify_rule { 3583 CLASSIFY_RULE_OPCODE_MAC, 3584 CLASSIFY_RULE_OPCODE_VLAN, 3585 CLASSIFY_RULE_OPCODE_PAIR, 3586 CLASSIFY_RULE_OPCODE_VXLAN, 3587 MAX_CLASSIFY_RULE 3588}; 3589 3590 3591/* 3592 * Classify rule types in E2/E3 3593 */ 3594enum classify_rule_action_type { 3595 CLASSIFY_RULE_REMOVE, 3596 CLASSIFY_RULE_ADD, 3597 MAX_CLASSIFY_RULE_ACTION_TYPE 3598}; 3599 3600 3601/* 3602 * client init ramrod data 3603 */ 3604struct client_init_general_data { 3605 u8 client_id; 3606 u8 statistics_counter_id; 3607 u8 statistics_en_flg; 3608 u8 is_fcoe_flg; 3609 u8 activate_flg; 3610 u8 sp_client_id; 3611 __le16 mtu; 3612 u8 statistics_zero_flg; 3613 u8 func_id; 3614 u8 cos; 3615 u8 traffic_type; 3616 u8 fp_hsi_ver; 3617 u8 reserved0[3]; 3618}; 3619 3620 3621/* 3622 * client init rx data 3623 */ 3624struct client_init_rx_data { 3625 u8 tpa_en; 3626#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) 3627#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 3628#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) 3629#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 3630#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) 3631#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 3632#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) 3633#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 3634 u8 vmqueue_mode_en_flg; 3635 u8 extra_data_over_sgl_en_flg; 3636 u8 cache_line_alignment_log_size; 3637 u8 enable_dynamic_hc; 3638 u8 max_sges_for_packet; 3639 u8 client_qzone_id; 3640 u8 drop_ip_cs_err_flg; 3641 u8 drop_tcp_cs_err_flg; 3642 u8 drop_ttl0_flg; 3643 u8 drop_udp_cs_err_flg; 3644 u8 inner_vlan_removal_enable_flg; 3645 u8 outer_vlan_removal_enable_flg; 3646 u8 status_block_id; 3647 u8 rx_sb_index_number; 3648 u8 dont_verify_rings_pause_thr_flg; 3649 u8 max_tpa_queues; 3650 u8 silent_vlan_removal_flg; 3651 __le16 max_bytes_on_bd; 3652 __le16 sge_buff_size; 3653 u8 approx_mcast_engine_id; 3654 u8 rss_engine_id; 3655 struct regpair bd_page_base; 3656 struct regpair sge_page_base; 3657 struct regpair cqe_page_base; 3658 u8 is_leading_rss; 3659 u8 is_approx_mcast; 3660 __le16 max_agg_size; 3661 __le16 state; 3662#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) 3663#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 3664#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) 3665#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 3666#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3667#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3668#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) 3669#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 3670#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) 3671#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 3672#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) 3673#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 3674#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) 3675#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 3676#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) 3677#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 3678 __le16 cqe_pause_thr_low; 3679 __le16 cqe_pause_thr_high; 3680 __le16 bd_pause_thr_low; 3681 __le16 bd_pause_thr_high; 3682 __le16 sge_pause_thr_low; 3683 __le16 sge_pause_thr_high; 3684 __le16 rx_cos_mask; 3685 __le16 silent_vlan_value; 3686 __le16 silent_vlan_mask; 3687 u8 handle_ptp_pkts_flg; 3688 u8 reserved6[3]; 3689 __le32 reserved7; 3690}; 3691 3692/* 3693 * client init tx data 3694 */ 3695struct client_init_tx_data { 3696 u8 enforce_security_flg; 3697 u8 tx_status_block_id; 3698 u8 tx_sb_index_number; 3699 u8 tss_leading_client_id; 3700 u8 tx_switching_flg; 3701 u8 anti_spoofing_flg; 3702 __le16 default_vlan; 3703 struct regpair tx_bd_page_base; 3704 __le16 state; 3705#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) 3706#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 3707#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) 3708#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 3709#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) 3710#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 3711#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) 3712#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 3713#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) 3714#define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 3715 u8 default_vlan_flg; 3716 u8 force_default_pri_flg; 3717 u8 tunnel_lso_inc_ip_id; 3718 u8 refuse_outband_vlan_flg; 3719 u8 tunnel_non_lso_pcsum_location; 3720 u8 tunnel_non_lso_outer_ip_csum_location; 3721}; 3722 3723/* 3724 * client init ramrod data 3725 */ 3726struct client_init_ramrod_data { 3727 struct client_init_general_data general; 3728 struct client_init_rx_data rx; 3729 struct client_init_tx_data tx; 3730}; 3731 3732 3733/* 3734 * client update ramrod data 3735 */ 3736struct client_update_ramrod_data { 3737 u8 client_id; 3738 u8 func_id; 3739 u8 inner_vlan_removal_enable_flg; 3740 u8 inner_vlan_removal_change_flg; 3741 u8 outer_vlan_removal_enable_flg; 3742 u8 outer_vlan_removal_change_flg; 3743 u8 anti_spoofing_enable_flg; 3744 u8 anti_spoofing_change_flg; 3745 u8 activate_flg; 3746 u8 activate_change_flg; 3747 __le16 default_vlan; 3748 u8 default_vlan_enable_flg; 3749 u8 default_vlan_change_flg; 3750 __le16 silent_vlan_value; 3751 __le16 silent_vlan_mask; 3752 u8 silent_vlan_removal_flg; 3753 u8 silent_vlan_change_flg; 3754 u8 refuse_outband_vlan_flg; 3755 u8 refuse_outband_vlan_change_flg; 3756 u8 tx_switching_flg; 3757 u8 tx_switching_change_flg; 3758 u8 handle_ptp_pkts_flg; 3759 u8 handle_ptp_pkts_change_flg; 3760 __le16 reserved1; 3761 __le32 echo; 3762}; 3763 3764 3765/* 3766 * The eth storm context of Cstorm 3767 */ 3768struct cstorm_eth_st_context { 3769 u32 __reserved0[4]; 3770}; 3771 3772 3773struct double_regpair { 3774 u32 regpair0_lo; 3775 u32 regpair0_hi; 3776 u32 regpair1_lo; 3777 u32 regpair1_hi; 3778}; 3779 3780/* 2nd parse bd type used in ethernet tx BDs */ 3781enum eth_2nd_parse_bd_type { 3782 ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL, 3783 MAX_ETH_2ND_PARSE_BD_TYPE 3784}; 3785 3786/* 3787 * Ethernet address typesm used in ethernet tx BDs 3788 */ 3789enum eth_addr_type { 3790 UNKNOWN_ADDRESS, 3791 UNICAST_ADDRESS, 3792 MULTICAST_ADDRESS, 3793 BROADCAST_ADDRESS, 3794 MAX_ETH_ADDR_TYPE 3795}; 3796 3797 3798/* 3799 * 3800 */ 3801struct eth_classify_cmd_header { 3802 u8 cmd_general_data; 3803#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) 3804#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 3805#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) 3806#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 3807#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) 3808#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 3809#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) 3810#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 3811#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) 3812#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 3813 u8 func_id; 3814 u8 client_id; 3815 u8 reserved1; 3816}; 3817 3818 3819/* 3820 * header for eth classification config ramrod 3821 */ 3822struct eth_classify_header { 3823 u8 rule_cnt; 3824 u8 reserved0; 3825 __le16 reserved1; 3826 __le32 echo; 3827}; 3828 3829 3830/* 3831 * Command for adding/removing a MAC classification rule 3832 */ 3833struct eth_classify_mac_cmd { 3834 struct eth_classify_cmd_header header; 3835 __le16 reserved0; 3836 __le16 inner_mac; 3837 __le16 mac_lsb; 3838 __le16 mac_mid; 3839 __le16 mac_msb; 3840 __le16 reserved1; 3841}; 3842 3843 3844/* 3845 * Command for adding/removing a MAC-VLAN pair classification rule 3846 */ 3847struct eth_classify_pair_cmd { 3848 struct eth_classify_cmd_header header; 3849 __le16 reserved0; 3850 __le16 inner_mac; 3851 __le16 mac_lsb; 3852 __le16 mac_mid; 3853 __le16 mac_msb; 3854 __le16 vlan; 3855}; 3856 3857 3858/* 3859 * Command for adding/removing a VLAN classification rule 3860 */ 3861struct eth_classify_vlan_cmd { 3862 struct eth_classify_cmd_header header; 3863 __le32 reserved0; 3864 __le32 reserved1; 3865 __le16 reserved2; 3866 __le16 vlan; 3867}; 3868 3869/* 3870 * Command for adding/removing a VXLAN classification rule 3871 */ 3872struct eth_classify_vxlan_cmd { 3873 struct eth_classify_cmd_header header; 3874 __le32 vni; 3875 __le16 inner_mac_lsb; 3876 __le16 inner_mac_mid; 3877 __le16 inner_mac_msb; 3878 __le16 reserved1; 3879}; 3880 3881/* 3882 * union for eth classification rule 3883 */ 3884union eth_classify_rule_cmd { 3885 struct eth_classify_mac_cmd mac; 3886 struct eth_classify_vlan_cmd vlan; 3887 struct eth_classify_pair_cmd pair; 3888 struct eth_classify_vxlan_cmd vxlan; 3889}; 3890 3891/* 3892 * parameters for eth classification configuration ramrod 3893 */ 3894struct eth_classify_rules_ramrod_data { 3895 struct eth_classify_header header; 3896 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3897}; 3898 3899 3900/* 3901 * The data contain client ID need to the ramrod 3902 */ 3903struct eth_common_ramrod_data { 3904 __le32 client_id; 3905 __le32 reserved1; 3906}; 3907 3908 3909/* 3910 * The eth storm context of Ustorm 3911 */ 3912struct ustorm_eth_st_context { 3913 u32 reserved0[52]; 3914}; 3915 3916/* 3917 * The eth storm context of Tstorm 3918 */ 3919struct tstorm_eth_st_context { 3920 u32 __reserved0[28]; 3921}; 3922 3923/* 3924 * The eth storm context of Xstorm 3925 */ 3926struct xstorm_eth_st_context { 3927 u32 reserved0[60]; 3928}; 3929 3930/* 3931 * Ethernet connection context 3932 */ 3933struct eth_context { 3934 struct ustorm_eth_st_context ustorm_st_context; 3935 struct tstorm_eth_st_context tstorm_st_context; 3936 struct xstorm_eth_ag_context xstorm_ag_context; 3937 struct tstorm_eth_ag_context tstorm_ag_context; 3938 struct cstorm_eth_ag_context cstorm_ag_context; 3939 struct ustorm_eth_ag_context ustorm_ag_context; 3940 struct timers_block_context timers_context; 3941 struct xstorm_eth_st_context xstorm_st_context; 3942 struct cstorm_eth_st_context cstorm_st_context; 3943}; 3944 3945 3946/* 3947 * union for sgl and raw data. 3948 */ 3949union eth_sgl_or_raw_data { 3950 __le16 sgl[8]; 3951 u32 raw_data[4]; 3952}; 3953 3954/* 3955 * eth FP end aggregation CQE parameters struct 3956 */ 3957struct eth_end_agg_rx_cqe { 3958 u8 type_error_flags; 3959#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) 3960#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 3961#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) 3962#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 3963#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) 3964#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 3965 u8 reserved1; 3966 u8 queue_index; 3967 u8 reserved2; 3968 __le32 timestamp_delta; 3969 __le16 num_of_coalesced_segs; 3970 __le16 pkt_len; 3971 u8 pure_ack_count; 3972 u8 reserved3; 3973 __le16 reserved4; 3974 union eth_sgl_or_raw_data sgl_or_raw_data; 3975 __le32 reserved5[8]; 3976}; 3977 3978 3979/* 3980 * regular eth FP CQE parameters struct 3981 */ 3982struct eth_fast_path_rx_cqe { 3983 u8 type_error_flags; 3984#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) 3985#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 3986#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) 3987#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 3988#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) 3989#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 3990#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) 3991#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 3992#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) 3993#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 3994#define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6) 3995#define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6 3996#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7) 3997#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7 3998 u8 status_flags; 3999#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) 4000#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 4001#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) 4002#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 4003#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) 4004#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 4005#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) 4006#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 4007#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) 4008#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 4009#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) 4010#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 4011 u8 queue_index; 4012 u8 placement_offset; 4013 __le32 rss_hash_result; 4014 __le16 vlan_tag; 4015 __le16 pkt_len_or_gro_seg_len; 4016 __le16 len_on_bd; 4017 struct parsing_flags pars_flags; 4018 union eth_sgl_or_raw_data sgl_or_raw_data; 4019 u8 tunn_type; 4020 u8 tunn_inner_hdrs_offset; 4021 __le16 reserved1; 4022 __le32 tunn_tenant_id; 4023 __le32 padding[5]; 4024 u32 marker; 4025}; 4026 4027 4028/* 4029 * Command for setting classification flags for a client 4030 */ 4031struct eth_filter_rules_cmd { 4032 u8 cmd_general_data; 4033#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) 4034#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 4035#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) 4036#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 4037#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) 4038#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 4039 u8 func_id; 4040 u8 client_id; 4041 u8 reserved1; 4042 __le16 state; 4043#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) 4044#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 4045#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) 4046#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 4047#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) 4048#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 4049#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) 4050#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 4051#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) 4052#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 4053#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) 4054#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 4055#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) 4056#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 4057#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) 4058#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 4059 __le16 reserved3; 4060 struct regpair reserved4; 4061}; 4062 4063 4064/* 4065 * parameters for eth classification filters ramrod 4066 */ 4067struct eth_filter_rules_ramrod_data { 4068 struct eth_classify_header header; 4069 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 4070}; 4071 4072/* Hsi version */ 4073enum eth_fp_hsi_ver { 4074 ETH_FP_HSI_VER_0, 4075 ETH_FP_HSI_VER_1, 4076 ETH_FP_HSI_VER_2, 4077 MAX_ETH_FP_HSI_VER 4078}; 4079 4080/* 4081 * parameters for eth classification configuration ramrod 4082 */ 4083struct eth_general_rules_ramrod_data { 4084 struct eth_classify_header header; 4085 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 4086}; 4087 4088 4089/* 4090 * The data for Halt ramrod 4091 */ 4092struct eth_halt_ramrod_data { 4093 __le32 client_id; 4094 __le32 reserved0; 4095}; 4096 4097 4098/* 4099 * destination and source mac address. 4100 */ 4101struct eth_mac_addresses { 4102#if defined(__BIG_ENDIAN) 4103 __le16 dst_mid; 4104 __le16 dst_lo; 4105#elif defined(__LITTLE_ENDIAN) 4106 __le16 dst_lo; 4107 __le16 dst_mid; 4108#endif 4109#if defined(__BIG_ENDIAN) 4110 __le16 src_lo; 4111 __le16 dst_hi; 4112#elif defined(__LITTLE_ENDIAN) 4113 __le16 dst_hi; 4114 __le16 src_lo; 4115#endif 4116#if defined(__BIG_ENDIAN) 4117 __le16 src_hi; 4118 __le16 src_mid; 4119#elif defined(__LITTLE_ENDIAN) 4120 __le16 src_mid; 4121 __le16 src_hi; 4122#endif 4123}; 4124 4125/* tunneling related data */ 4126struct eth_tunnel_data { 4127 __le16 dst_lo; 4128 __le16 dst_mid; 4129 __le16 dst_hi; 4130 __le16 fw_ip_hdr_csum; 4131 __le16 pseudo_csum; 4132 u8 ip_hdr_start_inner_w; 4133 u8 flags; 4134#define ETH_TUNNEL_DATA_IPV6_OUTER (0x1<<0) 4135#define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0 4136#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) 4137#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1 4138}; 4139 4140/* union for mac addresses and for tunneling data. 4141 * considered as tunneling data only if (tunnel_exist == 1). 4142 */ 4143union eth_mac_addr_or_tunnel_data { 4144 struct eth_mac_addresses mac_addr; 4145 struct eth_tunnel_data tunnel_data; 4146}; 4147 4148/*Command for setting multicast classification for a client */ 4149struct eth_multicast_rules_cmd { 4150 u8 cmd_general_data; 4151#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) 4152#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 4153#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) 4154#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 4155#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) 4156#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 4157#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) 4158#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 4159 u8 func_id; 4160 u8 bin_id; 4161 u8 engine_id; 4162 __le32 reserved2; 4163 struct regpair reserved3; 4164}; 4165 4166/* 4167 * parameters for multicast classification ramrod 4168 */ 4169struct eth_multicast_rules_ramrod_data { 4170 struct eth_classify_header header; 4171 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 4172}; 4173 4174/* 4175 * Place holder for ramrods protocol specific data 4176 */ 4177struct ramrod_data { 4178 __le32 data_lo; 4179 __le32 data_hi; 4180}; 4181 4182/* 4183 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 4184 */ 4185union eth_ramrod_data { 4186 struct ramrod_data general; 4187}; 4188 4189 4190/* 4191 * RSS toeplitz hash type, as reported in CQE 4192 */ 4193enum eth_rss_hash_type { 4194 DEFAULT_HASH_TYPE, 4195 IPV4_HASH_TYPE, 4196 TCP_IPV4_HASH_TYPE, 4197 IPV6_HASH_TYPE, 4198 TCP_IPV6_HASH_TYPE, 4199 VLAN_PRI_HASH_TYPE, 4200 E1HOV_PRI_HASH_TYPE, 4201 DSCP_HASH_TYPE, 4202 MAX_ETH_RSS_HASH_TYPE 4203}; 4204 4205 4206/* 4207 * Ethernet RSS mode 4208 */ 4209enum eth_rss_mode { 4210 ETH_RSS_MODE_DISABLED, 4211 ETH_RSS_MODE_REGULAR, 4212 ETH_RSS_MODE_VLAN_PRI, 4213 ETH_RSS_MODE_E1HOV_PRI, 4214 ETH_RSS_MODE_IP_DSCP, 4215 MAX_ETH_RSS_MODE 4216}; 4217 4218 4219/* 4220 * parameters for RSS update ramrod (E2) 4221 */ 4222struct eth_rss_update_ramrod_data { 4223 u8 rss_engine_id; 4224 u8 rss_mode; 4225 __le16 capabilities; 4226#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) 4227#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 4228#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) 4229#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 4230#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) 4231#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 4232#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3) 4233#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3 4234#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4) 4235#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4 4236#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5) 4237#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5 4238#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6) 4239#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6 4240#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7) 4241#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7 4242#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1<<8) 4243#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8 4244#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<9) 4245#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9 4246#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F<<10) 4247#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10 4248 u8 rss_result_mask; 4249 u8 reserved3; 4250 __le16 reserved4; 4251 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; 4252 __le32 rss_key[T_ETH_RSS_KEY]; 4253 __le32 echo; 4254 __le32 reserved5; 4255}; 4256 4257 4258/* 4259 * The eth Rx Buffer Descriptor 4260 */ 4261struct eth_rx_bd { 4262 __le32 addr_lo; 4263 __le32 addr_hi; 4264}; 4265 4266 4267/* 4268 * Eth Rx Cqe structure- general structure for ramrods 4269 */ 4270struct common_ramrod_eth_rx_cqe { 4271 u8 ramrod_type; 4272#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) 4273#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 4274#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) 4275#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 4276#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) 4277#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 4278 u8 conn_type; 4279 __le16 reserved1; 4280 __le32 conn_and_cmd_data; 4281#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) 4282#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 4283#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) 4284#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 4285 struct ramrod_data protocol_data; 4286 __le32 echo; 4287 __le32 reserved2[11]; 4288}; 4289 4290/* 4291 * Rx Last CQE in page (in ETH) 4292 */ 4293struct eth_rx_cqe_next_page { 4294 __le32 addr_lo; 4295 __le32 addr_hi; 4296 __le32 reserved[14]; 4297}; 4298 4299/* 4300 * union for all eth rx cqe types (fix their sizes) 4301 */ 4302union eth_rx_cqe { 4303 struct eth_fast_path_rx_cqe fast_path_cqe; 4304 struct common_ramrod_eth_rx_cqe ramrod_cqe; 4305 struct eth_rx_cqe_next_page next_page_cqe; 4306 struct eth_end_agg_rx_cqe end_agg_cqe; 4307}; 4308 4309 4310/* 4311 * Values for RX ETH CQE type field 4312 */ 4313enum eth_rx_cqe_type { 4314 RX_ETH_CQE_TYPE_ETH_FASTPATH, 4315 RX_ETH_CQE_TYPE_ETH_RAMROD, 4316 RX_ETH_CQE_TYPE_ETH_START_AGG, 4317 RX_ETH_CQE_TYPE_ETH_STOP_AGG, 4318 MAX_ETH_RX_CQE_TYPE 4319}; 4320 4321 4322/* 4323 * Type of SGL/Raw field in ETH RX fast path CQE 4324 */ 4325enum eth_rx_fp_sel { 4326 ETH_FP_CQE_REGULAR, 4327 ETH_FP_CQE_RAW, 4328 MAX_ETH_RX_FP_SEL 4329}; 4330 4331 4332/* 4333 * The eth Rx SGE Descriptor 4334 */ 4335struct eth_rx_sge { 4336 __le32 addr_lo; 4337 __le32 addr_hi; 4338}; 4339 4340 4341/* 4342 * common data for all protocols 4343 */ 4344struct spe_hdr { 4345 __le32 conn_and_cmd_data; 4346#define SPE_HDR_CID (0xFFFFFF<<0) 4347#define SPE_HDR_CID_SHIFT 0 4348#define SPE_HDR_CMD_ID (0xFF<<24) 4349#define SPE_HDR_CMD_ID_SHIFT 24 4350 __le16 type; 4351#define SPE_HDR_CONN_TYPE (0xFF<<0) 4352#define SPE_HDR_CONN_TYPE_SHIFT 0 4353#define SPE_HDR_FUNCTION_ID (0xFF<<8) 4354#define SPE_HDR_FUNCTION_ID_SHIFT 8 4355 __le16 reserved1; 4356}; 4357 4358/* 4359 * specific data for ethernet slow path element 4360 */ 4361union eth_specific_data { 4362 u8 protocol_data[8]; 4363 struct regpair client_update_ramrod_data; 4364 struct regpair client_init_ramrod_init_data; 4365 struct eth_halt_ramrod_data halt_ramrod_data; 4366 struct regpair update_data_addr; 4367 struct eth_common_ramrod_data common_ramrod_data; 4368 struct regpair classify_cfg_addr; 4369 struct regpair filter_cfg_addr; 4370 struct regpair mcast_cfg_addr; 4371}; 4372 4373/* 4374 * Ethernet slow path element 4375 */ 4376struct eth_spe { 4377 struct spe_hdr hdr; 4378 union eth_specific_data data; 4379}; 4380 4381 4382/* 4383 * Ethernet command ID for slow path elements 4384 */ 4385enum eth_spqe_cmd_id { 4386 RAMROD_CMD_ID_ETH_UNUSED, 4387 RAMROD_CMD_ID_ETH_CLIENT_SETUP, 4388 RAMROD_CMD_ID_ETH_HALT, 4389 RAMROD_CMD_ID_ETH_FORWARD_SETUP, 4390 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, 4391 RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 4392 RAMROD_CMD_ID_ETH_EMPTY, 4393 RAMROD_CMD_ID_ETH_TERMINATE, 4394 RAMROD_CMD_ID_ETH_TPA_UPDATE, 4395 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, 4396 RAMROD_CMD_ID_ETH_FILTER_RULES, 4397 RAMROD_CMD_ID_ETH_MULTICAST_RULES, 4398 RAMROD_CMD_ID_ETH_RSS_UPDATE, 4399 RAMROD_CMD_ID_ETH_SET_MAC, 4400 MAX_ETH_SPQE_CMD_ID 4401}; 4402 4403 4404/* 4405 * eth tpa update command 4406 */ 4407enum eth_tpa_update_command { 4408 TPA_UPDATE_NONE_COMMAND, 4409 TPA_UPDATE_ENABLE_COMMAND, 4410 TPA_UPDATE_DISABLE_COMMAND, 4411 MAX_ETH_TPA_UPDATE_COMMAND 4412}; 4413 4414/* In case of LSO over IPv4 tunnel, whether to increment 4415 * IP ID on external IP header or internal IP header 4416 */ 4417enum eth_tunnel_lso_inc_ip_id { 4418 EXT_HEADER, 4419 INT_HEADER, 4420 MAX_ETH_TUNNEL_LSO_INC_IP_ID 4421}; 4422 4423/* In case tunnel exist and L4 checksum offload, 4424 * the pseudo checksum location, on packet or on BD. 4425 */ 4426enum eth_tunnel_non_lso_csum_location { 4427 CSUM_ON_PKT, 4428 CSUM_ON_BD, 4429 MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION 4430}; 4431 4432enum eth_tunn_type { 4433 TUNN_TYPE_NONE, 4434 TUNN_TYPE_VXLAN, 4435 TUNN_TYPE_L2_GRE, 4436 TUNN_TYPE_IPV4_GRE, 4437 TUNN_TYPE_IPV6_GRE, 4438 TUNN_TYPE_L2_GENEVE, 4439 TUNN_TYPE_IPV4_GENEVE, 4440 TUNN_TYPE_IPV6_GENEVE, 4441 MAX_ETH_TUNN_TYPE 4442}; 4443 4444/* 4445 * Tx regular BD structure 4446 */ 4447struct eth_tx_bd { 4448 __le32 addr_lo; 4449 __le32 addr_hi; 4450 __le16 total_pkt_bytes; 4451 __le16 nbytes; 4452 u8 reserved[4]; 4453}; 4454 4455 4456/* 4457 * structure for easy accessibility to assembler 4458 */ 4459struct eth_tx_bd_flags { 4460 u8 as_bitfield; 4461#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) 4462#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 4463#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) 4464#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 4465#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) 4466#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 4467#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) 4468#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 4469#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) 4470#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 4471#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) 4472#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 4473#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) 4474#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 4475}; 4476 4477/* 4478 * The eth Tx Buffer Descriptor 4479 */ 4480struct eth_tx_start_bd { 4481 __le32 addr_lo; 4482 __le32 addr_hi; 4483 __le16 nbd; 4484 __le16 nbytes; 4485 __le16 vlan_or_ethertype; 4486 struct eth_tx_bd_flags bd_flags; 4487 u8 general_data; 4488#define ETH_TX_START_BD_HDR_NBDS (0x7<<0) 4489#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 4490#define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3) 4491#define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3 4492#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) 4493#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 4494#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) 4495#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 4496#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) 4497#define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 4498}; 4499 4500/* 4501 * Tx parsing BD structure for ETH E1/E1h 4502 */ 4503struct eth_tx_parse_bd_e1x { 4504 __le16 global_data; 4505#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) 4506#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 4507#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) 4508#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 4509#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) 4510#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 4511#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) 4512#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 4513#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) 4514#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 4515#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) 4516#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 4517 u8 tcp_flags; 4518#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) 4519#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 4520#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) 4521#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 4522#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) 4523#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 4524#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) 4525#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 4526#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) 4527#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 4528#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) 4529#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 4530#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) 4531#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 4532#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) 4533#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 4534 u8 ip_hlen_w; 4535 __le16 total_hlen_w; 4536 __le16 tcp_pseudo_csum; 4537 __le16 lso_mss; 4538 __le16 ip_id; 4539 __le32 tcp_send_seq; 4540}; 4541 4542/* 4543 * Tx parsing BD structure for ETH E2 4544 */ 4545struct eth_tx_parse_bd_e2 { 4546 union eth_mac_addr_or_tunnel_data data; 4547 __le32 parsing_data; 4548#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) 4549#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 4550#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) 4551#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 4552#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) 4553#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 4554#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) 4555#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 4556#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) 4557#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 4558}; 4559 4560/* 4561 * Tx 2nd parsing BD structure for ETH packet 4562 */ 4563struct eth_tx_parse_2nd_bd { 4564 __le16 global_data; 4565#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) 4566#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 4567#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) 4568#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4 4569#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) 4570#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 4571#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) 4572#define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 4573#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) 4574#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 4575#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) 4576#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 4577#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) 4578#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13 4579 u8 bd_type; 4580#define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0) 4581#define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0 4582#define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4) 4583#define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4 4584 u8 reserved3; 4585 u8 tcp_flags; 4586#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) 4587#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 4588#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) 4589#define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 4590#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) 4591#define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 4592#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) 4593#define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 4594#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) 4595#define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 4596#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) 4597#define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 4598#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) 4599#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 4600#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) 4601#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 4602 u8 reserved4; 4603 u8 tunnel_udp_hdr_start_w; 4604 u8 fw_ip_hdr_to_payload_w; 4605 __le16 fw_ip_csum_wo_len_flags_frag; 4606 __le16 hw_ip_id; 4607 __le32 tcp_send_seq; 4608}; 4609 4610/* The last BD in the BD memory will hold a pointer to the next BD memory */ 4611struct eth_tx_next_bd { 4612 __le32 addr_lo; 4613 __le32 addr_hi; 4614 u8 reserved[8]; 4615}; 4616 4617/* 4618 * union for 4 Bd types 4619 */ 4620union eth_tx_bd_types { 4621 struct eth_tx_start_bd start_bd; 4622 struct eth_tx_bd reg_bd; 4623 struct eth_tx_parse_bd_e1x parse_bd_e1x; 4624 struct eth_tx_parse_bd_e2 parse_bd_e2; 4625 struct eth_tx_parse_2nd_bd parse_2nd_bd; 4626 struct eth_tx_next_bd next_bd; 4627}; 4628 4629/* 4630 * array of 13 bds as appears in the eth xstorm context 4631 */ 4632struct eth_tx_bds_array { 4633 union eth_tx_bd_types bds[13]; 4634}; 4635 4636 4637/* 4638 * VLAN mode on TX BDs 4639 */ 4640enum eth_tx_vlan_type { 4641 X_ETH_NO_VLAN, 4642 X_ETH_OUTBAND_VLAN, 4643 X_ETH_INBAND_VLAN, 4644 X_ETH_FW_ADDED_VLAN, 4645 MAX_ETH_TX_VLAN_TYPE 4646}; 4647 4648 4649/* 4650 * Ethernet VLAN filtering mode in E1x 4651 */ 4652enum eth_vlan_filter_mode { 4653 ETH_VLAN_FILTER_ANY_VLAN, 4654 ETH_VLAN_FILTER_SPECIFIC_VLAN, 4655 ETH_VLAN_FILTER_CLASSIFY, 4656 MAX_ETH_VLAN_FILTER_MODE 4657}; 4658 4659 4660/* 4661 * MAC filtering configuration command header 4662 */ 4663struct mac_configuration_hdr { 4664 u8 length; 4665 u8 offset; 4666 __le16 client_id; 4667 __le32 echo; 4668}; 4669 4670/* 4671 * MAC address in list for ramrod 4672 */ 4673struct mac_configuration_entry { 4674 __le16 lsb_mac_addr; 4675 __le16 middle_mac_addr; 4676 __le16 msb_mac_addr; 4677 __le16 vlan_id; 4678 u8 pf_id; 4679 u8 flags; 4680#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) 4681#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 4682#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) 4683#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 4684#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) 4685#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 4686#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) 4687#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 4688#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) 4689#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 4690#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) 4691#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 4692 __le16 reserved0; 4693 __le32 clients_bit_vector; 4694}; 4695 4696/* 4697 * MAC filtering configuration command 4698 */ 4699struct mac_configuration_cmd { 4700 struct mac_configuration_hdr hdr; 4701 struct mac_configuration_entry config_table[64]; 4702}; 4703 4704 4705/* 4706 * Set-MAC command type (in E1x) 4707 */ 4708enum set_mac_action_type { 4709 T_ETH_MAC_COMMAND_INVALIDATE, 4710 T_ETH_MAC_COMMAND_SET, 4711 MAX_SET_MAC_ACTION_TYPE 4712}; 4713 4714 4715/* 4716 * Ethernet TPA Modes 4717 */ 4718enum tpa_mode { 4719 TPA_LRO, 4720 TPA_GRO, 4721 MAX_TPA_MODE}; 4722 4723 4724/* 4725 * tpa update ramrod data 4726 */ 4727struct tpa_update_ramrod_data { 4728 u8 update_ipv4; 4729 u8 update_ipv6; 4730 u8 client_id; 4731 u8 max_tpa_queues; 4732 u8 max_sges_for_packet; 4733 u8 complete_on_both_clients; 4734 u8 dont_verify_rings_pause_thr_flg; 4735 u8 tpa_mode; 4736 __le16 sge_buff_size; 4737 __le16 max_agg_size; 4738 __le32 sge_page_base_lo; 4739 __le32 sge_page_base_hi; 4740 __le16 sge_pause_thr_low; 4741 __le16 sge_pause_thr_high; 4742}; 4743 4744 4745/* 4746 * approximate-match multicast filtering for E1H per function in Tstorm 4747 */ 4748struct tstorm_eth_approximate_match_multicast_filtering { 4749 u32 mcast_add_hash_bit_array[8]; 4750}; 4751 4752 4753/* 4754 * Common configuration parameters per function in Tstorm 4755 */ 4756struct tstorm_eth_function_common_config { 4757 __le16 config_flags; 4758#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) 4759#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 4760#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) 4761#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 4762#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) 4763#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 4764#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) 4765#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 4766#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) 4767#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 4768#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) 4769#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 4770#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) 4771#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 4772 u8 rss_result_mask; 4773 u8 reserved1; 4774 __le16 vlan_id[2]; 4775}; 4776 4777 4778/* 4779 * MAC filtering configuration parameters per port in Tstorm 4780 */ 4781struct tstorm_eth_mac_filter_config { 4782 u32 ucast_drop_all; 4783 u32 ucast_accept_all; 4784 u32 mcast_drop_all; 4785 u32 mcast_accept_all; 4786 u32 bcast_accept_all; 4787 u32 vlan_filter[2]; 4788 u32 unmatched_unicast; 4789}; 4790 4791 4792/* 4793 * tx only queue init ramrod data 4794 */ 4795struct tx_queue_init_ramrod_data { 4796 struct client_init_general_data general; 4797 struct client_init_tx_data tx; 4798}; 4799 4800 4801/* 4802 * Three RX producers for ETH 4803 */ 4804struct ustorm_eth_rx_producers { 4805#if defined(__BIG_ENDIAN) 4806 u16 bd_prod; 4807 u16 cqe_prod; 4808#elif defined(__LITTLE_ENDIAN) 4809 u16 cqe_prod; 4810 u16 bd_prod; 4811#endif 4812#if defined(__BIG_ENDIAN) 4813 u16 reserved; 4814 u16 sge_prod; 4815#elif defined(__LITTLE_ENDIAN) 4816 u16 sge_prod; 4817 u16 reserved; 4818#endif 4819}; 4820 4821 4822/* 4823 * FCoE RX statistics parameters section#0 4824 */ 4825struct fcoe_rx_stat_params_section0 { 4826 __le32 fcoe_rx_pkt_cnt; 4827 __le32 fcoe_rx_byte_cnt; 4828}; 4829 4830 4831/* 4832 * FCoE RX statistics parameters section#1 4833 */ 4834struct fcoe_rx_stat_params_section1 { 4835 __le32 fcoe_ver_cnt; 4836 __le32 fcoe_rx_drop_pkt_cnt; 4837}; 4838 4839 4840/* 4841 * FCoE RX statistics parameters section#2 4842 */ 4843struct fcoe_rx_stat_params_section2 { 4844 __le32 fc_crc_cnt; 4845 __le32 eofa_del_cnt; 4846 __le32 miss_frame_cnt; 4847 __le32 seq_timeout_cnt; 4848 __le32 drop_seq_cnt; 4849 __le32 fcoe_rx_drop_pkt_cnt; 4850 __le32 fcp_rx_pkt_cnt; 4851 __le32 reserved0; 4852}; 4853 4854 4855/* 4856 * FCoE TX statistics parameters 4857 */ 4858struct fcoe_tx_stat_params { 4859 __le32 fcoe_tx_pkt_cnt; 4860 __le32 fcoe_tx_byte_cnt; 4861 __le32 fcp_tx_pkt_cnt; 4862 __le32 reserved0; 4863}; 4864 4865/* 4866 * FCoE statistics parameters 4867 */ 4868struct fcoe_statistics_params { 4869 struct fcoe_tx_stat_params tx_stat; 4870 struct fcoe_rx_stat_params_section0 rx_stat0; 4871 struct fcoe_rx_stat_params_section1 rx_stat1; 4872 struct fcoe_rx_stat_params_section2 rx_stat2; 4873}; 4874 4875 4876/* 4877 * The data afex vif list ramrod need 4878 */ 4879struct afex_vif_list_ramrod_data { 4880 u8 afex_vif_list_command; 4881 u8 func_bit_map; 4882 __le16 vif_list_index; 4883 u8 func_to_clear; 4884 u8 echo; 4885 __le16 reserved1; 4886}; 4887 4888struct c2s_pri_trans_table_entry { 4889 u8 val[MAX_VLAN_PRIORITIES]; 4890}; 4891 4892/* 4893 * cfc delete event data 4894 */ 4895struct cfc_del_event_data { 4896 u32 cid; 4897 u32 reserved0; 4898 u32 reserved1; 4899}; 4900 4901 4902/* 4903 * per-port SAFC demo variables 4904 */ 4905struct cmng_flags_per_port { 4906 u32 cmng_enables; 4907#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) 4908#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 4909#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) 4910#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 4911#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) 4912#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 4913#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) 4914#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 4915#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) 4916#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 4917 u32 __reserved1; 4918}; 4919 4920 4921/* 4922 * per-port rate shaping variables 4923 */ 4924struct rate_shaping_vars_per_port { 4925 u32 rs_periodic_timeout; 4926 u32 rs_threshold; 4927}; 4928 4929/* 4930 * per-port fairness variables 4931 */ 4932struct fairness_vars_per_port { 4933 u32 upper_bound; 4934 u32 fair_threshold; 4935 u32 fairness_timeout; 4936 u32 reserved0; 4937}; 4938 4939/* 4940 * per-port SAFC variables 4941 */ 4942struct safc_struct_per_port { 4943#if defined(__BIG_ENDIAN) 4944 u16 __reserved1; 4945 u8 __reserved0; 4946 u8 safc_timeout_usec; 4947#elif defined(__LITTLE_ENDIAN) 4948 u8 safc_timeout_usec; 4949 u8 __reserved0; 4950 u16 __reserved1; 4951#endif 4952 u8 cos_to_traffic_types[MAX_COS_NUMBER]; 4953 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; 4954}; 4955 4956/* 4957 * Per-port congestion management variables 4958 */ 4959struct cmng_struct_per_port { 4960 struct rate_shaping_vars_per_port rs_vars; 4961 struct fairness_vars_per_port fair_vars; 4962 struct safc_struct_per_port safc_vars; 4963 struct cmng_flags_per_port flags; 4964}; 4965 4966/* 4967 * a single rate shaping counter. can be used as protocol or vnic counter 4968 */ 4969struct rate_shaping_counter { 4970 u32 quota; 4971#if defined(__BIG_ENDIAN) 4972 u16 __reserved0; 4973 u16 rate; 4974#elif defined(__LITTLE_ENDIAN) 4975 u16 rate; 4976 u16 __reserved0; 4977#endif 4978}; 4979 4980/* 4981 * per-vnic rate shaping variables 4982 */ 4983struct rate_shaping_vars_per_vn { 4984 struct rate_shaping_counter vn_counter; 4985}; 4986 4987/* 4988 * per-vnic fairness variables 4989 */ 4990struct fairness_vars_per_vn { 4991 u32 cos_credit_delta[MAX_COS_NUMBER]; 4992 u32 vn_credit_delta; 4993 u32 __reserved0; 4994}; 4995 4996/* 4997 * cmng port init state 4998 */ 4999struct cmng_vnic { 5000 struct rate_shaping_vars_per_vn vnic_max_rate[4]; 5001 struct fairness_vars_per_vn vnic_min_rate[4]; 5002}; 5003 5004/* 5005 * cmng port init state 5006 */ 5007struct cmng_init { 5008 struct cmng_struct_per_port port; 5009 struct cmng_vnic vnic; 5010}; 5011 5012 5013/* 5014 * driver parameters for congestion management init, all rates are in Mbps 5015 */ 5016struct cmng_init_input { 5017 u32 port_rate; 5018 u16 vnic_min_rate[4]; 5019 u16 vnic_max_rate[4]; 5020 u16 cos_min_rate[MAX_COS_NUMBER]; 5021 u16 cos_to_pause_mask[MAX_COS_NUMBER]; 5022 struct cmng_flags_per_port flags; 5023}; 5024 5025 5026/* 5027 * Protocol-common command ID for slow path elements 5028 */ 5029enum common_spqe_cmd_id { 5030 RAMROD_CMD_ID_COMMON_UNUSED, 5031 RAMROD_CMD_ID_COMMON_FUNCTION_START, 5032 RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 5033 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 5034 RAMROD_CMD_ID_COMMON_CFC_DEL, 5035 RAMROD_CMD_ID_COMMON_CFC_DEL_WB, 5036 RAMROD_CMD_ID_COMMON_STAT_QUERY, 5037 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 5038 RAMROD_CMD_ID_COMMON_START_TRAFFIC, 5039 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 5040 RAMROD_CMD_ID_COMMON_SET_TIMESYNC, 5041 MAX_COMMON_SPQE_CMD_ID 5042}; 5043 5044/* 5045 * Per-protocol connection types 5046 */ 5047enum connection_type { 5048 ETH_CONNECTION_TYPE, 5049 TOE_CONNECTION_TYPE, 5050 RDMA_CONNECTION_TYPE, 5051 ISCSI_CONNECTION_TYPE, 5052 FCOE_CONNECTION_TYPE, 5053 RESERVED_CONNECTION_TYPE_0, 5054 RESERVED_CONNECTION_TYPE_1, 5055 RESERVED_CONNECTION_TYPE_2, 5056 NONE_CONNECTION_TYPE, 5057 MAX_CONNECTION_TYPE 5058}; 5059 5060 5061/* 5062 * Cos modes 5063 */ 5064enum cos_mode { 5065 OVERRIDE_COS, 5066 STATIC_COS, 5067 FW_WRR, 5068 MAX_COS_MODE 5069}; 5070 5071 5072/* 5073 * Dynamic HC counters set by the driver 5074 */ 5075struct hc_dynamic_drv_counter { 5076 u32 val[HC_SB_MAX_DYNAMIC_INDICES]; 5077}; 5078 5079/* 5080 * zone A per-queue data 5081 */ 5082struct cstorm_queue_zone_data { 5083 struct hc_dynamic_drv_counter hc_dyn_drv_cnt; 5084 struct regpair reserved[2]; 5085}; 5086 5087 5088/* 5089 * Vf-PF channel data in cstorm ram (non-triggered zone) 5090 */ 5091struct vf_pf_channel_zone_data { 5092 u32 msg_addr_lo; 5093 u32 msg_addr_hi; 5094}; 5095 5096/* 5097 * zone for VF non-triggered data 5098 */ 5099struct non_trigger_vf_zone { 5100 struct vf_pf_channel_zone_data vf_pf_channel; 5101}; 5102 5103/* 5104 * Vf-PF channel trigger zone in cstorm ram 5105 */ 5106struct vf_pf_channel_zone_trigger { 5107 u8 addr_valid; 5108}; 5109 5110/* 5111 * zone that triggers the in-bound interrupt 5112 */ 5113struct trigger_vf_zone { 5114#if defined(__BIG_ENDIAN) 5115 u16 reserved1; 5116 u8 reserved0; 5117 struct vf_pf_channel_zone_trigger vf_pf_channel; 5118#elif defined(__LITTLE_ENDIAN) 5119 struct vf_pf_channel_zone_trigger vf_pf_channel; 5120 u8 reserved0; 5121 u16 reserved1; 5122#endif 5123 u32 reserved2; 5124}; 5125 5126/* 5127 * zone B per-VF data 5128 */ 5129struct cstorm_vf_zone_data { 5130 struct non_trigger_vf_zone non_trigger; 5131 struct trigger_vf_zone trigger; 5132}; 5133 5134 5135/* 5136 * Dynamic host coalescing init parameters, per state machine 5137 */ 5138struct dynamic_hc_sm_config { 5139 u32 threshold[3]; 5140 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; 5141 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; 5142 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; 5143 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; 5144 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; 5145}; 5146 5147/* 5148 * Dynamic host coalescing init parameters 5149 */ 5150struct dynamic_hc_config { 5151 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]; 5152}; 5153 5154 5155struct e2_integ_data { 5156#if defined(__BIG_ENDIAN) 5157 u8 flags; 5158#define E2_INTEG_DATA_TESTING_EN (0x1<<0) 5159#define E2_INTEG_DATA_TESTING_EN_SHIFT 0 5160#define E2_INTEG_DATA_LB_TX (0x1<<1) 5161#define E2_INTEG_DATA_LB_TX_SHIFT 1 5162#define E2_INTEG_DATA_COS_TX (0x1<<2) 5163#define E2_INTEG_DATA_COS_TX_SHIFT 2 5164#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 5165#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 5166#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 5167#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 5168#define E2_INTEG_DATA_RESERVED (0x7<<5) 5169#define E2_INTEG_DATA_RESERVED_SHIFT 5 5170 u8 cos; 5171 u8 voq; 5172 u8 pbf_queue; 5173#elif defined(__LITTLE_ENDIAN) 5174 u8 pbf_queue; 5175 u8 voq; 5176 u8 cos; 5177 u8 flags; 5178#define E2_INTEG_DATA_TESTING_EN (0x1<<0) 5179#define E2_INTEG_DATA_TESTING_EN_SHIFT 0 5180#define E2_INTEG_DATA_LB_TX (0x1<<1) 5181#define E2_INTEG_DATA_LB_TX_SHIFT 1 5182#define E2_INTEG_DATA_COS_TX (0x1<<2) 5183#define E2_INTEG_DATA_COS_TX_SHIFT 2 5184#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 5185#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 5186#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 5187#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 5188#define E2_INTEG_DATA_RESERVED (0x7<<5) 5189#define E2_INTEG_DATA_RESERVED_SHIFT 5 5190#endif 5191#if defined(__BIG_ENDIAN) 5192 u16 reserved3; 5193 u8 reserved2; 5194 u8 ramEn; 5195#elif defined(__LITTLE_ENDIAN) 5196 u8 ramEn; 5197 u8 reserved2; 5198 u16 reserved3; 5199#endif 5200}; 5201 5202 5203/* 5204 * set mac event data 5205 */ 5206struct eth_event_data { 5207 u32 echo; 5208 u32 reserved0; 5209 u32 reserved1; 5210}; 5211 5212 5213/* 5214 * pf-vf event data 5215 */ 5216struct vf_pf_event_data { 5217 u8 vf_id; 5218 u8 reserved0; 5219 u16 reserved1; 5220 u32 msg_addr_lo; 5221 u32 msg_addr_hi; 5222}; 5223 5224/* 5225 * VF FLR event data 5226 */ 5227struct vf_flr_event_data { 5228 u8 vf_id; 5229 u8 reserved0; 5230 u16 reserved1; 5231 u32 reserved2; 5232 u32 reserved3; 5233}; 5234 5235/* 5236 * malicious VF event data 5237 */ 5238struct malicious_vf_event_data { 5239 u8 vf_id; 5240 u8 err_id; 5241 u16 reserved1; 5242 u32 reserved2; 5243 u32 reserved3; 5244}; 5245 5246/* 5247 * vif list event data 5248 */ 5249struct vif_list_event_data { 5250 u8 func_bit_map; 5251 u8 echo; 5252 __le16 reserved0; 5253 __le32 reserved1; 5254 __le32 reserved2; 5255}; 5256 5257/* function update event data */ 5258struct function_update_event_data { 5259 u8 echo; 5260 u8 reserved; 5261 __le16 reserved0; 5262 __le32 reserved1; 5263 __le32 reserved2; 5264}; 5265 5266 5267/* union for all event ring message types */ 5268union event_data { 5269 struct vf_pf_event_data vf_pf_event; 5270 struct eth_event_data eth_event; 5271 struct cfc_del_event_data cfc_del_event; 5272 struct vf_flr_event_data vf_flr_event; 5273 struct malicious_vf_event_data malicious_vf_event; 5274 struct vif_list_event_data vif_list_event; 5275 struct function_update_event_data function_update_event; 5276}; 5277 5278 5279/* 5280 * per PF event ring data 5281 */ 5282struct event_ring_data { 5283 struct regpair_native base_addr; 5284#if defined(__BIG_ENDIAN) 5285 u8 index_id; 5286 u8 sb_id; 5287 u16 producer; 5288#elif defined(__LITTLE_ENDIAN) 5289 u16 producer; 5290 u8 sb_id; 5291 u8 index_id; 5292#endif 5293 u32 reserved0; 5294}; 5295 5296 5297/* 5298 * event ring message element (each element is 128 bits) 5299 */ 5300struct event_ring_msg { 5301 u8 opcode; 5302 u8 error; 5303 u16 reserved1; 5304 union event_data data; 5305}; 5306 5307/* 5308 * event ring next page element (128 bits) 5309 */ 5310struct event_ring_next { 5311 struct regpair addr; 5312 u32 reserved[2]; 5313}; 5314 5315/* 5316 * union for event ring element types (each element is 128 bits) 5317 */ 5318union event_ring_elem { 5319 struct event_ring_msg message; 5320 struct event_ring_next next_page; 5321}; 5322 5323 5324/* 5325 * Common event ring opcodes 5326 */ 5327enum event_ring_opcode { 5328 EVENT_RING_OPCODE_VF_PF_CHANNEL, 5329 EVENT_RING_OPCODE_FUNCTION_START, 5330 EVENT_RING_OPCODE_FUNCTION_STOP, 5331 EVENT_RING_OPCODE_CFC_DEL, 5332 EVENT_RING_OPCODE_CFC_DEL_WB, 5333 EVENT_RING_OPCODE_STAT_QUERY, 5334 EVENT_RING_OPCODE_STOP_TRAFFIC, 5335 EVENT_RING_OPCODE_START_TRAFFIC, 5336 EVENT_RING_OPCODE_VF_FLR, 5337 EVENT_RING_OPCODE_MALICIOUS_VF, 5338 EVENT_RING_OPCODE_FORWARD_SETUP, 5339 EVENT_RING_OPCODE_RSS_UPDATE_RULES, 5340 EVENT_RING_OPCODE_FUNCTION_UPDATE, 5341 EVENT_RING_OPCODE_AFEX_VIF_LISTS, 5342 EVENT_RING_OPCODE_SET_MAC, 5343 EVENT_RING_OPCODE_CLASSIFICATION_RULES, 5344 EVENT_RING_OPCODE_FILTERS_RULES, 5345 EVENT_RING_OPCODE_MULTICAST_RULES, 5346 EVENT_RING_OPCODE_SET_TIMESYNC, 5347 MAX_EVENT_RING_OPCODE 5348}; 5349 5350/* 5351 * Modes for fairness algorithm 5352 */ 5353enum fairness_mode { 5354 FAIRNESS_COS_WRR_MODE, 5355 FAIRNESS_COS_ETS_MODE, 5356 MAX_FAIRNESS_MODE 5357}; 5358 5359 5360/* 5361 * Priority and cos 5362 */ 5363struct priority_cos { 5364 u8 priority; 5365 u8 cos; 5366 __le16 reserved1; 5367}; 5368 5369/* 5370 * The data for flow control configuration 5371 */ 5372struct flow_control_configuration { 5373 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 5374 u8 dcb_enabled; 5375 u8 dcb_version; 5376 u8 dont_add_pri_0_en; 5377 u8 reserved1; 5378 __le32 reserved2; 5379 u8 dcb_outer_pri[MAX_TRAFFIC_TYPES]; 5380}; 5381 5382 5383/* 5384 * 5385 */ 5386struct function_start_data { 5387 u8 function_mode; 5388 u8 allow_npar_tx_switching; 5389 __le16 sd_vlan_tag; 5390 __le16 vif_id; 5391 u8 path_id; 5392 u8 network_cos_mode; 5393 u8 dmae_cmd_id; 5394 u8 no_added_tags; 5395 __le16 reserved0; 5396 __le32 reserved1; 5397 u8 inner_clss_vxlan; 5398 u8 inner_clss_l2gre; 5399 u8 inner_clss_l2geneve; 5400 u8 inner_rss; 5401 __le16 vxlan_dst_port; 5402 __le16 geneve_dst_port; 5403 u8 sd_accept_mf_clss_fail; 5404 u8 sd_accept_mf_clss_fail_match_ethtype; 5405 __le16 sd_accept_mf_clss_fail_ethtype; 5406 __le16 sd_vlan_eth_type; 5407 u8 sd_vlan_force_pri_flg; 5408 u8 sd_vlan_force_pri_val; 5409 u8 c2s_pri_tt_valid; 5410 u8 c2s_pri_default; 5411 u8 reserved2[6]; 5412 struct c2s_pri_trans_table_entry c2s_pri_trans_table; 5413}; 5414 5415struct function_update_data { 5416 u8 vif_id_change_flg; 5417 u8 afex_default_vlan_change_flg; 5418 u8 allowed_priorities_change_flg; 5419 u8 network_cos_mode_change_flg; 5420 __le16 vif_id; 5421 __le16 afex_default_vlan; 5422 u8 allowed_priorities; 5423 u8 network_cos_mode; 5424 u8 lb_mode_en_change_flg; 5425 u8 lb_mode_en; 5426 u8 tx_switch_suspend_change_flg; 5427 u8 tx_switch_suspend; 5428 u8 echo; 5429 u8 update_tunn_cfg_flg; 5430 u8 inner_clss_vxlan; 5431 u8 inner_clss_l2gre; 5432 u8 inner_clss_l2geneve; 5433 u8 inner_rss; 5434 __le16 vxlan_dst_port; 5435 __le16 geneve_dst_port; 5436 u8 sd_vlan_force_pri_change_flg; 5437 u8 sd_vlan_force_pri_flg; 5438 u8 sd_vlan_force_pri_val; 5439 u8 sd_vlan_tag_change_flg; 5440 u8 sd_vlan_eth_type_change_flg; 5441 u8 reserved1; 5442 __le16 sd_vlan_tag; 5443 __le16 sd_vlan_eth_type; 5444 __le16 reserved0; 5445 __le32 reserved2; 5446}; 5447 5448/* 5449 * FW version stored in the Xstorm RAM 5450 */ 5451struct fw_version { 5452#if defined(__BIG_ENDIAN) 5453 u8 engineering; 5454 u8 revision; 5455 u8 minor; 5456 u8 major; 5457#elif defined(__LITTLE_ENDIAN) 5458 u8 major; 5459 u8 minor; 5460 u8 revision; 5461 u8 engineering; 5462#endif 5463 u32 flags; 5464#define FW_VERSION_OPTIMIZED (0x1<<0) 5465#define FW_VERSION_OPTIMIZED_SHIFT 0 5466#define FW_VERSION_BIG_ENDIEN (0x1<<1) 5467#define FW_VERSION_BIG_ENDIEN_SHIFT 1 5468#define FW_VERSION_CHIP_VERSION (0x3<<2) 5469#define FW_VERSION_CHIP_VERSION_SHIFT 2 5470#define __FW_VERSION_RESERVED (0xFFFFFFF<<4) 5471#define __FW_VERSION_RESERVED_SHIFT 4 5472}; 5473 5474/* 5475 * Dynamic Host-Coalescing - Driver(host) counters 5476 */ 5477struct hc_dynamic_sb_drv_counters { 5478 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; 5479}; 5480 5481 5482/* 5483 * 2 bytes. configuration/state parameters for a single protocol index 5484 */ 5485struct hc_index_data { 5486#if defined(__BIG_ENDIAN) 5487 u8 flags; 5488#define HC_INDEX_DATA_SM_ID (0x1<<0) 5489#define HC_INDEX_DATA_SM_ID_SHIFT 0 5490#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 5491#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5492#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 5493#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5494#define HC_INDEX_DATA_RESERVE (0x1F<<3) 5495#define HC_INDEX_DATA_RESERVE_SHIFT 3 5496 u8 timeout; 5497#elif defined(__LITTLE_ENDIAN) 5498 u8 timeout; 5499 u8 flags; 5500#define HC_INDEX_DATA_SM_ID (0x1<<0) 5501#define HC_INDEX_DATA_SM_ID_SHIFT 0 5502#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 5503#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5504#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 5505#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5506#define HC_INDEX_DATA_RESERVE (0x1F<<3) 5507#define HC_INDEX_DATA_RESERVE_SHIFT 3 5508#endif 5509}; 5510 5511 5512/* 5513 * HC state-machine 5514 */ 5515struct hc_status_block_sm { 5516#if defined(__BIG_ENDIAN) 5517 u8 igu_seg_id; 5518 u8 igu_sb_id; 5519 u8 timer_value; 5520 u8 __flags; 5521#elif defined(__LITTLE_ENDIAN) 5522 u8 __flags; 5523 u8 timer_value; 5524 u8 igu_sb_id; 5525 u8 igu_seg_id; 5526#endif 5527 u32 time_to_expire; 5528}; 5529 5530/* 5531 * hold PCI identification variables- used in various places in firmware 5532 */ 5533struct pci_entity { 5534#if defined(__BIG_ENDIAN) 5535 u8 vf_valid; 5536 u8 vf_id; 5537 u8 vnic_id; 5538 u8 pf_id; 5539#elif defined(__LITTLE_ENDIAN) 5540 u8 pf_id; 5541 u8 vnic_id; 5542 u8 vf_id; 5543 u8 vf_valid; 5544#endif 5545}; 5546 5547/* 5548 * The fast-path status block meta-data, common to all chips 5549 */ 5550struct hc_sb_data { 5551 struct regpair_native host_sb_addr; 5552 struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; 5553 struct pci_entity p_func; 5554#if defined(__BIG_ENDIAN) 5555 u8 rsrv0; 5556 u8 state; 5557 u8 dhc_qzone_id; 5558 u8 same_igu_sb_1b; 5559#elif defined(__LITTLE_ENDIAN) 5560 u8 same_igu_sb_1b; 5561 u8 dhc_qzone_id; 5562 u8 state; 5563 u8 rsrv0; 5564#endif 5565 struct regpair_native rsrv1[2]; 5566}; 5567 5568 5569/* 5570 * Segment types for host coaslescing 5571 */ 5572enum hc_segment { 5573 HC_REGULAR_SEGMENT, 5574 HC_DEFAULT_SEGMENT, 5575 MAX_HC_SEGMENT 5576}; 5577 5578 5579/* 5580 * The fast-path status block meta-data 5581 */ 5582struct hc_sp_status_block_data { 5583 struct regpair_native host_sb_addr; 5584#if defined(__BIG_ENDIAN) 5585 u8 rsrv1; 5586 u8 state; 5587 u8 igu_seg_id; 5588 u8 igu_sb_id; 5589#elif defined(__LITTLE_ENDIAN) 5590 u8 igu_sb_id; 5591 u8 igu_seg_id; 5592 u8 state; 5593 u8 rsrv1; 5594#endif 5595 struct pci_entity p_func; 5596}; 5597 5598 5599/* 5600 * The fast-path status block meta-data 5601 */ 5602struct hc_status_block_data_e1x { 5603 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; 5604 struct hc_sb_data common; 5605}; 5606 5607 5608/* 5609 * The fast-path status block meta-data 5610 */ 5611struct hc_status_block_data_e2 { 5612 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; 5613 struct hc_sb_data common; 5614}; 5615 5616 5617/* 5618 * IGU block operartion modes (in Everest2) 5619 */ 5620enum igu_mode { 5621 HC_IGU_BC_MODE, 5622 HC_IGU_NBC_MODE, 5623 MAX_IGU_MODE 5624}; 5625 5626 5627/* 5628 * IP versions 5629 */ 5630enum ip_ver { 5631 IP_V4, 5632 IP_V6, 5633 MAX_IP_VER 5634}; 5635 5636/* 5637 * Malicious VF error ID 5638 */ 5639enum malicious_vf_error_id { 5640 MALICIOUS_VF_NO_ERROR, 5641 VF_PF_CHANNEL_NOT_READY, 5642 ETH_ILLEGAL_BD_LENGTHS, 5643 ETH_PACKET_TOO_SHORT, 5644 ETH_PAYLOAD_TOO_BIG, 5645 ETH_ILLEGAL_ETH_TYPE, 5646 ETH_ILLEGAL_LSO_HDR_LEN, 5647 ETH_TOO_MANY_BDS, 5648 ETH_ZERO_HDR_NBDS, 5649 ETH_START_BD_NOT_SET, 5650 ETH_ILLEGAL_PARSE_NBDS, 5651 ETH_IPV6_AND_CHECKSUM, 5652 ETH_VLAN_FLG_INCORRECT, 5653 ETH_ILLEGAL_LSO_MSS, 5654 ETH_TUNNEL_NOT_SUPPORTED, 5655 MAX_MALICIOUS_VF_ERROR_ID 5656}; 5657 5658/* 5659 * Multi-function modes 5660 */ 5661enum mf_mode { 5662 SINGLE_FUNCTION, 5663 MULTI_FUNCTION_SD, 5664 MULTI_FUNCTION_SI, 5665 MULTI_FUNCTION_AFEX, 5666 MAX_MF_MODE 5667}; 5668 5669/* 5670 * Protocol-common statistics collected by the Tstorm (per pf) 5671 */ 5672struct tstorm_per_pf_stats { 5673 struct regpair rcv_error_bytes; 5674}; 5675 5676/* 5677 * 5678 */ 5679struct per_pf_stats { 5680 struct tstorm_per_pf_stats tstorm_pf_statistics; 5681}; 5682 5683 5684/* 5685 * Protocol-common statistics collected by the Tstorm (per port) 5686 */ 5687struct tstorm_per_port_stats { 5688 __le32 mac_discard; 5689 __le32 mac_filter_discard; 5690 __le32 brb_truncate_discard; 5691 __le32 mf_tag_discard; 5692 __le32 packet_drop; 5693 __le32 reserved; 5694}; 5695 5696/* 5697 * 5698 */ 5699struct per_port_stats { 5700 struct tstorm_per_port_stats tstorm_port_statistics; 5701}; 5702 5703 5704/* 5705 * Protocol-common statistics collected by the Tstorm (per client) 5706 */ 5707struct tstorm_per_queue_stats { 5708 struct regpair rcv_ucast_bytes; 5709 __le32 rcv_ucast_pkts; 5710 __le32 checksum_discard; 5711 struct regpair rcv_bcast_bytes; 5712 __le32 rcv_bcast_pkts; 5713 __le32 pkts_too_big_discard; 5714 struct regpair rcv_mcast_bytes; 5715 __le32 rcv_mcast_pkts; 5716 __le32 ttl0_discard; 5717 __le16 no_buff_discard; 5718 __le16 reserved0; 5719 __le32 reserved1; 5720}; 5721 5722/* 5723 * Protocol-common statistics collected by the Ustorm (per client) 5724 */ 5725struct ustorm_per_queue_stats { 5726 struct regpair ucast_no_buff_bytes; 5727 struct regpair mcast_no_buff_bytes; 5728 struct regpair bcast_no_buff_bytes; 5729 __le32 ucast_no_buff_pkts; 5730 __le32 mcast_no_buff_pkts; 5731 __le32 bcast_no_buff_pkts; 5732 __le32 coalesced_pkts; 5733 struct regpair coalesced_bytes; 5734 __le32 coalesced_events; 5735 __le32 coalesced_aborts; 5736}; 5737 5738/* 5739 * Protocol-common statistics collected by the Xstorm (per client) 5740 */ 5741struct xstorm_per_queue_stats { 5742 struct regpair ucast_bytes_sent; 5743 struct regpair mcast_bytes_sent; 5744 struct regpair bcast_bytes_sent; 5745 __le32 ucast_pkts_sent; 5746 __le32 mcast_pkts_sent; 5747 __le32 bcast_pkts_sent; 5748 __le32 error_drop_pkts; 5749}; 5750 5751/* 5752 * 5753 */ 5754struct per_queue_stats { 5755 struct tstorm_per_queue_stats tstorm_queue_statistics; 5756 struct ustorm_per_queue_stats ustorm_queue_statistics; 5757 struct xstorm_per_queue_stats xstorm_queue_statistics; 5758}; 5759 5760 5761/* 5762 * FW version stored in first line of pram 5763 */ 5764struct pram_fw_version { 5765 u8 major; 5766 u8 minor; 5767 u8 revision; 5768 u8 engineering; 5769 u8 flags; 5770#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) 5771#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 5772#define PRAM_FW_VERSION_STORM_ID (0x3<<1) 5773#define PRAM_FW_VERSION_STORM_ID_SHIFT 1 5774#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) 5775#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 5776#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) 5777#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 5778#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) 5779#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 5780}; 5781 5782 5783/* 5784 * Ethernet slow path element 5785 */ 5786union protocol_common_specific_data { 5787 u8 protocol_data[8]; 5788 struct regpair phy_address; 5789 struct regpair mac_config_addr; 5790 struct afex_vif_list_ramrod_data afex_vif_list_data; 5791}; 5792 5793/* 5794 * The send queue element 5795 */ 5796struct protocol_common_spe { 5797 struct spe_hdr hdr; 5798 union protocol_common_specific_data data; 5799}; 5800 5801/* The data for the Set Timesync Ramrod */ 5802struct set_timesync_ramrod_data { 5803 u8 drift_adjust_cmd; 5804 u8 offset_cmd; 5805 u8 add_sub_drift_adjust_value; 5806 u8 drift_adjust_value; 5807 u32 drift_adjust_period; 5808 struct regpair offset_delta; 5809}; 5810 5811/* 5812 * The send queue element 5813 */ 5814struct slow_path_element { 5815 struct spe_hdr hdr; 5816 struct regpair protocol_data; 5817}; 5818 5819 5820/* 5821 * Protocol-common statistics counter 5822 */ 5823struct stats_counter { 5824 __le16 xstats_counter; 5825 __le16 reserved0; 5826 __le32 reserved1; 5827 __le16 tstats_counter; 5828 __le16 reserved2; 5829 __le32 reserved3; 5830 __le16 ustats_counter; 5831 __le16 reserved4; 5832 __le32 reserved5; 5833 __le16 cstats_counter; 5834 __le16 reserved6; 5835 __le32 reserved7; 5836}; 5837 5838 5839/* 5840 * 5841 */ 5842struct stats_query_entry { 5843 u8 kind; 5844 u8 index; 5845 __le16 funcID; 5846 __le32 reserved; 5847 struct regpair address; 5848}; 5849 5850/* 5851 * statistic command 5852 */ 5853struct stats_query_cmd_group { 5854 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 5855}; 5856 5857 5858/* 5859 * statistic command header 5860 */ 5861struct stats_query_header { 5862 u8 cmd_num; 5863 u8 reserved0; 5864 __le16 drv_stats_counter; 5865 __le32 reserved1; 5866 struct regpair stats_counters_addrs; 5867}; 5868 5869 5870/* 5871 * Types of statistcis query entry 5872 */ 5873enum stats_query_type { 5874 STATS_TYPE_QUEUE, 5875 STATS_TYPE_PORT, 5876 STATS_TYPE_PF, 5877 STATS_TYPE_TOE, 5878 STATS_TYPE_FCOE, 5879 MAX_STATS_QUERY_TYPE 5880}; 5881 5882 5883/* 5884 * Indicate of the function status block state 5885 */ 5886enum status_block_state { 5887 SB_DISABLED, 5888 SB_ENABLED, 5889 SB_CLEANED, 5890 MAX_STATUS_BLOCK_STATE 5891}; 5892 5893 5894/* 5895 * Storm IDs (including attentions for IGU related enums) 5896 */ 5897enum storm_id { 5898 USTORM_ID, 5899 CSTORM_ID, 5900 XSTORM_ID, 5901 TSTORM_ID, 5902 ATTENTION_ID, 5903 MAX_STORM_ID 5904}; 5905 5906 5907/* 5908 * Taffic types used in ETS and flow control algorithms 5909 */ 5910enum traffic_type { 5911 LLFC_TRAFFIC_TYPE_NW, 5912 LLFC_TRAFFIC_TYPE_FCOE, 5913 LLFC_TRAFFIC_TYPE_ISCSI, 5914 MAX_TRAFFIC_TYPE 5915}; 5916 5917 5918/* 5919 * zone A per-queue data 5920 */ 5921struct tstorm_queue_zone_data { 5922 struct regpair reserved[4]; 5923}; 5924 5925 5926/* 5927 * zone B per-VF data 5928 */ 5929struct tstorm_vf_zone_data { 5930 struct regpair reserved; 5931}; 5932 5933/* Add or Subtract Value for Set Timesync Ramrod */ 5934enum ts_add_sub_value { 5935 TS_SUB_VALUE, 5936 TS_ADD_VALUE, 5937 MAX_TS_ADD_SUB_VALUE 5938}; 5939 5940/* Drift-Adjust Commands for Set Timesync Ramrod */ 5941enum ts_drift_adjust_cmd { 5942 TS_DRIFT_ADJUST_KEEP, 5943 TS_DRIFT_ADJUST_SET, 5944 TS_DRIFT_ADJUST_RESET, 5945 MAX_TS_DRIFT_ADJUST_CMD 5946}; 5947 5948/* Offset Commands for Set Timesync Ramrod */ 5949enum ts_offset_cmd { 5950 TS_OFFSET_KEEP, 5951 TS_OFFSET_INC, 5952 TS_OFFSET_DEC, 5953 MAX_TS_OFFSET_CMD 5954}; 5955 5956/* Tunnel Mode */ 5957enum tunnel_mode { 5958 TUNN_MODE_NONE, 5959 TUNN_MODE_VXLAN, 5960 TUNN_MODE_GRE, 5961 MAX_TUNNEL_MODE 5962}; 5963 5964 /* zone A per-queue data */ 5965struct ustorm_queue_zone_data { 5966 struct ustorm_eth_rx_producers eth_rx_producers; 5967 struct regpair reserved[3]; 5968}; 5969 5970 5971/* 5972 * zone B per-VF data 5973 */ 5974struct ustorm_vf_zone_data { 5975 struct regpair reserved; 5976}; 5977 5978 5979/* 5980 * data per VF-PF channel 5981 */ 5982struct vf_pf_channel_data { 5983#if defined(__BIG_ENDIAN) 5984 u16 reserved0; 5985 u8 valid; 5986 u8 state; 5987#elif defined(__LITTLE_ENDIAN) 5988 u8 state; 5989 u8 valid; 5990 u16 reserved0; 5991#endif 5992 u32 reserved1; 5993}; 5994 5995 5996/* 5997 * State of VF-PF channel 5998 */ 5999enum vf_pf_channel_state { 6000 VF_PF_CHANNEL_STATE_READY, 6001 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, 6002 MAX_VF_PF_CHANNEL_STATE 6003}; 6004 6005 6006/* 6007 * vif_list_rule_kind 6008 */ 6009enum vif_list_rule_kind { 6010 VIF_LIST_RULE_SET, 6011 VIF_LIST_RULE_GET, 6012 VIF_LIST_RULE_CLEAR_ALL, 6013 VIF_LIST_RULE_CLEAR_FUNC, 6014 MAX_VIF_LIST_RULE_KIND 6015}; 6016 6017 6018/* 6019 * zone A per-queue data 6020 */ 6021struct xstorm_queue_zone_data { 6022 struct regpair reserved[4]; 6023}; 6024 6025 6026/* 6027 * zone B per-VF data 6028 */ 6029struct xstorm_vf_zone_data { 6030 struct regpair reserved; 6031}; 6032 6033#endif /* BNX2X_HSI_H */ 6034